This document discusses FPGA configuration, including: 1. The FPGA configuration process involves clearing memory, initialization, loading configuration data, and startup. 2. Configuration modes like master serial, slave serial, and daisy chaining allow loading data from external sources. 3. Daisy chaining connects the configuration pins of multiple FPGAs together to load design data into all devices from a single source.

1. FPGA
Configuration
Majed Roohani
Amirali Sharifian
1
Spring-2013

2. Introduction
 What is configuration?
 Process for loading data into the FPGA
Configuration
Data
Source
Configuration
Data
Source
FPGAFPGA
Control
Logic
(optional)
Control
Logic
(optional)
2

3. Introduction
 When does configuration happen?
 On power-up
 On demand
 Why do FPGAs need to be configured?
 FPGA configuration memory is volatile
 What do I need to know about FPGA configuration?
 What happens during configuration
 How to set up various configuration modes and daisy-chains
 How to troubleshoot problems
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4. FPGA Configuration Process
 In order to understand the configuration
process, you need to know a little about:
 Configuration modes
 Configuration pins
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5. Configuration Modes
 Configuration modes define the specifics of how
the FPGA will interact with:
 The data source
 External control logic (if any)
 Many configuration modes to choose from
 Serial modes (Master and Slave)
 SelectMAP mode (Slave Parallel)
 Boundary scan mode (Slave) - always available
 Other Xilinx FPGA families have more configuration modes
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6. Configuration Modes
 Configuration pins (M0, M1, M2))
Note:
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7. Configuration Modes:
Serial Modes
 Data is loaded 1 bit per CCLK
 Master serial
 FPGA drives configuration clock
(CCLK)
 FPGA provides all control logic
 Slave serial
 External control logic required to
generate CCLK
 Microprocessor
 Xilinx serial download cable
 Another FPGA
Serial
Data
Serial
Data FPGAFPGA
CCLK
Data
Serial
Data
Serial
Data FPGAFPGA
Control
Logic
Control
Logic
Data
CCLK
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8. Configuration Modes:
SelectMAP Mode
 CCLK is driven by
external logic
 Data is loaded 1 byte
per CCLK
Byte-Wide
Data
Byte-Wide
Data FPGAFPGA
Control
Logic
Control
Logic
Data
CCLKControl Signals
Presentation
Name 8
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9. Configuration Modes:
Boundary Scan Mode
 External control logic required
 Control signals and data are
presented on the boundary
scan pins (TDI, TMS, TCK)
 Data is loaded 1 bit per TCK
 Always available
(independently on
M0,M1,M2)
Serial
Data
Serial
Data FPGAFPGA
Control
Logic
Control
Logic
Data
Control Signals
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10. Configuration Pins
 Specific pins on the FPGA are used during
configuration
 Some pins act differently depending on
configuration mode
 Example: CCLK is an output in some modes
and an input in others
 Some pins are only used in specific configuration
modes
 Example: CCLK is not used for Boundary Scan
mode
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11. Configuration Pin Descriptions
 Mode Pins (M0, M1, M2)
 Input pins that select which configuration
mode is being used
 PROGRAM
 Active low input that initiates configuration
 CCLK (Configuration Clock)
 Input or output, depending on configuration
mode
 Frequency up to 10MHz (see Data Book for
your device family)
 DIN
 Serial input for configuration data
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12. Configuration Pin Descriptions
 DOUT
 Output to next device in a daisy-chain
 Used in daisy-chains only
 INIT
 Open-drain bi-directional pin
 Error and Power Stabilization Flag
 DONE
 Open-drain bi-directional pin
 Indicates completion of configuration process
 Other pins are used for specific configuration
modes
 (i.e. JTAG Pins)
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13. Configuration Process
 Four major phases in the process:
 Configuration memory clear
 Initialization
 Load configuration data
 Start-up
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Configurati
on Memory
Clear
Configurati
on Memory
Clear
InitializationInitialization
Load
Configurati
on Data
Load
Configurati
on Data
Start-UpStart-Up

14. Configuration Process
Configuration Memory Clear Phase
 2 Way to configure
 Non-configuration I/O pins are
disabled with optional pull-up
resistors
 INIT and DONE pins are driven low
 FPGA memory is cleared
 PROGRAM is checked after each
memory pass
 Proceed to initialization
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Configuration at Power-
Up
Vcc AND Vccnt
High?
No
FPGA
Drives INIT and
DONE low
Configuration During
User Operation
User Pulls
PROGRAM
low
Yes
Clear
Configuration
Memory
User Holding
PROGRAM low?
Yes
Initialization
No

15. Configuration Process:
Initialization Phase
 INIT pin is released
 INIT may be held low externally to
delay configuration
 Mode pins are sampled
 Appropriate configuration pins
become active
 Proceed to load configuration
data
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Configuration
Memory
Clear
Release INIT
INIT
High?
Yes
Sample
Mode Pins
Load
Configuration
Data
No

16. Configuration Process:
Load Configuration Data Phase
 FPGA starts receiving data
 CRC is checked during the
data frames transmission
 If incorrect value received, INIT is
driven low and rest of data is
ignored
 If the CRC checks pass,
proceed to start-up
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Initialization
Load Data
Frames
CRC
Correct?
Yes
Start-UP
No
Pull INIT
Low

17. Configuration Process:
Start-up Phase
 Transition phase from configuration to
normal operation
 Order of events is user programmable
 Accessed through software options
 Default sequence is:
 DONE pin is released
 All I/O pins become active
 Global write enable released
 Global reset released
 FPGA is operational
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Load
Configuration
Data
Release
DONE
Activate
I/O Pins
Release
GWE
Release
GSR
FPGA is
Operational

18. Configuration Process:
Start-up Phase
 Default sequence is:
 DONE pin is released
 All I/O pins become active
 Global write enable released
 Global reset released
 Another useful sequence is “Sync to
DONE”
 Useful for multiple FPGA configuration
(Daisy chain)
 Configuration option
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19. Master Serial Mode
 All mode pins tied low
 FPGA drives CCLK as an
output
 Data stream loaded 1 bit at
a time
 Use when data stream is
stored in a serial PROM
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20. Slave Serial Mode
 All mode pins tied high
 FPGA receives CCLK as an
input
 Data stream loaded 1 bit at
a time
 Use with the Xilinx serial
download cable
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21. What Is a Daisy-Chain?
 Multiple FPGAs connected in series for
configuration
 Allows configuration of many devices from a single data
source
 Minimal board traces
 First device in the chain can be in master serial or
slave serial mode
 All other devices must be in slave serial mode
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22. Daisy-Chain Question
 How do you think these FPGAs could be connected to
form a Daisy-chain?
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23. Daisy-Chain Answer
 Connect all PROGRAM, CCLK and DONE pins together
 Connect each DOUT to the DIN of next device
 Recommend connecting INIT pins, but not required
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24. Creating a Daisy-Chain
 Connect PROGRAM pins
 Required so that all FPGAs will reprogram together
 Connect CCLK pins
 Required so that all FPGAs are synchronized with each other and
with the configuration data
 Connect DONE pins
 Required so that all FPGAs start-up together
 Connect each DOUT to the DIN of next device
 Required to allow each FPGA to receive configuration data
 Connect INIT pins
 Recommended to create a single error flag, but not required
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25. How a Daisy-Chain Works
 First FPGA in the chain is configured first
 Keeps DOUT high until its configuration memory is full
 Then data is passed to the next device in the chain
 Start-up sequence occurs after all devices are
configured
 FPGA devices pause after internally releasing DONE, and
continue when DONE externally goes high
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26. Xilinx In-System Programming
Using an
Embedded Microcontroller
 Use XAPP 058(v 4.1)
 Virtex® series
 Spartan® series
 CoolRunner® series
 XC9500 series
 Platform Flash PROM family
 XC18V00 family
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27. important benefits of in-system
programmability
 Reduces device handling costs and time to market
 Saves the expense of laying out new PC boards
 Allows remote maintenance, modification, and testing
 Increases the life span and functionality of products
 Enables unique, customer-specific features
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28. Microcontroller and JTAG
Chain Schematic
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29. XSVF File Generation Flow to
Embedded System
33

30. C-code and header files
 lenval.c
 micro.c
 ports.c
 lenval.h
 micro.h
 ports.h
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31. Configuration PROM
Programming File Creation
Storage Flow
35

32. CPLD Programming File
Creation and Storage Flow
36

33. FPGA Programming File
Creation and Storage Flow
37

34. Selected iMPACT Batch
Command
38

35. Using the iMPACT GUI to
Create XSVF Files
39

36. Write XSVF file to selected
Device
40

37. IMPACT batch command
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38. Summary
 Field programmable devices are configured on power-up
from an external data source
 The phases of the configuration process are:
 Configuration memory clear
 Initialization
 Load configuration data
 Start-up
 Master serial and slave serial are the simplest configuration
modes
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