This document presents a summary of a presentation on applying FPGAs for motor speed control. It was delivered by five students from the Electrical Engineering department at the University College of Engineering in Rajasthan, India. The presentation covered FPGA introductions, applications, structures, programming, and using an FPGA with an intelligent power module and motor to observe waveforms for motor speed control. It concluded that FPGAs provide flexibility for prototyping and application in areas like automotive, consumer electronics, and industrial controls.
Field Programmable Gate Array (FPGA) contains ten thousand to more than a million logic gates with programmable interconnection. Programmable interconnections are available for users or designers to perform given functions easily.How FPGAs are used in Space are briefly described in this slide.
Field-programmable gate array\
only for these students that are intrested in Field-programmable gate array
field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a customer or a designer after manufacturing – hence "field-programmable". The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application-specific integrated circuit (ASIC). (Circuit diagrams were previously used to specify the configuration, as they were for ASICs
The FPGA industry sprouted from programmable read-only memory (PROM) and programmable logic devices (PLDs). PROMs and PLDs both had the option of being programmed in batches in a factory or in the field (field-programmable). However, programmable logic was hard-wired between logic gates.[6]
In the late 1980s, the Naval Surface Warfare Center funded an experiment proposed by Steve Casselman to develop a computer that would implement 600,000 reprogrammable gates. Casselman was successful and a patent related to the system was issued in 1992.[6]
Some of the industry's foundational concepts and technologies for programmable logic arrays, gates, and logic blocks are founded in patents awarded to David W. Page and LuVerne R. Peterson in 1985.
Complex Programmable Logic Device (CPLD) Architecture and Its Applicationselprocus
A CPLD (complex programmable logic device) chip includes several circuit blocks on a single chip with inside wiring resources to attach the circuit blocks. Each circuit block is comparable to a PLA or a PAL.
Field Programmable Gate Array (FPGA) contains ten thousand to more than a million logic gates with programmable interconnection. Programmable interconnections are available for users or designers to perform given functions easily.How FPGAs are used in Space are briefly described in this slide.
Field-programmable gate array\
only for these students that are intrested in Field-programmable gate array
field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a customer or a designer after manufacturing – hence "field-programmable". The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application-specific integrated circuit (ASIC). (Circuit diagrams were previously used to specify the configuration, as they were for ASICs
The FPGA industry sprouted from programmable read-only memory (PROM) and programmable logic devices (PLDs). PROMs and PLDs both had the option of being programmed in batches in a factory or in the field (field-programmable). However, programmable logic was hard-wired between logic gates.[6]
In the late 1980s, the Naval Surface Warfare Center funded an experiment proposed by Steve Casselman to develop a computer that would implement 600,000 reprogrammable gates. Casselman was successful and a patent related to the system was issued in 1992.[6]
Some of the industry's foundational concepts and technologies for programmable logic arrays, gates, and logic blocks are founded in patents awarded to David W. Page and LuVerne R. Peterson in 1985.
Complex Programmable Logic Device (CPLD) Architecture and Its Applicationselprocus
A CPLD (complex programmable logic device) chip includes several circuit blocks on a single chip with inside wiring resources to attach the circuit blocks. Each circuit block is comparable to a PLA or a PAL.
Traditional vs. SoC FPGA Design Flow A Video Pipeline Case StudyAltera Corporation
This presentation compares the impact of traditional FPGA engineering design flow to one employed with an SoC FPGA. The two approaches will be contrasted in terms of their impacts on system architecture design, debugging, risk mitigation, system integration, bring-up, feature enhancements, design obsolescence, and engineering effort. A case study is presented that explores these impacts within a video pipeline development effort.
This presentation gives an overview of FPGA devices. An FPGA is a device that contains a matrix of re-configurable gate array logic circuitry. When a FPGA is configured, the internal circuitry is connected in a way that creates a hardware implementation of the software application.
FPGA devices can deliver the performance and reliability of dedicated hardware circuitry.
In this presentation we described implementation of Digital Signal processing on FPGA. If you still have any query about Digital Signal processing on FPGA then feel free to contact us at:
http://www.siliconmentor.com/
This is a presentation on FPGA from my 3rd year academics which was the field of my mini project/seminar in the same. Main emphasis is laid on the application of FPGA in DSP domain
FROM FPGA TO ASIC IMPLEMENTATION OF AN OPENRISC BASED SOC FOR VOIP APPLICATIONieijjournal
ASIC (Application Specific Integrated Circuit) design verification takes as long as the designers take to describe, synthesis and implement the design. The hybrid approach, where the design is first prototyped on an FPGA (Field-Programmable Gate Array) platform for functional validation and then implemented as
an ASIC allows earlier defect detection in the design process and thus allows a significant time saving. This paper deals with a CMOS standard-cell ASIC implementation of a SoC (System on Chip) based on the OpenRISC processor for Voice over IP (VoIP) application; where a hybrid approach is adopted. The
architecture of the design is mainly based on the reuse of IPs cores described at the RTL level. This RTL code is technology-independent; hence the design can be ported easily from FPGA to ASIC. Results show that the SoC occupied the area of 2.64mm². Regarding the power consumption, RTL power estimation is given.
FROM FPGA TO ASIC IMPLEMENTATION OF AN OPENRISC BASED SOC FOR VOIP APPLICATIONieijjournal1
ASIC (Application Specific Integrated Circuit) design verification takes as long as the designers take to
describe, synthesis and implement the design. The hybrid approach, where the design is first prototyped on
an FPGA (Field-Programmable Gate Array) platform for functional validation and then implemented as
an ASIC allows earlier defect detection in the design process and thus allows a significant time saving.
This paper deals with a CMOS standard-cell ASIC implementation of a SoC (System on Chip) based on the
OpenRISC processor for Voice over IP (VoIP) application; where a hybrid approach is adopted. The
architecture of the design is mainly based on the reuse of IPs cores described at the RTL level. This RTL
code is technology-independent; hence the design can be ported easily from FPGA to ASIC. Results show
that the SoC occupied the area of 2.64mm². Regarding the power consumption, RTL power estimation is
given.
FROM FPGA TO ASIC IMPLEMENTATION OF AN OPENRISC BASED SOC FOR VOIP APPLICATIONieijjournal
ASIC (Application Specific Integrated Circuit) design verification takes as long as the designers take to describe, synthesis and implement the design. The hybrid approach, where the design is first prototyped on an FPGA (Field-Programmable Gate Array) platform for functional validation and then implemented as
an ASIC allows earlier defect detection in the design process and thus allows a significant time saving.
This paper deals with a CMOS standard-cell ASIC implementation of a SoC (System on Chip) based on the
OpenRISC processor for Voice over IP (VoIP) application; where a hybrid approach is adopted. The
architecture of the design is mainly based on the reuse of IPs cores described at the RTL level. This RTL code is technology-independent; hence the design can be ported easily from FPGA to ASIC.
Traditional vs. SoC FPGA Design Flow A Video Pipeline Case StudyAltera Corporation
This presentation compares the impact of traditional FPGA engineering design flow to one employed with an SoC FPGA. The two approaches will be contrasted in terms of their impacts on system architecture design, debugging, risk mitigation, system integration, bring-up, feature enhancements, design obsolescence, and engineering effort. A case study is presented that explores these impacts within a video pipeline development effort.
This presentation gives an overview of FPGA devices. An FPGA is a device that contains a matrix of re-configurable gate array logic circuitry. When a FPGA is configured, the internal circuitry is connected in a way that creates a hardware implementation of the software application.
FPGA devices can deliver the performance and reliability of dedicated hardware circuitry.
In this presentation we described implementation of Digital Signal processing on FPGA. If you still have any query about Digital Signal processing on FPGA then feel free to contact us at:
http://www.siliconmentor.com/
This is a presentation on FPGA from my 3rd year academics which was the field of my mini project/seminar in the same. Main emphasis is laid on the application of FPGA in DSP domain
FROM FPGA TO ASIC IMPLEMENTATION OF AN OPENRISC BASED SOC FOR VOIP APPLICATIONieijjournal
ASIC (Application Specific Integrated Circuit) design verification takes as long as the designers take to describe, synthesis and implement the design. The hybrid approach, where the design is first prototyped on an FPGA (Field-Programmable Gate Array) platform for functional validation and then implemented as
an ASIC allows earlier defect detection in the design process and thus allows a significant time saving. This paper deals with a CMOS standard-cell ASIC implementation of a SoC (System on Chip) based on the OpenRISC processor for Voice over IP (VoIP) application; where a hybrid approach is adopted. The
architecture of the design is mainly based on the reuse of IPs cores described at the RTL level. This RTL code is technology-independent; hence the design can be ported easily from FPGA to ASIC. Results show that the SoC occupied the area of 2.64mm². Regarding the power consumption, RTL power estimation is given.
FROM FPGA TO ASIC IMPLEMENTATION OF AN OPENRISC BASED SOC FOR VOIP APPLICATIONieijjournal1
ASIC (Application Specific Integrated Circuit) design verification takes as long as the designers take to
describe, synthesis and implement the design. The hybrid approach, where the design is first prototyped on
an FPGA (Field-Programmable Gate Array) platform for functional validation and then implemented as
an ASIC allows earlier defect detection in the design process and thus allows a significant time saving.
This paper deals with a CMOS standard-cell ASIC implementation of a SoC (System on Chip) based on the
OpenRISC processor for Voice over IP (VoIP) application; where a hybrid approach is adopted. The
architecture of the design is mainly based on the reuse of IPs cores described at the RTL level. This RTL
code is technology-independent; hence the design can be ported easily from FPGA to ASIC. Results show
that the SoC occupied the area of 2.64mm². Regarding the power consumption, RTL power estimation is
given.
FROM FPGA TO ASIC IMPLEMENTATION OF AN OPENRISC BASED SOC FOR VOIP APPLICATIONieijjournal
ASIC (Application Specific Integrated Circuit) design verification takes as long as the designers take to describe, synthesis and implement the design. The hybrid approach, where the design is first prototyped on an FPGA (Field-Programmable Gate Array) platform for functional validation and then implemented as
an ASIC allows earlier defect detection in the design process and thus allows a significant time saving.
This paper deals with a CMOS standard-cell ASIC implementation of a SoC (System on Chip) based on the
OpenRISC processor for Voice over IP (VoIP) application; where a hybrid approach is adopted. The
architecture of the design is mainly based on the reuse of IPs cores described at the RTL level. This RTL code is technology-independent; hence the design can be ported easily from FPGA to ASIC.
Design and Development of Artix-7 FPGAbased Educational BoardIJERA Editor
This paper proposes a new approach that makes it possible for every student to perform experiments of developing and designing a board within limited time available for the course. An educational FPGA board and respective interface are also discussed. The board is a low-cost and high-performance Single Board Computer built around the Xilinx Artix-7 FPGA family XC7Z010 chip. This design provides a hardware implementation and algorithm verification platform for high-speed digital signal processing system.
Programmable logic controller performance enhancement by field programmable g...ISA Interchange
PLC, the core element of modern automation systems, due to serial execution, exhibits limitations like slow speed and poor scan time. Improved PLC design using FPGA has been proposed based on parallel execution mechanism for enhancement of performance and flexibility. Modelsim as simulation platform and VHDL used to translate, integrate and implement the logic circuit in FPGA. Xilinx’s Spartan kit for implementation-testing and VB has been used for GUI development. Salient merits of the design include cost-effectiveness, miniaturization, user-friendliness, simplicity, along with lower power consumption, smaller scan time and higher speed. Various functionalities and applications like typical PLC and industrial alarm annunciator have been developed and successfully tested. Results of simulation, design and implementation have been reported.
The Field Programmable Gate Array (FPGA) industry is expanding both in market share and in innovation. The tailored FPGA features make them a better choice to include FPGA in an increasing number of applications in the upcoming years. A constant development of FPGA technology has led to minimize the gap of performance levels between FPGA and Application Specific Integrated Circuit (ASIC). Hence, in recent years, FPGA based platforms are proven more attractive than ASICs since their performance is high in addition to the low cost of the development process and short time to market. Therefore, nowadays, FPGA is highly attractive for a huge range of applications in communications, computing, avionics, security, automotive and consumer electronics. Field Programmable Gate Array industry has shown a steady growth with a market prediction value of USD 9 billion by 2023. Currently, the FPGA companies started growing in reserch areas such as Artifitial Intelligence (AI), Internet of Thing (IoT) and LIght Detection and Ranging (LIDAR). The aim of this paper is to review the developments in FPGA.
1. Guide:-
Dr. D.K. Palwalia
(Associate Professor)
(EE Department)
Delivered by:-
Nisha Verma (10/034)
Pawan Garg (10/037)
Prachi (10/039)
Priyesh Vijayvergiya (10/041)
Rajkumar Meena (11/653)
(Electrical Engineering)
UNIVERSITY COLLEGE OF ENGINEERING
RAJASTHAN TECHNICAL UNIVERSITY, KOTA
A
PRESENTATION
ON
APPLICATION OF FPGA FOR
SPEED CONTROL OF MOTOR
2. 1. FPGA-Introduction
2. Why do we need FPGA
3. Structure of FPGA (Xilinx)
5. Nomenclature
6. Spartan 6 FPGA Kit – XC6SLX25-FT256
7. FPGA Programming
8. IPM – Intelligent Power Module
9. FPGA + IPM + MOTOR
10. Waveform observed
11. Applications of FPGA
12. Conclusion
13. References
3. FPGA chips handle dense logic and memory elements offering very high logic capacity
Uncommitted logic blocks are replicated in an FPGA with interconnects and I/O blocks
A field-programmable gate array (FPGA) is an integrated circuit designed to
be configured by a customer or a designer after manufacturing – hence "field-
programmable
FPGA’s contain lots of building blocks (ports, logic, …) with a complete
interconnection structure . By programming these connections, different logical
blocks or slices can be linked to obtain the desired circuit.
The FPGA industry sprouted from programmable read-only memory (PROM) and
programmable logic devices (PLDs). Xilinx and Altera are the current FPGA market
leaders .
4. Before Programmable Logic?
Fixed hardware = Fixed usability
Limited flexibility only possible by adding software support, for example
processors.
Upgrade or alteration in hardware logic was not guaranteed.
An upgrade meant a completely new system.
With FPGAs
Reprogrammable Logic reusability
Lower Non-Recurring Engineering (NRE) Cost
Good for Prototyping
Less Time to Market
Can act as a testing device for other digital circuits
Economical to be used for small volumes of products
Students can understand digital design concepts in a better way by designing their
custom logic
8. To define the behavior of the FPGA, the user provides a hardware
description language (HDL) or a schematic design. The HDL form is
more suited to work with large structures because it's possible to
just specify them numerically rather than having to draw every piece
by hand.
VHDL (VHSIC Hardware Description Language) is a hardware
description language used in electronic design automation to
describe digital and mixed-signal systems such as field-
programmable gate arrays and integrated circuits. VHDL can also be
used as a general purpose parallel programming language.
9. Step - by - Step Process
Choice of language (Verilog, VHDL)
Architectural design
Editing programs
Compiling programs
Synthesizing programs (.EDIF)
Placing and routing programs (.VO, .SDF, .TTF)
Loading programs to FPGA
Debugging FPGA programs
Documenting programs
Delivering programs
10.
11. • It work as DC-DC Converter (Chopper) or DC-AC Converter (Inverter).
It works using a IGBT based IPM and works on basis of software from
DSP Processor. The power module can be used for studying the operation
of chopper, single phase and three phase inverter and speed control of
single phase and three phase induction motor , etc.
• They are advanced hybrid power devices that combine high speed, low
loss IGBTs with optimized gate drive and protection circuitry. Highly
effective over-current and short-circuit protection is realized through the
use of advanced current sense IGBT chips that allow continuous monitoring
of power device current.
• IPM has been optimized for minimum switching losses in order to meet
industry demands for acoustically noiseless inverters with carrier
frequencies up to 20KHz.
IPM
19. 1. ASIC Prototyping
2. Automotive
3. Broadcast:
4. Consumer Electronics
5. Distributed Monetary Systems
6. Data Center
7. High Performance Computing
8. Industrial
9. Medical
10. Scientific Instruments
11. Security
12. Video & Image Processing
13. Wired Communication
14. Wireless Communication
20. The flexibility of FPGAs gives them a distinct advantage over other
programmable logic devices on the market. The advantage is most
apparent in application where time to market concerns are paramount.
Because FPGAs are reprogrammable and can implement any sort of logic
circuit, designs can be modified after initial implementation. With one
time programmable technologies such as AISCs, logic is set at the factory
and no changes can be made after manufacture . The drawbacks to FPGA
use involve speed and space. Switching gate resistances and capacitances
make for slow logic and poor logic density.
21. 1. www.optimagic.com
2. Brown 1992, Field Programmable Gate Arrays, Kluwer Academic Publishers
3. Bostock 1996, FPGAs and Programmable LSI: a Designers Handbook, Oxford:
Butterworth-Hieneman
4. Wakerly 2000, Digital Design: Principals and Practice
5. www.xilinx.com