EVALUATION OF OPTICALLY ILLUMINATED MOSFET CHARACTERISTICS BY TCAD SIMULATIONVLSICS Design
In this paper we report effect of optical illumination on Silicon MOSFET. The MOSFET has been studied in
respect of current voltage, transconductance admittance and scattering parameters. Gain analysis of the
Silicon MOSFET is done in dark and under optical illumination. The device is fabricated using ATHENA™
process simulator and the device simulation is performed using ATLAS™ from SILVACO international.
The simulation results indicate potential of MOSFET as optically sensitive structure which can be used
for increase in data transmission/reception rates, reduction of interconnect delays, elimination of clock
skew, or as a photodetector for optoelectronic applications at low and radio frequency.
Design and test challenges in Nano-scale analog and mixed CMOS technology VLSICS Design
The continuous increase of integration densities in Complementary Metal–Oxide–Semiconductor (CMOS) technology has driven the rapid growth of very large scale integrated (VLSI) circuit for today's high-tech electronics industries from consumer products to telecommunications and computers. As CMOS technologies are scaled down into the nanometer range, analog and mixed integrated circuit (IC) design and testing have become a real challenge to ensure the functionality and quality of the product. The first part of the paper presents the CMOS technology scaling impact on design and reliability for consumer and critical applications. We then propose a discussion on the role and challenges of testing analog and mixed devices in the nano-scale era. Finally we present the IDDQ testing technique used to detect the most likely defects of bridging type occurring in analog CMOS circuits during the manufacturing process and creating a resistive path between VDD supply and the ground. To prove the efficiency of the proposed technique we design a CMOS 90nm operational amplifier (Opamp) and a Built in Current Sensor (BICS) to validate the technique and correlate it with post layout simulation results.
EVALUATION OF OPTICALLY ILLUMINATED MOSFET CHARACTERISTICS BY TCAD SIMULATIONVLSICS Design
In this paper we report effect of optical illumination on Silicon MOSFET. The MOSFET has been studied in
respect of current voltage, transconductance admittance and scattering parameters. Gain analysis of the
Silicon MOSFET is done in dark and under optical illumination. The device is fabricated using ATHENA™
process simulator and the device simulation is performed using ATLAS™ from SILVACO international.
The simulation results indicate potential of MOSFET as optically sensitive structure which can be used
for increase in data transmission/reception rates, reduction of interconnect delays, elimination of clock
skew, or as a photodetector for optoelectronic applications at low and radio frequency.
Design and test challenges in Nano-scale analog and mixed CMOS technology VLSICS Design
The continuous increase of integration densities in Complementary Metal–Oxide–Semiconductor (CMOS) technology has driven the rapid growth of very large scale integrated (VLSI) circuit for today's high-tech electronics industries from consumer products to telecommunications and computers. As CMOS technologies are scaled down into the nanometer range, analog and mixed integrated circuit (IC) design and testing have become a real challenge to ensure the functionality and quality of the product. The first part of the paper presents the CMOS technology scaling impact on design and reliability for consumer and critical applications. We then propose a discussion on the role and challenges of testing analog and mixed devices in the nano-scale era. Finally we present the IDDQ testing technique used to detect the most likely defects of bridging type occurring in analog CMOS circuits during the manufacturing process and creating a resistive path between VDD supply and the ground. To prove the efficiency of the proposed technique we design a CMOS 90nm operational amplifier (Opamp) and a Built in Current Sensor (BICS) to validate the technique and correlate it with post layout simulation results.
Any form of education in an engineering or science discipline is incomplete without a means of testing and appreciating theories learned in class. The ability to carry out experimentation demonstrating theories through laboratory work is an integral part of an engineering, science and technology education. In laboratories, students can learn how to process real data, understand and appreciate discrepancies between their observations and the predictions according to theories. Not only do students appreciate those discrepancies, they learn how to make compromises to minimize the imperfections of their observations. This is a valuable skill for an engineer to have as engineers are problem solvers.
Modelling of next zen memory cell using low power consuming high speed nano d...eSAT Journals
Abstract Hybrid SET-CMOS circuits which syndicate the assets of both the SET [Single Electron Transistor] and CMOS depicts highest possibilities to be incorporated in practical implementation for future low power VLSI/ULSI configurations. The proposed work is an attempt based on SET-CMOS hybrid circuit to realize the next gen simple Memory Cell. The authors adhered to MIB model for SET and BSIM4 model for CMOS in realizing the complex cell. The maneuver of the proposed circuit is verified subsequently in standard environment. The outcomes are in good trade off with the conventional statistics of existing memory cell. Keywords: SET, SED, Hybrid CMOS-SET, MIB and Memory Cell
Design and optimization of a new compact 2.4 GHz-bandpass filter using DGS te...TELKOMNIKA JOURNAL
The objective of this work is the study, the design and the optimization of an innovative structure of a network of coupled copper metal lines deposited on the upper surface of a R04003 type substrate of height 0.813 with a ground deformed by slots (DGS). This structure is designed in an optimal configuration for use in the design of narrowband bandpass filter for wireless communication systems (WLAN), the aim of use the defected ground structure is to remove the unwanted harmonics in the rejection band, the simulation results obtained from this structure using CST software show a very high selectivity of the designed filter, a very low level of losses (less than-0.45 dB) with a size overall size of 43.5x34.3 mm.
Microstructure anlaysis and enhancement of nodular cast iron using digital im...eSAT Journals
Abstract Digital image processing is the technique to process pixel variations on digital images. This paper employs the digital image processing procedure for microstructure analysis and enhancement of nodular cast iron properties inorder to determine the quality factors. This processing made to sharpen and enhance the microstructure before quantitative analysis. This analysis taken in the analog form of nodular cast iron was performed manually such that, it is time consuming for multiple set of images. To avoid this criteria probably, Digital Image Processing techniques are being used. Often the nodular cast iron images are corrupted or defected during transmission by impulse noise which is often filtered using median filters. In this paper, some of processing steps as pre-processing, segmentation, filtering process and edge detection are done on these images for effective and lossless transmission ensuring the counting of nodules in microstructure and detailed study of grain properties that correlates with the mechanical properties such as ductility, malleability and brittleness. Only 30% restoration of image applicable to an acceptable level is limited. A new filtering method – Resolution Based Median Filter (RBMF) is proposed which achieves more than 95% restoration of nodular cast iron images to an acceptable level. This method optimizes further microstructure analysis of grain smoothening and grain boundary detection using finite element simulation model by varying the intensity level of images. Keywords – Digital Image Processing, Material Microstructure, Edge Detection, Grain Boundary, Resolution Based Median Filter (RBMF).
EFFECTIVE PEEC MODELING OF TRANSMISSION LINES STRUCTURES USING A SELECTIVE ME...EEIJ journal
The transmission lines structures are quite common in the system of electromagnetic compatibility (EMC)
analysis. The increasing complexities of physical structures make electromagnetic modeling an
increasingly tough task, and computational efficiency is desirable. In this paper, a novel selective mesh
approach is presented for partial element equivalent circuit (PEEC) modeling where intense coupling parts
are meshed while the remaining parts are eliminated. With the proposed approach, the meshed ground
plane is dependent on the length and height of the above transmission lines. Relevant compact formulae for
determining mesh boundaries are deduced, and a procedure of general mesh generation is also given. A
numerical example is presented, and a validation check is accomplished, showing that the approach leads
to a significant reduction in unknowns and thus computation time and consumed memories, while
preserving the sufficient precision. This approach is especially useful for modeling the electromagnetic
coupling of transmission lines and reference ground, and it may also be beneficial for other equivalent
circuit modeling techniques.
3-D ICs are an attractive chip architecture that can alleviate the interconnect related problems such as delay and power dissipation and can also facilitate integration of heterogeneous technologies in one chip (SoC).
Any form of education in an engineering or science discipline is incomplete without a means of testing and appreciating theories learned in class. The ability to carry out experimentation demonstrating theories through laboratory work is an integral part of an engineering, science and technology education. In laboratories, students can learn how to process real data, understand and appreciate discrepancies between their observations and the predictions according to theories. Not only do students appreciate those discrepancies, they learn how to make compromises to minimize the imperfections of their observations. This is a valuable skill for an engineer to have as engineers are problem solvers.
Modelling of next zen memory cell using low power consuming high speed nano d...eSAT Journals
Abstract Hybrid SET-CMOS circuits which syndicate the assets of both the SET [Single Electron Transistor] and CMOS depicts highest possibilities to be incorporated in practical implementation for future low power VLSI/ULSI configurations. The proposed work is an attempt based on SET-CMOS hybrid circuit to realize the next gen simple Memory Cell. The authors adhered to MIB model for SET and BSIM4 model for CMOS in realizing the complex cell. The maneuver of the proposed circuit is verified subsequently in standard environment. The outcomes are in good trade off with the conventional statistics of existing memory cell. Keywords: SET, SED, Hybrid CMOS-SET, MIB and Memory Cell
Design and optimization of a new compact 2.4 GHz-bandpass filter using DGS te...TELKOMNIKA JOURNAL
The objective of this work is the study, the design and the optimization of an innovative structure of a network of coupled copper metal lines deposited on the upper surface of a R04003 type substrate of height 0.813 with a ground deformed by slots (DGS). This structure is designed in an optimal configuration for use in the design of narrowband bandpass filter for wireless communication systems (WLAN), the aim of use the defected ground structure is to remove the unwanted harmonics in the rejection band, the simulation results obtained from this structure using CST software show a very high selectivity of the designed filter, a very low level of losses (less than-0.45 dB) with a size overall size of 43.5x34.3 mm.
Microstructure anlaysis and enhancement of nodular cast iron using digital im...eSAT Journals
Abstract Digital image processing is the technique to process pixel variations on digital images. This paper employs the digital image processing procedure for microstructure analysis and enhancement of nodular cast iron properties inorder to determine the quality factors. This processing made to sharpen and enhance the microstructure before quantitative analysis. This analysis taken in the analog form of nodular cast iron was performed manually such that, it is time consuming for multiple set of images. To avoid this criteria probably, Digital Image Processing techniques are being used. Often the nodular cast iron images are corrupted or defected during transmission by impulse noise which is often filtered using median filters. In this paper, some of processing steps as pre-processing, segmentation, filtering process and edge detection are done on these images for effective and lossless transmission ensuring the counting of nodules in microstructure and detailed study of grain properties that correlates with the mechanical properties such as ductility, malleability and brittleness. Only 30% restoration of image applicable to an acceptable level is limited. A new filtering method – Resolution Based Median Filter (RBMF) is proposed which achieves more than 95% restoration of nodular cast iron images to an acceptable level. This method optimizes further microstructure analysis of grain smoothening and grain boundary detection using finite element simulation model by varying the intensity level of images. Keywords – Digital Image Processing, Material Microstructure, Edge Detection, Grain Boundary, Resolution Based Median Filter (RBMF).
EFFECTIVE PEEC MODELING OF TRANSMISSION LINES STRUCTURES USING A SELECTIVE ME...EEIJ journal
The transmission lines structures are quite common in the system of electromagnetic compatibility (EMC)
analysis. The increasing complexities of physical structures make electromagnetic modeling an
increasingly tough task, and computational efficiency is desirable. In this paper, a novel selective mesh
approach is presented for partial element equivalent circuit (PEEC) modeling where intense coupling parts
are meshed while the remaining parts are eliminated. With the proposed approach, the meshed ground
plane is dependent on the length and height of the above transmission lines. Relevant compact formulae for
determining mesh boundaries are deduced, and a procedure of general mesh generation is also given. A
numerical example is presented, and a validation check is accomplished, showing that the approach leads
to a significant reduction in unknowns and thus computation time and consumed memories, while
preserving the sufficient precision. This approach is especially useful for modeling the electromagnetic
coupling of transmission lines and reference ground, and it may also be beneficial for other equivalent
circuit modeling techniques.
3-D ICs are an attractive chip architecture that can alleviate the interconnect related problems such as delay and power dissipation and can also facilitate integration of heterogeneous technologies in one chip (SoC).
A 2.4 ghz cmos lna input matching design using resistive feedback topology in...eSAT Journals
Abstract The attempt made in the paper shows an innovative designing for the enhancement and reliability in CMOS technology. A 2.4 GHz resistive feedback narrowband noise amplifier (LNA) using a series inductor input matching networks. It is easy reliable with an extra gm boosting as well as inductively degenerated topology. By using this resistive feedback topology increases the gain as well as noise figure of 2.2 dB,S21 parameter of 26dB,and IIP3 of -13dBm,while 2.8mW of power consuming from a 1.2V and its area 0.6mm2 in 0.13μm CMOS ,which gives the best figure of merit and performance. Keywords: LNA, CMOS, noise figure, resistive feedback, gm boosting, voltage gain boosting.
Wideband CMOS Power Amplifiers Design at mm-Wave: Challenges and Case Studiesaiclab
Constant striving towards higher data rates in modern communication systems and the foreseen revolution related to the forthcoming 5G mobile communications are laying the ground for an explosion of the millimetre-wave radio market. The reason? Frequency bands are wider, less overcrowded, and cheaper. Modulation schemes can be relaxed, while very directive antennas can be exploited to realize radio hops of several hundred meters.
On the other hand, the design of all the involved high frequency components is more demanding. The power amplifier, specifically, is a fundamental block of the transmitter for its impact on the overall performance of the entire system and hence poses severe challenges to the designer.
This workshop addresses the peculiar issues involved in the design of power amplifiers in this high-frequency scenario and compares them to the ones confronted with in the traditional microwave bands.
Experts coming from leading groups actively involved in mm-wave PA design will describe and comment upon solutions of choice and real-world examples, both in compound semiconductors (GaAs and GaN) and in Si-CMOS.
PERFORMANCE OF DIFFERENT CMOS LOGIC STYLES FOR LOW POWER AND HIGH SPEED VLSICS Design
Designing high-speed low-power circuits with CMOS technology has been a major research problem for many years. Several logic families have been proposed and used to improve circuit performance beyond that of conventional static CMOS family. Fast circuit families are becoming attractive in deep submicron technologies since the performance benefits obtained from process scaling are decreasing as feature size decreases. This paper presents CMOS differential circuit families such as Dual rail domino logic and pseudo Nmos logic their delay and power variations in terms of adder design and logical design. Domino CMOS has become the prevailing logic family for high performance CMOS applications and it is extensively used in most state-of-the-art processors due to its high speed capabilities. The drawback of domino CMOS is that it provides only non-inverting functions because of its monotonic nature. Dual-Rail Domino logic, (also known as clocked Cascade voltage switch logic where both polarities of the output are generated, provides a robust solution to this problem.
Hybrid and Electric Drives are far more complex than the traditional I.C. Engine based powertrains of cars and trucks. Such complexity multiplies the possible failure modes that could lead to catastrophic failure of the drivetrain, as well as make the job of optimizing the powertrain for fuel efficiency, much more challenging. Model Based Design is a solution to manage complexity, find and eliminate failure modes, and to find and exploit even obscure performance improvement opportunities. This presentation shows some nuances and advances of Model Based Design methods for Hybrid and Electric Powertrains
Presentation of a fault tolerance algorithm for design of quantum-dot cellul...IJECEIAES
A novel algorithm for working out the Kink energy of quantum-dot cellular automata (QCA) circuits and their fault tolerability is introduced. In this algorithm at first with determining the input values on a specified design, the calculation between cells makes use of Kink physical relations will be managed. Therefore, the polarization of any cell and consequently output cell will be set. Then by determining missed cell(s) on the discussed circuit, the polarization of output cell will be obtained and by comparing it with safe state or software simulation, its fault tolerability will be proved. The proposed algorithm was implemented on a novel and advance fault tolerance full adder whose performance has been demonstrated. This algorithm could be implemented on any QCA circuit. Noticeably higher speed of the algorithm than simulation and traditional manual methods, expandability of this algorithm for variable circuits, beyond of four-dot square of QCA circuits, and the investigation of several damaged cells instead just one and special cell are the advantages of algorithmic action.