This document provides an overview of MOSFET modeling concepts including: 1. Symmetry properties and normalization of the drain current equation. 2. Definitions of the forward and reverse currents, and the specific (normalization) current. 3. Description of the pinch-off voltage, slope factor, and their determination as functions of gate voltage.

1. EE 290C
CMOS Analog Design Using
All-region MOSFET Modeling
Lecture 4: Design-oriented dc MOSFET model

2. Symmetry and Normalization - 1
I D = I D (VG , VS , VD )
1. VG
VS VD
Ungrounded local substrate:
VG→ VGB VS→ VSB VD→ VDB B ID
2. Symmetry B
V1 ID V2
I D (VG , V1 , V2 ) = − I D (VG , V2 , V1 )
VG
CMOS Analog Design Using All Region MOSFET Modeling
2

3. Symmetry and Normalization - 2
3. For a long-channel MOSFET
W
I D = I F − I R = I S i f − ir  = I SQ  f (VG , VS ) − f (VG , VD ) 
L 
 
I F ( R ) = I S  q ′ ( D ) 2 + 2 q′ ( D )  D
 IS 
IS
ID
q′ ( D ) = QIS ( D ) / ( −nCoxφt )
′ ′
IS
i f (r ) = I F ( R) / I S
G IF − IR
φt2 WW
′
I S = µ Cox n = I SQ B
2L L
IS and ISQ are the normalization (specific)
current and the “sheet” normalization
S
current, slightly dependent on bias.
3
CMOS Analog Design Using All Region MOSFET Modeling

4. Forward and Reverse Currents
Long-channel MOSFET I D = I F − I R = I (VG ,VS ) − I (VG ,VD )
IF: forward current
IR=
IR: reverse current
IF=
CMOS Analog Design Using All Region MOSFET Modeling 4

5. Specific Current
φt2 W W
The specific (normalization) current ′
I S = µCox n = I SQ
2L L
ISQ : design parameter
slightly dependent on VG
ISQ ≈25 nA (p-channel)
ISQ ≈75 nA (n-channel)
in 0.35 µm CMOS
CMOS Analog Design Using All Region MOSFET Modeling 5

6. Pinch-off Voltage and Slope Factor - 1
UCCM VP − VS ( D ) = φt  qIS ( D ) − 1 + ln q′ ( D )  & q′ ( D ) = 1 + i f ( r ) − 1
′  IS
IS
2
 γ γ
2

VP =  VG − VT 0 +  2φF +  −  − 2φF
 2  2

  Linearization:
VG − VG 0
VP = VP 0 +
VP n (VG 0 )
Slope =1/n
Slope =1
γ
n (VG 0 ) = 1 +
2 VP 0 + 2φF
In particular:
VP0
VG − VT 0
VP =
n (VT 0 )
γ
n (VT 0 ) = 1 +
VT0 VG0 VG 2 2φF
CMOS Analog Design Using All Region MOSFET Modeling 6

7. Pinch-off Voltage and Slope Factor - 2
Determination of the pinch-off voltage and the slope factor as
functions of VG. NMOS transistor W=20 µm, L=2 µm, 0.18 µm
CMOS technology.
7
CMOS Analog Design Using All Region MOSFET Modeling

8. The I-V Relationship
( )
VP − VS = φt  1 + i f − 2 + ln 1 + i f (r ) −1 
 
1,00E-03
10-3 VD = VG
ID (A)
VD
1,00E-04
ID
VS = 0 V
1,00E-05
0.5
1.0
10-6
1,00E-06
1.5
VS
VG
2.0
1,00E-07
2.5
3.0
1,00E-08
10-90,00E+00
1,00E-09
5,00E-01 1,00E+00 1,50E+00 2,00E+00 2,50E+00 3,00E+00 3,50E+00 4,00E+00
4 4,50E+00(V)
0 1 2 3 VG
Common-source characteristics
CMOS Analog Design Using All Region MOSFET Modeling 8

9. The I-V relationship
( )
VP − VS = φt  1 + i f − 2 + ln 1 + i f (r ) − 1 
 
10-3
ID (A) VD = VG
VG = 4.8 V
VD
ID
10-6
VG
0.8 V VS
10-9
0 1 2 3 VS (V)
Common-gate characteristics VG=0.8, 1.2, 1.6,
2.0, 2.4, 3.0, 3.6, 4.2, and 4.8 V
CMOS Analog Design Using All Region MOSFET Modeling 9

10. Weak inversion model
Weak inversion VG − VT 0
( )
− VS ( D ) = φt  1 + i f ( r ) − 2 + ln 1 + i f (r) −1 
if(r)<1  
n
-1
if(r)/2
 VG −VT 0 
−VS  / φt W

nCox φ t2e1 = 2 I S e1
1 − e 
−VDS / φt ′
I0 = µ n
e n 
I D = I0   L
CMOS Analog Design Using All Region MOSFET Modeling 10

11. Strong inversion model - 1
VG − VT 0
( )
− VS ( D ) = φt  1 + i f ( r ) − 2 + ln 1 + i f ( r ) − 1 
 
n
Strong inversion
VG − VT 0
if(r)>>1 − VS ( D ) ≅ φt i f ( r ) = φt I F ( R ) I S
n
W 2
2
(V − V − nVS ) − (VG − VT 0 − nVD ) 
′
I D = I F − I R ≅ µ nCox
 G T0
2nL
Moderate inversion
1<if(r) <100 Both sqrt(.) and ln(.) terms are important
CMOS Analog Design Using All Region MOSFET Modeling 11

12. Strong inversion model - 2
ID
VDS
VG
ID/IF
1
VDSsat=VP=(VG-VT0)/n VDS
Output characteristics at VS=0
CMOS Analog Design Using All Region MOSFET Modeling 12

13. Strong inversion model - 3
′
µ Cox W ′
µ Cox W
(VG − VT 0 )
ID = (VG − VT 0 − nVS )
ID ID =
ID
2n L 2n L
SCE, µ, n,
“model”
VT0 VG (VG − VT 0 ) n
VDD VS
ID VDD
ID
VG
VG
VS
CMOS Analog Design Using All Region MOSFET Modeling 13

14. Universal output characteristics
 1+ if −1 
 q′ 
VDS
 = 1 + i f − 1 + ir + ln  
′ ′
= qIS − qID + ln  IS
 1 + ir − 1 
′
φt  qID   
(a) if= 4.5x 10-2 (VG=0.7 V).
(b) if= 65(VG= 1.2 V).
(c) if= 9.5x102 (VG= 2.0 V).
(d) if= 3.1x 103 (VG= 2.8 V).
(e) if= 6.8x 103 (VG= 3.6 V).
(f) if= 1.2x 104 (VG= 4.4 V).
(o): measured
(—): model
CMOS Analog Design Using All Region MOSFET Modeling 14

15. Saturation voltage
Saturation voltage (VDSsat) – VDS such that q′ / qIS = ξ
′
ID
( )
VDSsat = φt ln (1 ξ ) + (1 − ξ ) 1+ i f −1  (1−ξ) is the saturation level
 
CMOS Analog Design Using All Region MOSFET Modeling 15

16. Transconductances - 1
Transconductances ∆I D = g mg ∆VG − g ms ∆V S + g md ∆V D + g mb ∆V B
∂I D ∂I ∂I ∂I
g mg − g ms + g md + g mb = 0 , g ms = − D , g md = D , g mb = D
g mg =
∂VG ∂VS ∂VD ∂VB
∂ ( IF − IR ) ∂I W
Calculation of gms ′
= − F = − µ QIS
g ms = −
∂ VS ∂ VS L
W
′
= − µ QID
g md
L
Pao-Sah ID (UCCM)
∂ (i f − ir )
g mg = I S
∂VG ∂i f ∂i f g ms − g md
=− g mg =
∂VG n∂VS n
UCCM
g
∂ir ∂i in saturation
g mg = ms
=− r
n
∂VG n∂VD
16
CMOS Analog Design Using All Region MOSFET Modeling

17. Transconductances - 2
VDD
ID
VG
VS
Source transconductance VG= 0.8, 1.2, 1.6, 2.0, 2.4, 3.0, 3.6, 4.2, and
4.8 V (W=L=25 µm, tox=280 Å)
CMOS Analog Design Using All Region MOSFET Modeling 17

18. Transconductances - 3
VDD
ID
VS
VG
Gate transconductance VS= 0, 0.5, 1.0,1.5, 2.0, 2.5, and 3.0 V
W=L=25 µm, tox=280 Å
18
CMOS Analog Design Using All Region MOSFET Modeling

19. The transconductance-to-current ratio - 1
WI (if <1)
≅1
g ms ( d )φ t 2
Transconductance = 2
-to-current ratio I F (R) 1 + i f (r ) + 1 ≅ SI (if >>1)
i f (r )
100
102
gms/IF
W=25 µm
tox = 28 nm (IS = 26 nA)
Seqüência1
101 L=25 µm, tox= 280 Å
10
tox = 5.5 nm (IS = 111 nA)
Seqüência2
L=20 µm, tox= 55 Å
model
Seqüência3
1001
1,00E-04 1,00E-03 1,00E-02 1,00E-01 1,00E+00 1,00E+01 1,00E+02 1,00E+03 1,00E+04
10-4 10-2 100 102 104
if
CMOS Analog Design Using All Region MOSFET Modeling
19

20. The transconductance-to-current ratio - 2
g ms ( d )φ t 2 WI (if <1)
Transconductance ≅1
=
-to-current ratio I F (R) 1 + i f (r ) + 1 2
≅ SI (if >>1)
i f (r )
10 2
1,00E+02
gms/IF
V = 1.0 V (IS = 33 nA)
GB
Seqüência1
10 1
1,00E+01
VGB = 2.0 V (IS = 26 nA)
Seqüência2
W=L=25 µm, tox= 280 Å
VGB = 3.0 V (IS = 24 nA)
Seqüência3
model
Seqüência4
10 10 0
1,00E+00
10 10 10 10
-4 -2 0 2 4
if
1,00E-04 1,00E-03 1,00E-02 1,00E-01 1,00E+00 1,00E+01 1,00E+02 1,00E+03 1,00E+04
CMOS Analog Design Using All Region MOSFET Modeling 20

21. The transconductance-to-current ratio - 3
g ms ( d )φ t 2 WI (if <1)
Transconductance ≅1
=
-to-current ratio I F (R) 1 + i f (r ) + 1 2
≅ SI (if >>1)
i f (r )
102
100
gms/IF
W=25 µm, tox= 280 Å
L = 25 µm (IS = 26 nA)
Seqüência1
1010
1
L = 2.5 µm (IS = 260 nA)
Seqüência2
model
Seqüência3
100 1
1,00E-04 1,00E-03 1,00E-02 1,00E-01 1,00E+00 1,00E+01 1,00E+02 1,00E+03 1,00E+04 1,00E+05
10-4 10-2 100 102 104
if
CMOS Analog Design Using All Region MOSFET Modeling 21

22. The low-frequency small-signal model
G
g md v d
id
g mb vb
S D
g ms v s
g mg v g
B
CMOS Analog Design Using All Region MOSFET Modeling 22