Reliability Testing Methods

1. 2016 Prognostics and System Health Management Conference (PHM-Chengdu)
A Comprehensive Reliability Analysis Method for
Electronic Products Based on Simulation and
Hardware Test
Libing Zhao, Wei Zhang, Haijing Zhou, Ling Shen, and Jian Li
China Academy of Aerospace Standardization and Product Assurance
Beijing, China
Email: ghostgun896@163.com
Abstract—This paper aims to propose a comprehensive reliability
analysis method for electronic products by the combination of
EDA (Electronic Design Automatic) software simulation and
hardware test. Through hardware tests to the key waveforms of
an electronic product’s PCB (Printed Circuit Board), the physics
model of the concerned module can be modeled with the
application of Saber. Then the reliability of circuit schematic
level can be analyzed by the worst case circuit analysis technique.
On the contrary, the hardware test can verify the correctness of
the simulation. Furthermore, the signal integrity and
electromagnetic interference of an electronic product’s total
circuit board can be analyzed with ANSYS software, the
reliability of the total circuit board level can be analyzed.
Keywords-reliability analysis; electronic products; circuit
simulation; hardware test
I. INTRODUCTION
Modern electronic products own the characters of high
reliability and long life circle, however, the phenomenon that
failure of electronic product leads to system’s fault or safety
incidents occurs frequently [1]. Therefore, reliability analysis
for electronic products during design stage and validation stage
has become more urgent and necessary.
The electronic products’ reliability engineering technique
has been built based on the statistic theory of failure data,
namely ‘Reliable Mathematics’, which emphasizes on the
prediction of product’s reliability through the statistics on the
tendency of failure data. However, the method referred cannot
deal with products with small samples or locate the original
reason for products’ failure, let alone support on products’
design improvements [2]. Chen did some researches on
reliability simulation prediction of electronic product based on
physics of failure method [3]. Yang applied Bayesian Networks
in the reliability analysis of electronic products [4]. Sun
analyzed the reliability of electronic products based on “failure
mode-failure mechanism-analysis model” [5]. Liu proposed a
reliability design and analysis method for electronic products
based on a digital prototype [6]. With the application of EDA
software simulation and hardware test, it will be more
convenient to analyze the weakness and the reliability of the
electronic product.
As for the reliability of an electronic product, it is crucial to
analyze the reliability of circuit schematic level and total circuit
board level whereas the designers always concern about the
expected stable output indexes and neglect the product’s
dynamic characters. On the circuit schematic level, the stress
value of a device is the key parameter to evaluate the reliability.
However, there exist difficulties in the technique, such as
getting the exact stress value of a device during dynamic
process, or the exact simulation model of a device. On the other
hand, the signal integrity and electromagnetic interference
should be analyzed to improve the board level reliability, while
the correctness of signal integrity and electromagnetic
interference simulation should be concerned [7].
In this paper, the techniques that simulation and hardware
test are combined together to analyze the comprehensive
reliability of electronic products. For the circuit schematic level
reliability, the physical model of a circuit board can be
modeled in Saber, and the devices that can not obtained in
library file should be modeled combined the hardware tests.
Firstly, the transient analysis can obtain the practical
waveforms of the circuit; in the meantime, verify the
correctness of the model which is built. Secondly, through the
worst case circuit analysis technique, the stress value of the
circuit can be achieved. Hence, the circuit schematic level
reliability can be guaranteed. For the board level reliability,
with the application of ANSYS SIwave and Designer, the
signal integrity and electromagnetic interference of the total
circuit board can be analyzed, and the hardware test guarantees
the correctness of the results.
II. ANALYSIS OF ELECTRONIC PRODUCT’S CIRCUIT
SCHEMATIC LEVEL RELIABILITY
A. Technical Framework of Electronic Product’s Circuit
Schematic Level Reliability
The traditional reliability and simulation analysis method
cannot identify the weakness of the electronic products for the
simulation model must be more precise and closer to real
operation condition and environment. According to this
difficulty, the analysis method which combines simulation and
hardware test is proposed.
978-1-5090-2778-1/16/$31.00 ©2016 IEEE
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2. 2016 Prognostics and System Health Management Conference (PHM-Chengdu)
Figure 3. Performance simulation and hardware test verification process
The key problem is to seek methods to combine the
hardware test data and simulation data. There are two methods:
one is apply data identification technique to the test data, then
simulation data model is generated; the other is that simulation
data and hardware test data is used for data fitting. The
technical framework of the method is illustrated in the Fig. 1
below.
Figure 1. The framework of circuit schematic level reliability analysis for
electronic products
The process of the method contains: simulation-dominated
analysis, physical modeling, model verification, key signal
hardware test, fault identification, simulation optimization,
simulation verification. Among which simulation is based on
worst case circuit analysis technique.
B. Modeling and Verification of Electronic Product’s
Physical Model
The selection and analysis for critical circuit module of
electronic product are the primary tasks to identify the
weakness and analyze the reliability. For those components
which are commonly used can be obtained directly from the
Saber’s library. However, some components which are lack of
relevant data can hardly get their practical models. Concerning
this situation, hardware test can be combined to acquire the
nominal characters of the circuit.
For the established physical model, comparisons of
practical hardware test on the key signal waveforms and
simulation waveforms (mainly DC operation point and
transient analysis waveforms) confirm the accuracy of the
model. The modeling process is shown in Fig. 2.
Electronic Products
Physical Modeling
Simulation Model
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时时(s)
电电(V)
主主PWM
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时时(s)
电电(V)
P5的的的电电
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时时(s)
电电(V)
P5的的电的电电
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40
时时(s)
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CN10的4脚电电
Hardware Test of the Key Signal
Measurement Data
Simulate the Key Signal
Simulation Waveforms
Comparisons of
Practical and Simulation
Waveforms
Similar
Dissimilar
Performance Simulation Analysis
Figure 2. Modeling process of electronic products
C. Performance Simulation Analysis for Electronic Products
Combinations of extreme cases such as environmental
variations of operation condition, drifting of device parameter
and input bias can be modeled in Saber, then running circuit
performance simulation can identify the overstressed
components, and the components that impact much on the
products and weakness of the product as well.
The advantages of the performance simulations include:
1) Sensitivity simulation analysis reflects the device
parameter drifts’ impact on the circuit performance. The
combinations of parameter’s variations under worst case
situation are based on the sensitivity analysis.
2) Worst case parts stress simulation analysis can compute
the extreme stress value under worst case situation and offer
judgments on whether the parts operate over their rated value.
3) Monte Carlo simulation analysis is a statistic method that
each component parameter subjects to a certain distribution,
and then simulating the circuit enough times to compute the
envelops of product’s performance.
After simulation and analysis above, hardware test should
verify the identified weakness of the electronic product. The
performance simulation and verification process is shown in
Fig. 3.
Through the above simulation and hardware test, the
weakness of electronic product can be identified, and then the
reliability of the electronic product can be guaranteed.
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3. 2016 Prognostics and System Health Management Conference (PHM-Chengdu)
D. An Illustrative Example
A quasi-resonant current controller is modeled on Saber
based on chip NCP1380, which is applied to a flyback switch
power supply circuit in Fig. 4 [8].
1) Physical modeling and model verification
Figure 4. Flyback switch power supply circuit
Figure 5. The control logic graph of chip NCP1380
The control logic graph of chip NCP1380 is shown in Fig. 5.
With regard to the established model of chip NCP1380, it is
necessary to verify the accuracy of the model by comparing the
simulation and hardware test waveforms of the key pins. The
crucial characters of the switch power supply circuit include:
direct current stable output voltage, voltage of FB pin, MOS,
DRV pin, ZCD pin, CT pin. Fig. 6.a shows the measurement
voltages of output, FB, drain of MOS. Fig. 6.b lists the
transient waveforms of simulation. Fig. 7.a shows the
measurement voltages of DRV, ZCD, CT. Fig. 7.b lists the
transient waveforms of simulation.
(a) (b)
Figure 6. (a) The measurement voltages of output, FB, drain of MOS; (b)
lists the transient waveforms of simulation
(a) (b)
Figure 7. (a) The measurement voltages of DRV, ZCD, CT; (b) lists the
transient waveforms of simulation
Through the comparisons of hardware test waveforms and
simulation waveforms, the error of key character parameter is
less than 10%. The results are shown in Table I. The error
generates from the regardless of parasitical parameter of the
components.
TABLE I. COMPARISONS OF KEY WAVEFORMS
Key
Waveforms
Hardware Test Simulation Analysis
Relative
Error
Output: 40V 39.6V 40.435V 2.1%
FB pin 1.48V 1.52V 2.7%
Drain of MOS 478V, 66.67KHz 441.35V, 65.989KHz 7.7%
DRV pin 13V, 64.52KHz 12.99V,65.9KHz 0.007%
ZCD pin
0.65V, second
valleya 0.71V, second valley 9.23%
CT pin 1.4V, 64.52KHz 1.417V, 65.9KHz 1.2%
a. Valley determines the mode of chip NCP1380.
2) Simulation analysis
After transient analysis, the sensitivity analysis is
implemented to locate the devices that system output 40V is
sensitive to.
Through the above sensitivity analysis results, it can be
seen that the resistors R1, R26, R27, R28 and the capacitor C12
impact more on the 40V output than other devices.
In order to detect whether if there are overstressed devices
that might exceed their maximum ratings, the stress simulation
analysis is proposed. The stress simulation results are shown in
Fig. 9; it can be seen that there are not devices which are
operating exceed their maximum ratings.
For the purpose of computing the envelops of system
outputs while there exists device’s parameter perturbance, the
parameter perturbances of resistor R1, R26, R27, R28 and
capacitor C12 are considered.
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4. 2016 Prognostics and System Health Management Conference (PHM-Chengdu)
Figure 8. Sensitivity analysis results
Figure 9. Stress analysis results
Figure 10. 50 times Monte Carlo simulation results
Through 50 times Monte Carlo simulations, the range of
40V output variation is 39.42V~41.372V, which is satisfied
with the requirement of system. Furthermore, the hardware test
waveforms in Fig. 6.a guarantee the correctness of the
simulation results.
III. ANALYSIS OF ELECTRONIC PRODUCT’S TOTAL CIRCUIT
BOARD LEVEL RELIABILITY
As for the total circuit board level reliability, it is crucial to
analysis the board’s signal integrity and electromagnetic
interference. An important challenge in the work of signal
integrity engineers and electromagnetic interference engineers
is to ensure system functions work well and radiation
interference criteria are met for system design specifications.
These challenges can be reduced significantly by co-designing
the system and accounting for thermal, SI, PI and the 3-D
enclosure design simultaneously. We propose a integrated
workflow for engineers to solve the total circuit board’s signal
integrity and electromagnetic interference, thus the total circuit
board level reliability can be guaranteed [9,10].
A. Integrated Workflow for Total Circuit Board Level
Reliability
Figure 11. Board level reliability analysis flow
There are there major steps in this integrated simulation
flow (seen in Fig. 11).
Step 1: Import and extract the physical PCB layout electric
properties from their layout file and then export the PCB’s S-
parameter model by using ANSYS SIwave.
ANSYS SIwave is a 2.5D EM simulation tool that uses the
finite element method (FEM) and the method of moments
(MOM). It is a hybrid solver which uses a 2-D triangular mesh
and can handle very complex PCB layouts. It solves complete
layouts including the traces, planes, through hole vias, metal
thickness, and dielectric thickness effects.
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5. 2016 Prognostics and System Health Management Conference (PHM-Chengdu)
Step 2: Import the extracted S-parameter model into the
ANSYS Designer.
ANSYS Designer which has a circuit simulation capability
for both SerDes and parallel busses. The Designer includes
numerous model types such as extracted PCB S-parameter
models, driver/receiver IBIS models, RLC passive component
equivalent models and arbitrary input signals to perform a very
accurate and detail circuit simulation. Next the dynamic link
combines the circuit waveform characteristics into the SIwave
EM field solver.
Step 3: Compute the potential crosstalk. The signal
waveforms simulated in Designer are treated as excitation
sources within SIwave and this produces near-field and far-
field results with the defined input signal waveforms.
B. An Illustrative Example
In order to simplify the verification condition, a physical
structure has been created which owns a 3-layer PCB layout in
SIwave. In this layout, the top and bottom layers are power
layer and ground layer, and the middle layer is a signal layer.
The goal is to analyze the selected nets’ signal integrity and
compute the near field and far field from PCB.
Signal In
Via
ANSYS SIwave
Figure 12. The PCB layout
Following the simulation procedure provided in the
previous section, we first get the PCB’s S-parameter from
results using SIwave in Fig. 13. Secondly, run a transient (time
domain) simulation of the overall circuit, which includes the
driver, receiver, source, load and the SIwave S-parameter
model. And afterwards, apply push excitations to convert the
time domain waveforms into the frequency domain sources in
SIwave. Finally, Use the new frequency domain sources in
SIwave so that one can compute the far field response.
This figure reflects the S parameters of this net on the PCB
wiring board along with the change of frequency. For example,
the bold curve in the Fig. 13 is the S parameter for the pair
(U2_pair1_neg, VCC_main), and it can be seen that the worst
frequency of signal attenuation is 1.732e+03MHz.
The waveforms in Fig. 15 is input eye plot of voltage (pin
U1_pair1_pos - pin U1_pair1_neg). Through the plots one can
easily get the time domain waveforms. After transient analysis
in Designer, frequency dependent sources are needed for far
field simulations; therefore, it is necessary to convert all the
voltages information at all ports locations obtained from the
previous transient simulation into frequency domain sources
using an FFT. Namely, the signal waveforms are treated as
excitation sources within SIwave. The far-field simulation
results with the defined input signal waveforms are shown in
Fig. 16.
Figure 13. The S parameter plot
Figure 14. The circuit model in ANSYS Designer
Figure 15. Time domain input signal in ANSYS Designer
Figure 16. Far field results from PCB
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6. 2016 Prognostics and System Health Management Conference (PHM-Chengdu)
Figure 17. Near field results from PCB
The near field results are shown in Fig. 17, the electric and
magnetic field intensity varies with frequency. If the intensity
of electric and magnetic field intensity exceeds the expected
intensity, one should seek ways to lower the intensity.
Therefore, the total board level reliability of an electronic
product is guaranteed.
IV. CONCLUSION
In order to analyze the electronic products’ reliability, a
comprehensive reliability analysis method by the combination
of EDA software simulation and hardware test is proposed.
The reliability of circuit schematic level can be analyzed by the
worst case circuit analysis technique with the help of hardware
test. Furthermore, the reliability of the total circuit board level
can be guaranteed with the analysis of the signal integrity and
electromagnetic interference of total circuit board. The
shortcoming of the paper is that the board level reliability does
not combine the hardware test technique.
ACKNOWLEDGMENT
The authors thank the supports provided by China
Academy of Aerospace Standardization and Product
Assurance.
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