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1. PRESENTING BY:-
MD AFROJ ALAM ANSARI
1AM20EC045
GUIDE :- Dr. JENITTA J
AMC ENGINEERING COLLEGE,BENGALURU-83
DEPARTMENT OF ELECTRONICS AND COMM.
ENGINEERING

2. CONTENTS
 INTRODUCTION
 CHALLENGES IN MANUAL CIRCUIT DESIGN
 OBJECTIVE OF THE FRAMEWORK
 COMPONENTS OF THE FRAMEWORK
 PROPOSED CIRCUIT DESIGN FRAMEWORK
 BENEFITS
 CHALLENGES AND FUTURE DIRECTIONS
 EXPERIMENTAL RESULT
 CONCLUSION
 REFERENCES

3. INTRODUCTION
 The article discusses challenges in integrated circuit (IC) design
automation, proposing a unified framework to address topology selection
and transistor sizing.
 It outlines existing methods including library-based, building-block-based,
and transistor-based approaches.
 The proposed framework offers a two-stage design process, a novel
voltage-based graph representation, and a multiagent reinforcement
learning optimizer for faster convergence.
 Experimental validation on level shifter circuits in a 180-nm CMOS
process demonstrates its effectiveness in accelerating design while
ensuring practicality and robustness.

4. CHALLENGES IN MANUAL
CIRCUIT DESIGN
 COMPLEXITY MANAGEMENT- Modern circuits are
becoming increasingly complex, making manual design
error-prone and time-consuming.
 RESOURCE INTENSIVENESS- Manual circuit design requires
significant human resources, including skilled engineers
and designers.
 TIME CONSTRAINTS- Manual design processes are
inherently time-consuming, often requiring iterative trial-
and-error approaches.
 LIMITED SCALIBILITY- Manual design methods struggle to
scale efficiently to handle larger and more complex
designs.

5. OBJECTIVE OF THE
FRAMEWORK
 Efficiency Enhancement- To streamline the design
process of level shifter circuits, minimizing time and effort
required for design iterations.
 Performance Optimization- To optimize the performance
metrics of level shifter circuits, including speed, power
consumption, and area.
 Flexibility and Customization- To provide flexibility in
designing level shifter circuits tailored to specific
requirements and constraints.
 Robustness and Reliability- To ensure the robustness
and reliability of designed level shifter circuits across
different operating conditions.

6. COMPONENTS OF THE
FRAMEWORK
 Design Space Exploration
 Modeling and Simulation.
 Optimization Algorithms
 Constraint Handling
 Performance Evaluation
 Design Validation and Verification
 Automated Layout Generation
 Technology-Aware Design

7. PROPOSED CIRCUIT DESIGN
FRAMEWORK
Fig. 2. Examples of proposed graph-based
circuit representation. (a) Simple circuit with a
pair of MOSFET devices. (b) Complex circuit
where gates are connected to other nodes.
Fig. 1. Overview of the proposed circuit
design framework.

8. BENEFITS
1. Time-Saving: ACDFs can significantly reduce the time
required to design LSCs. By automating the design
process, designers can quickly generate multiple circuit
designs .
2. Improved Quality: ACDFs can generate a large number
of potential circuit designs, allowing designers to explore
a wide range of options..
3. Cost-Effective: By automating the design process,
ACDFs can help reduce costs associated with manual
design effortS.
4. Efficient Resource Utilization: ACDFs can efficiently
utilize available design resources, such as processing
power and memory.

9. CHALLENGES AND FUTURE
DIRECTIONS
 Challenges in Current Framework:
• Limited Scalability: Current frameworks may struggle to efficiently handle large
and complex designs.
• Design Space Exploration: Challenges in fully exploring the design space to find
optimal solutions.
• Resource Intensiveness: Frameworks may require significant computational
resources and time for optimization.
 Future Directions:
• Scalability Enhancement:
• Develop techniques to improve the scalability of the framework for handling larger and
more complex designs.
• Advanced Optimization Algorithms:
• Explore advanced optimization algorithms, including machine learning and artificial
intelligence techniques, to further enhance design efficiency.
• Exploration of Design Space:
• Develop methods for more comprehensive exploration of the design space, considering a
broader range of design alternatives and trade-offs.
• Resource Efficiency:
• Optimize algorithms and methodologies to reduce the computational resources and time
required for design optimization.

10. EXPERIMENTAL RESULT
Fig. 3.Level shifter circuit topologies generated by topology generator (a) C1. (b) C2. (c) C3. (d) C4. (e) C5
Fig. 4. Experimental results of topology generation. (a) Fitness. (b) Number of species.

11. Fig. 5. Trends of reward improvement with and without proposed algorithmic
optimization techniques. Proposed techniques enable a faster and more
stable optimization process. (a) D4PG. (b) DDPG. (c) D4PG with multiupdate.
(d) DDPG with multiupdate. (e) D4PG with multiupdate and episode
early stopping. (f) DDPG with multiupdate and episode early stopping.

12. Fig. 6. Reward trends of
alternative approaches for
comparisons. (a) Scalar
value critic. (b) Action
scaling.
Fig. 7. Trends of output
swing ratio when the
circuit is optimized (a) at
TT corner only and (b) at
all process corners.
Considering process
corners significantly
improves reliability.
( a ) ( b ) ( c )
(d) (e)
Fig. 8. Layout of
generated circuits and
their size. (a) C1 (4.7
μm × 8.6 μm).
(b) C2 (3.5 μm × 11.2
μm). (c) C3 (4.5 μm ×
10.3 μm). (d) C4
(4.0 μm × 8.4 μm). (e)
C5 (4.0 μm × 8.2 μm).

13. Fig. 9.(a) Delay
measurement circuit,
(b) test chip layout,
and (c) test chip
micrography.
Fig. 10. Baseline level shifter
designs from prior work. (a) B1
(b) B2 (c) B3 (d) B4 (e) B5

14. CONCLUSION
 A novel automatic circuit design framework for
level shifter circuits integrates a topology
generator and a circuit optimizer, bypassing
the need for preconstructed building blocks.
 By leveraging evolutionary algorithms for
topology generation and reinforcement
learning for transistor sizing, it achieves
superior performance with test chips
demonstrating 2.8×–5.3× lower power-delay
products compared to manually designed
circuits, validated in a 180-nm CMOS process.

15. REFRENCES
• L. Lavagno, L. Scheffer, and G. Martin, EDA for IC Implementation,
Circuit Design, and Process Technology. Boca Raton, FL,
USA: CRC Press, 2016.
• O. Aaserud and I. R. Nielsen, “Trends in current analog design—A panel
debate,” Analog Integr. Circuits Signal Process., vol. 7, no. 1, pp. 5–9,1995.
• M. C. Golumbic, A. Mintz, and U. Rotics, “An improvement on the complexity
of factoring read-once Boolean functions,” Discr. Appl. Math.,
vol. 156, no. 10, pp. 1633–1636, May 2008.
• V. N. Possani, V. Callegaro, A. I. Reis, R. P. Ribas, F. De Souza Marques,
and L. S. Da Rosa, “Graph-based transistor network generation method
for supergate design,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst.,
vol. 24, no. 2, pp. 692–705, Feb. 2016.
• H. Y. Koh, C. H. Séquin, and P. R. Gray, “OPASYN: A computer
for CMOS operational amplifiers,” IEEE Trans. Comput.-Aided Design
Integr. Circuits Syst., vol. 9, no. 2, pp. 113–125, Feb. 1990.

16. THANK YOU