Wideband CMOS Power Amplifiers Design at mm-Wave: Challenges and Case Studies

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Wideband CMOS PA Design at mm-Wave:
Challenges and Case Studies
WW04
Matteo Bassi
University of Pavia, Italy
matteo.bassi@unipv.it
WW04 Power Amplifier Design Challenges and Solutions for mm-wave Radios

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Outline
• CMOS Power Amplifier Design Challenges
• Coupled Resonators to Improve GBW
• Case Studies
– [CS1] A 40-67 GHz PA with 13 dBm PSAT and 16% PAE in
28nm CMOS LP
– [CS2] A 15 GHz-Bandwidth 20 dBm PSAT Power Amplifier
with 22% PAE in 65 nm CMOS
• Wrap up and conclusions

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CMOS Power Amplifier Trends
• Generation of power at mm-wave in CMOS technology is challenging
• If large bandwidth is required, output power further limited
[http://isscc.org/doc/2016/ISSCC2016_TechTrends.pdf*]
*CMOS only

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Power Amplifier Design Trade-Off
• Demand for broadband PAs:
• Radar Imaging, Gb/s Wireless, Chip-to-Chip Links
• For a given power, bandwidth trades with gain and efficiency
Bandwidth
EfficiencyGain

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GBW-Efficiency Trade-Off
• High efficiency requires high gain
• As a matter of fact, having both high gain/stage (hence
good efficiency) and large BW is difficult
1
1Out In Out
DC DC
P P P
PAE
P P G
−  
= = − 
 

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Typical Power Amplifier
• Active Stages
• High output power: large Ci2 andCo2
• Class AB biasing: high efficiency but low gm
• At the interstage GBW is limited to ≈ gm,MIn/Ci2

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GBW vs Efficiency at Interstage 1/2
• Assumptions:
– Fixed output power Pout and gain G=Vout/Vin
– Fixed Vdd and size of MPA for desired Pout
– Inductor L1 resonates Ci,PA at center frequency
– For every MDR size, RD selected to achieve desired gain G

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GBW vs Efficiency at Interstage 2/2
• If 55% fractional BW is targeted, an interstage network with GBWEN=3
allows 5x smaller transistor, and PAE goes from 11% to 26%
•  Interstage network with high GBW key in ehnancing efficiency at a fixed
fractional BW

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Coupled Resonators (CR)
• Simple topology and low losses
• Two peaking frequencies:
• L2 used to control the bandwidth
• ZIn ≈ RL within band
1 3
21 1 3 3
1 1
, 1L H L
L L
LL C L C
ω ω ω
+
≈= ≈ +

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GBW Improvement
2 , 2CR LC CR LCZt Zt BW BW≈ ≈
Coupled resonators allow x2 GBW enhancement (GBWEN)
20 40 60 80 100
10
20
30
40
50
Frequency [GHz]|Zt|[dB]
CR
LC

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In-Band Ripple Minimization
• Limited inductor Q leads to asymmetric response
• Coupled resonator can be conveniently tuned to minimize in-band
ripple
30 40 50 60 70 80
20
25
30
35
Frequency [GHz]
|Vout/Iin|[dB]
Q=100 Q=30 Q=10
30 40 50 60 70 80
22
24
26
28
30
32
Frequency [GHz]|Vout/Iin|[dB]
Q=10
1
3
( )
( )
T H
T L
Z L
Z L
ω
ω
≈
Decreasing Q Increasing L1/L3

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PA Targets and Complete Schematic
• Design targets:
• PSAT ≈ 13dBm, Fractional Bandwidth (f.c.) > 40% @60GHz
• Gain > 10dB, PAE > 10%
• Careful design of interstage and output matching network are
key in achieve desired targets

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Output Matching Network
Split L2
Norton transformation
for impedance scaling
Transformer
Coupled Resonators
for 2x GBWEN

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Output Matching Network
• Transformer for differential to single-ended conversion
• L2s implemented by the parasitic inductor of the trace
connecting pads to the transformer
• Efficiency greater than 70%
Lp=Ls=70pH, k=0.7 - L2s=40pH

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Traditional Interstage Matching Network
• L resonates Ci and Co at center frequency
• Given a target gain Gd and bandwidth BWd
• Explicit resistor Re increases bandwidth but decreases gain
• Larger MIn required to restore gain level at the cost of
increased power consumption

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Interstage Matching Network
• Given Gd and BWd, GBW improvement of inductively coupled
resonators exploited to scale down transistor size by n
• Norton transformations further reduce the size and power
consumption by t
• nt close to 3 in this design

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Input Matching Network
• Neutralization increases stability but also QIN
• Inductive degeneration decreases QIN to achieve wideband input
matching and enhances linearity
• Mutual coupling facilitates layout routing and reduces inductors
length

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Chip Microphotograph
ST 28nm CMOS LP, chip area: 0.34 mm2
620 μm
540μm
Interstage Matching
Output Matching

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Measured S-Parameters
30 35 40 45 50 55 60 65 70
-60
-50
-40
-30
-20
-10
0
10
20
Frequency [GHz]
S-Parameters[dB]
S21
S11
S22
S12
Gain ≈ 13 dB, BW ≈ 27 GHz, Frac. BW ≈ 51%

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Large Signal Performance at 50GHz
-10 -5 0 5
0
5
10
15
20
Input Power [dBm]
Pout[dBm]/Gain[dB]/PAE[%] Pout Gain PAE
PSAT ≈ 13.3dBm, P1dB ≈ 12dBm, PAE = 16% @ 50GHz

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Large Signal Performance vs Frequency
Uniform PSAT and P1dB from 42-50GHz
40 42 44 46 48 50
0
5
10
15
20
Frequency [GHz]
P
1dB
[dBm]/P
SAT
[dBm]/PAEpeak[%]
P1dB
PSAT PAE

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Performance Summary and Comparison
Reference
Tech.
& Vdd
Gain
[dB]
BW
[GHz]
GBW
[GHz]
PSAT
[dBm]
P1dB
[dBm]
PAE
[%]
Frac.
BW [%]
[W1] 65nm / 1.8V 16 21.0 133 13.0 8.0 8.0 35
[W2] 65nm / 1V 16 9.0 57 11.5 n.d. 15.2 15
[W3] 45nm / 2V 20 13.0 130 14.5 11.2 14.4 22
[W4] 65nm / 1.2V 18 12.5 99 9.6 n.d. 13.6 21
[CS1] 28nm / 1V 13 27.0 121 13.0 12.0 16.0 51
Largest bandwidth with state-of-the-art efficiency
and output power

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Power Combining
• Transformer-based combiner/splitter is popular
– Compact size 
– Low insertion loss 
– Generally low bandwidth 
• Wideband combining with coupled resonators
• Power combining mandatory for high POUT in CMOS PAs

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Wideband Combiner
• Easy to transform
– Divide the left network into two same parts

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Wideband Splitter
• Easy to transform
– Divide the right network into two same parts

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Comparison with Transformer Splitter
20 40 60 80 100
10
20
30
40
50
Frequency [GHz]
TrasnimpedanceGain[dBOhm]
Designed Power Splitter
Simple Tuned Transformer
More than two times
GBW improvement.
Practical
impedance

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Complete Schematic
• A prototype has been designed in ST 65nm CMOS:
– Bandwidth > 13 GHz
– Gain > 25dB
– OP1dB > 15dBm
– PAE > 20%
120u/60n 120u/60n 240u/60n
120u/60n 240u/60n

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Chip Microphotograph
ST 65nm CMOS
Chip area: 0.57 mm2
Core area: 0.11 mm2

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Measured S-Parameters
Gain≈30dB, BW3dB: 58.5-73.5GHz
40 50 60 70 80 90
-60
-40
-20
0
20
40
Frequency [GHz]
S-Parameters[dB]
S21
S12
S11
S22

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Large Signal Performance at 65GHz
PSAT≈20dBm, P1dB≈16dBm, PAE ≈ 22%, Pdc ≈ 470mW
-20 -15 -10 -5 0 5
0
5
10
15
20
25
30
35
Input Power [dBm]
Pout[dBm]/Gain[dB]/PAE[%] Pout Gain PAE

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Large Signal Performance vs Frequency
P1dB>15dBm, PAE>15% over the bandwidth
60 65 70 75
12
14
16
18
20
22
24
Frequency [GHz]
S-Parameters[dB]
Peak PAE
Pout
P1dB

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Performance Summary and Comparison
State-of-the-art PSAT and PAE with the largest GBW
Reference
Tech.
& Vdd
Gain
(dB)
BW
(GHz)
GBW
(GHz)
PSAT
(dBm)
P1dB
(dBm)
PAE
(%)
[W5] 28nm / 1V 24 11 174 16.5 11.7 13
[W6] 40nm / 1V 17 6 42 17 13.8 30
[W7] 65nm / 1.2V 17.7 12 92 16.8 15.5 15
[W8] 28nm SOI/ 1V 35 8 450 18.9 15 18
[CS2] 65nm / 1V 30 15 474 20 16 22

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Conclusions
• High GBW is critical for PAs to achieve high efficiency over large
bandwidth
• Coupled resonator can improve PA GBW while forming compact
layout
• A methodology was proposed to build wideband combiner/splitter
using coupled resonators
• A [CS1] two-stage one-path PA with 13dBm PSAT, 16% PAE, and 27
GHz BW in 28nm CMOS and a [CS2] three-stage two-path PA with
20dBm PSAT, 22% PAE, and 15GHz BW in 65nm CMOS demonstrate the
effectiveness of the proposed techniques

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References
[CS1a] J. Zhao, M. Bassi, A. Bevilacqua, A. Ghilioni, A. Mazzanti and F. Svelto, "A 40–67GHz power amplifier with 13dBm PSAT and 16% PAE in 28
nm CMOS LP," European Solid State Circuits Conference (ESSCIRC), ESSCIRC 2014 - 40th, Venice Lido, 2014, pp. 179-182.
[CS1b] M. Bassi, J. Zhao, A. Bevilacqua, A. Ghilioni, A. Mazzanti and F. Svelto, "A 40–67 GHz Power Amplifier With 13 dBm PSAT and 16% PAE in
28 nm CMOS LP," in IEEE Journal of Solid-State Circuits, vol. 50, no. 7, pp. 1618-1628, July 2015.
[CS2] J. Zhao, M. Bassi, A. Mazzanti and F. Svelto, "A 15 GHz-bandwidth 20dBm PSAT power amplifier with 22% PAE in 65nm CMOS," Custom
Integrated Circuits Conference (CICC), 2015 IEEE, San Jose, CA, 2015, pp. 1-4.
[W1] A. Siligaris et al., “A 65-nm CMOS fully integrated transceiver module for 60-GHz wireless HD applications,” IEEE J. Solid-State Circuits, vol.
46, no. 12, pp. 3005–3017, Dec 2011.
[W2] W. Chan and J. Long, “A 58–65GHz neutralized CMOS power amplifier with PAE above 10% at 1-V supply,” IEEE J. Solid-State Circuits, vol. 45,
no. 3, pp. 554–564, March 2010.
[W3] M. Abbasi et al., “A broadband differential cascode power amplifier in 45 nm CMOS for high-speed 60GHz system-on-chip,” in Radio
Frequency Integrated Circuits Symposium (RFIC), 2010 IEEE, May 2010, pp. 533–536.
[W4] T. Wang et al., “A 55–67GHz power amplifier with 13.6% PAE in 65 nm standard CMOS,” in Radio Frequency Integrated Circuits Symposium
(RFIC), 2011 IEEE, June 2011, pp. 1–4.
[W5] S. Thyagarajan, A. Niknejad, and C. Hull, “A 60 GHz linear wideband power amplifier using cascode neutralization in 28 nm CMOS,” in
Custom Integrated Circuits Conference (CICC), 2013 IEEE, Sept 2013, pp. 1–4.
[W6] D. Zhao and P. Reynaert, “A 60-GHz dual-mode class AB power amplifier in 40-nm CMOS,” Solid-State Circuits, IEEE Journal of, vol. 48, no.
10, pp. 2323–2337, Oct 2013.
[W7] P. Farahabadi and K. Moez, “A dual-mode highly efficient 60 GHz power amplifier in 65 nm CMOS,” in Radio Frequency Integrated Circuits
Symposium, 2014 IEEE, June 2014, pp. 155–158.
[W8] A. Larie et al., “A 60 GHz 28 nm UTBB FD-SOI CMOS reconfigurable power amplifier with 21% PAE, 18.2 dBm P1dB and 74mW PDC,” in
Solid-State Circuits Conference - (ISSCC), 2015 IEEE International, Feb 2015, pp. 1–3.

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