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1. 02/19/15 1
VLSI Design and Layout PracticeVLSI Design and Layout Practice
Lect5 – Stick Diagram & ScalableLect5 – Stick Diagram & Scalable
Design RulesDesign Rules
Danny Wen-Yaw ChungDanny Wen-Yaw Chung
Institute of Electronic EngineeringInstitute of Electronic Engineering
Chung-Yuan Christian UniversityChung-Yuan Christian University
Sept. 2008Sept. 2008

2. 02/19/15 2Wen-Yaw Chung/Chung-Yuan University VLSI Design
IC Layout Concept and Examples
 I. Stick Diagram
 II. Design Rules
 III. Layout Verification
Ref: http://140.135.9.56/XMS/

3. 02/19/15 3Wen-Yaw Chung/Chung-Yuan University VLSI Design

4. 02/19/15 4Wen-Yaw Chung/Chung-Yuan University VLSI Design

5. 02/19/15 5Wen-Yaw Chung/Chung-Yuan University VLSI Design
A. Basic Concept
 1. Based on the view point of IC layout, the stick
diagram can help us understand the circuit function
and its geometrical location relative to other circuit
blocks.

Legend:
contact
metal 2
metal 1
poly
ndiff
pdiff
VDD
in
VSS
out
■

6. 02/19/15 6Wen-Yaw Chung/Chung-Yuan University VLSI Design
A. Basic Concept
 2. Although the stick diagram is an abstract
presentation of real layout, it can use
graphical symbols or legend to allocate the
circuit to 2-diomensional plane and reach the
aim same as the physical layout does.
 3. The stick diagram is similar to a
backbone of the real layout but without the
real size and aspect ratio of the devices, it
still can reflect the real condition to layout of
the silicon chip.

7. 02/19/15 7Wen-Yaw Chung/Chung-Yuan University VLSI Design
B. Notations of the stick diagram

8. 02/19/15 8Wen-Yaw Chung/Chung-Yuan University VLSI Design
Stick Diagram
 Intermediate representation
 between the transistor level and the mask (layout)
level.
 Gives topological information
 (identifies different layers and their relationship)
 Assumes that wires have no width.
 It is possible
 to translate stick diagram automatically to layout
with correct design rules.
[Ref]: 教育部顧問室
「超大型積體電路與系統設計」教育改進計畫
EDA 聯盟 – 推廣課程 Chap.1

9. 02/19/15 9Wen-Yaw Chung/Chung-Yuan University VLSI Design
Stick Diagram
 1. When the same material (on the same layer) touch or cross,
they are connected and belong to the same electrical node.
 2. When polysilicon crosses N or P diffusion, an N or P
transistor is formed.
 Polysilicon is drawn on top of diffusion.
 Diffusion must be drawn connecting the source and the drain.
 Gate is automatically self-aligned during fabrication.
[Ref]: 教育部顧問室
「超大型積體電路與系統設計」教育改進計畫
EDA 聯盟 – 推廣課程 Chap.1

10. 02/19/15 10Wen-Yaw Chung/Chung-Yuan University VLSI Design
Stick Diagram
 3. When a metal line needs to be connected to one of
the other three conductors, a contact cut (via) is
required.
[Ref]: 教育部顧問室
「超大型積體電路與系統設計」教育改進計畫
EDA 聯盟 – 推廣課程 Chap.1

11. 02/19/15 11Wen-Yaw Chung/Chung-Yuan University VLSI Design
Stick Diagram
 4. Manhattan geometrical rule: When we use only vertical
and horizontal lines In orthogonal to describe circuitry.
 Boston geometrical rule: The stick diagram also allows
curves to describe circuitry.
 5. In order to describe N/PMOS more completely, to
add n-well 、 P+ select 、 well contact and substrate
contact are optional for 4-terminal notation.

12. 02/19/15 12Wen-Yaw Chung/Chung-Yuan University VLSI Design
Conclusion
 1. Stick diagram is a draft of real layout, it serves
as an abstract view between the schematic and
layout.
 2. Stick diagram uses different lines, colors and
geometrical shapes to present circuit nodes,
devices, and their relative location.
 3. Stick diagram doesn’t include information about
the accurate coordinates and sizes of device, the
length and width of conductors and the real size of
well region.

13. 02/19/15 13Wen-Yaw Chung/Chung-Yuan University VLSI Design
CMOS Inverter Stick
Diagrams
 Basic layout
․ More area efficient layout
[Ref]: 教育部顧問室
「超大型積體電路與系統設計」教育改進計畫
EDA 聯盟 – 推廣課程 Chap.1

14. 02/19/15 14Wen-Yaw Chung/Chung-Yuan University VLSI Design
 CMOS inverter described in other way.
VDD
in
VSS
out
CMOS Inverter Stick
Diagrams

15. 02/19/15 15Wen-Yaw Chung/Chung-Yuan University VLSI Design
CMOS Transmission Gate
The transmission gate Circuit schematic Stick diagram

16. 02/19/15 16Wen-Yaw Chung/Chung-Yuan University VLSI Design
CMOS Stick Diagrams NAND/NOR

17. 02/19/15 17Wen-Yaw Chung/Chung-Yuan University VLSI Design
[Ref]: 教育部顧問室
「超大型積體電路與系統設計」教育改進計畫
EDA 聯盟 – 推廣課程 Chap.1
CMOS Stick Diagrams NAND

18. 02/19/15 18Wen-Yaw Chung/Chung-Yuan University VLSI Design
< Exercise 1 >
To draw the following circuitry by using a stick diagram

19. 02/19/15 19Wen-Yaw Chung/Chung-Yuan University VLSI Design
< Exercise 2 >
To draw the stick diagram and the schematic for the following layout
NWELL
NSELECT
PSELECT
POLY
ACTIVE
METAL1
NWELL
NSELECT
PSELECT
POLY
ACTIVE
METAL1

20. 02/19/15 20Wen-Yaw Chung/Chung-Yuan University VLSI Design
CMOS Stick Diagrams
[Ref]: 教育部顧問室
「超大型積體電路與系統設計」教育改進計畫
EDA 聯盟 – 推廣課程 Chap.1
NOR

21. 02/19/15 21Wen-Yaw Chung/Chung-Yuan University VLSI Design
CMOS Inverter Mask Layout
Min. spacing and
line width consideration

22. 02/19/15 22Wen-Yaw Chung/Chung-Yuan University VLSI Design
Lambda-based Design Rules
 Lambda design rules are based on a
reference metric λthat has units of um.
 All widths, spacing and distances are
written in the form  Value = m λ
Where m is scaling multiplier.
<e.g.> λ= 1um  w = 2 λ=2um
s = 3λ=3um

23. 02/19/15 23Wen-Yaw Chung/Chung-Yuan University VLSI Design
Lambda based design: half of technology since 1985. As technology
changes with smaller dimensions, a simple change in the value of λ can
be used to produce a new mask set.
All device mask dimensions are based on multiples of λ, e.g., polysilicon
minimum width = 2λ. Minimum metal to metal spacing = 3λ
6λ
2λ
6λ
λ
3λ
3λ
Lambda-based Design Rules

24. 02/19/15 24Wen-Yaw Chung/Chung-Yuan University VLSI Design
Active Contact and Surround Rule

25. 02/19/15 25Wen-Yaw Chung/Chung-Yuan University VLSI Design
Potential Problem - Misalignment

26. 02/19/15 26Wen-Yaw Chung/Chung-Yuan University VLSI Design
Potential Problem – Short between Source and Drain

27. 02/19/15 27Wen-Yaw Chung/Chung-Yuan University VLSI Design
Degree of anisotropy A = 1 – rlat/rvert
Where r  respective etch rates
Physical Limitations

28. 02/19/15 28Wen-Yaw Chung/Chung-Yuan University VLSI Design
Design Rule (0)
 Due to the photo resolution, concentration,
temperature and reaction time of the chemical
reagents, the layout should tolerate some errors
caused by process environment.
 In order to avoid the influence from process
variation, the layout of the circuit schematics
should follow the design Rule 。

29. 02/19/15 29Wen-Yaw Chung/Chung-Yuan University VLSI Design
The purpose of design rules
 Ref. Jan M. Rabaey, et. al, © Digital
Integrated Circuits 2nd Edition
 Interface between designer and process
engineer
 Guidelines for constructing process masks
 Unit dimension: Minimum line width
 scalable design rules: lambda parameter
 absolute dimensions (micron rules)

30. 02/19/15 30Wen-Yaw Chung/Chung-Yuan University VLSI Design
Design Rules(1)
 Layout rules are used for preparing the masks for
fabrication.
 Fabrication processes have inherent limitations in
accuracy.
 Design rules specify geometry of masks to optimize yield
and reliability (trade-offs: area, yield, reliability).
 Three major rules:
 Wire width: Minimum dimension associated with a
given feature.
 Wire separation: Allowable separation.
 Contact: overlap rules.
[Ref]: 教育部顧問室
「超大型積體電路與系統設計」教育改進計畫
EDA 聯盟 – 推廣課程 Chap.1

31. 02/19/15 31Wen-Yaw Chung/Chung-Yuan University VLSI Design
Design Rules(2)
 Two major approaches:
 “Micron” rules: stated at micron resolution.
 λ rules: simplified micron rules with
limited scaling attributes.
 λ may be viewed as the size of minimum
feature.
 Design rules represents a tolerance which
insures very high probability of correct
fabrication (not a hard boundary between
correct and incorrect fabrication).
 Design rules are determined by experience.
[Ref]: 教育部顧問室
「超大型積體電路與系統設計」教育改進計畫
EDA 聯盟 – 推廣課程 Chap.1

32. 02/19/15 32Wen-Yaw Chung/Chung-Yuan University VLSI Design
Terminology & Definition
 Min. Width : The min. width of the line
(layer)
 <Example> Wpoly(min.) = 0.5um
 Min. Space : The min. spacing between
lines with same material
 <Example> Spoly-poly(min.) = 0.5um

33. 02/19/15 33Wen-Yaw Chung/Chung-Yuan University VLSI Design
 <Min. Extension : The min. extension over different
layers
 <Example> Poly-gate extension over diffusion area =
0.55um
 Min. Overlap : The overlap between different layers
 <Example> Poly1 overlap Poly2 min. = 0.7um
Terminology & Definition

34. 02/19/15 34Wen-Yaw Chung/Chung-Yuan University VLSI Design
Terminology & Definition
 Max. area of the specific region.
 <Example> Bonding Pad Area, max. = 100um x
100um

35. 02/19/15 35Wen-Yaw Chung/Chung-Yuan University VLSI Design
Conventional Layer Definition
Layer
Polysilicon
Metal1
Metal2
Contact To Poly
Contact To Diffusion
Via
Well (p,n)
Active Area (n+,p+)
Color Representation
Yellow
Green
Red
Blue
Magenta
Black
Black
Black
Select (p+,n+) Green
Layer
Polysilicon
Metal1
Metal2
Contact To Poly
Contact To Diffusion
Via
Well (p,n)
Active Area (n+,p+)
Color Representation
Yellow
Green
Red
Blue
Magenta
Black
Black
Black
Select (p+,n+) Green
Layer
Polysilicon
Metal1
Metal2
Contact To Poly
Contact To Diffusion
Via
Well (p,n)
Active Area (n+,p+)
Color Representation
Yellow
Green
Red
Blue
Magenta
Black
Black
Black
Select (p+,n+) Green

36. 02/19/15 36Wen-Yaw Chung/Chung-Yuan University VLSI Design
SCMOS Design Rules
IntraIntra--Layer Design RulesLayer Design Rules
Metal2
4
3
Ref. Jan M. Rabaey, et. al, © Digital Integrated Circuits 2nd Edition

37. 02/19/15 37Wen-Yaw Chung/Chung-Yuan University VLSI Design
SCMOS Design Rules
1
2
1
Via
Metal to
Poly ContactMetal to
Active Contact
1
2
5
4
3 2
2

38. 02/19/15 38Wen-Yaw Chung/Chung-Yuan University VLSI Design
SCMOS Design Rules
1
3 3
2
2
2
Well
Substrate
Select
3
5

39. 02/19/15 39Wen-Yaw Chung/Chung-Yuan University VLSI Design
SCMOS Design Rules
[Ref]: 教育部顧問室
「超大型積體電路與系統設計」教育改進計畫
EDA 聯盟 – 推廣課程 Chap.1

40. 02/19/15 40Wen-Yaw Chung/Chung-Yuan University VLSI Design
MOSIS Layout Design Rules
 MOSIS design rules (SCMOS rules) are available at
http://www.mosis.org.
 3 basic design rules:
 Wire width
 Wire separation
 Contact rule
 MOSIS design rule examples
[Ref]: 教育部顧問室
「超大型積體電路與系統設計」教育改進計畫
EDA 聯盟 – 推廣課程 Chap.1

41. 02/19/15 41Wen-Yaw Chung/Chung-Yuan University VLSI Design
III. Layout Verification
 A. Definition
 DRC – Design Rule Check
 ERC – Electrical Rule Check
 LVS – Layout Versus Schematic
 LPE – Layout Parameter
Extraction

42. 02/19/15 42Wen-Yaw Chung/Chung-Yuan University VLSI Design
Layout Verification
 B. DRC(Design Rule Check) ：
 => To check the min. line width and
spacing based on the design rules.
C. ERC(Electrical Rule Check) ：
 => To check the short circuit
between Power and Ground, or check
the floating node or devices.

43. 02/19/15 43Wen-Yaw Chung/Chung-Yuan University VLSI Design
Layout Verification
D. LVS(Layout versus Schematic) ：
 => To verify the consistency between Schematic
and Layout. For example ： to check the amount of
transistor numbers, sizes of W/L.
E. LPE or PEX(Layout Parameter
Extraction) ：
 => From the database of layout, to extract the
devices with parasitics including effective W/L,
parasitic capacitances and series resistance. The
extracted file is in SPICE format and can be used
for Post-Layout Simulation 。

44. 02/19/15 44Wen-Yaw Chung/Chung-Yuan University VLSI Design
Layout Verification
F. Simulations
Pre-Layout Simulation - before layout work
Post-Layout Simulation – after layout work, post layout
simulation will reflect more realistic circuit performance.

45. 02/19/15 45Wen-Yaw Chung/Chung-Yuan University VLSI Design
Layout Verification
The complete design environment of Fill-Custom Design
Design database – Cadence Design Framework II
Circuit Editor – Text editor/Schematic editor (S-edit,
Composer)
Circuit Simulator – SPICE,TSPICE, HSPICE
Layout Editor – Cadence Virtuoso, Laker, L-edit
Layout Verification Diva, Dracula, Calibre, Hercules

46. 02/19/15 46Wen-Yaw Chung/Chung-Yuan University VLSI Design
Concluding Remarks
 Milestones technology in silicon era
 Transistor  Integrated Circuits  CMOS
Technology
 Key weapons in SOC era
 Design Automation
 Design Reuse
 Breakthrough techniques in design automation
 Simulation (e.g., SPICE, Verilog-XL, etc.)
 Automatic Placement and Routing (APR)
 Logic Synthesis (e.g., Design Compiler)
 Formal Verification
 Test Pattern Generation
It is EDA that pushes the IC design technology forward !
[Ref]: 教育部顧問室
「超大型積體電路與系統設計」教育改進計畫
EDA 聯盟 – 推廣課程 Chap.1

47. 02/19/15 47Wen-Yaw Chung/Chung-Yuan University VLSI Design
[Ref.] John P. Uyemura, “Physical Design of CMOS
Integrated Circuits Using L-EDIT”, PWS Publishing Company, 1995.
SCNA Layout Rules

48. 02/19/15 48Wen-Yaw Chung/Chung-Yuan University VLSI Design
SCNA Layout Rules

49. 02/19/15 49Wen-Yaw Chung/Chung-Yuan University VLSI Design
SCNA Layout Rules

50. 02/19/15 50Wen-Yaw Chung/Chung-Yuan University VLSI Design
SCNA Layout Rules

51. 02/19/15 51Wen-Yaw Chung/Chung-Yuan University VLSI Design
SCNA Layout Rules

52. 02/19/15 52Wen-Yaw Chung/Chung-Yuan University VLSI Design
SCNA Layout Rules

53. 02/19/15 53Wen-Yaw Chung/Chung-Yuan University VLSI Design
LAB. 3
 Set#1 – Stick Diagram Practice
 Set#2 – Reverse Engineering