Ip so c-30sept2010
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The document discusses challenges in designing low power speech processing systems-on-chip (SoCs). It outlines C-DAC's focus on low power applications and describes their ASTRA portfolio of IPs. It then covers various low power design techniques like clock gating, power gating, voltage and frequency scaling. The document concludes by describing C-DAC's NAADA speech processor SoC that integrates these techniques and achieves less than 5mW power consumption.
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Kurt Shuler is the VP of Marketing at Arteris. He has previous experience at Intel, TI, and 3 startups. He has an MIT Sloan MBA and US Air Force Academy Engineering BS. Arteris delivers interconnect IP for on-chip and inter-chip communications based on networking techniques. It was founded in 2003 and has seen several milestones including first shipments in 2006, first silicon in 2007, first shipping systems in 2009, and becoming profitable in Q4 2010. Arteris serves the wireless, DTV, connectivity, automotive and consumer markets and has investors including ARM, Qualcomm, Synopsys, NTT DoCoMo and VCs.
The long road to IP commercialization
Since the birth of RMM in 1995, Semiconductor IP activities had grown from a pure R&D initiative into a significant factor of many SoC project budget.
For the last 25 the major growth of the SIP market was driven by Microprocessor, Memory and I/O vendors.
In recent years the landscape of SIP is changing and new horizons appear brought by new IP vendors representing variety of business models.
In this panel discussion, each of the speakers will have 5 – 10 minute to present its SIP commercialization practice and vision.
The second half of the talk will be dedicated for 3 – 4 questions that should be answer by each of the speakers, allowing the audience to evaluate the different opinions.
Rosetta ip commercialization panel
Omri Raisman presented on application specific intellectual property (ASIP) cores. Some key points:
1) An ASIP is an IP core that is specified, implemented, and verified for a specific targeted application, which allows for better optimization and cost-effectiveness compared to general purpose IP cores.
2) Verification of an ASIP can be more exhaustive since it is limited to the defined functionality for its targeted application.
3) Targeting an IP core to a specific application enhances its commercial value by reducing development costs and time to market.
Design and Reuse Panel
Bob Blake joined Altera's European product and technical marketing group in 2000. While at Altera, Bob has been responsible for the technical marketing of Altera's high-speed transceiver products and software design tools and methodologies. Mr Blake is currently the manager of the European Corporate and Product Marketing team; the team are responsible for marketing all Altera Products and tools within Europe. Mr. Blake has over twenty years of experience in the electronics industry within design, applications, and management roles, including systems design with embedded processors and programmable logic. Mr. Blake holds an honors degree in Electronic Engineering from Portsmouth University.
FPGA’s, Addressing New Markets With 44 & 28 nm Devices
The growing ASIC tape-out costs, countered by increased FPGA capacity, speed and lower cost are making FPGA’s an attractive solution for applications that have traditionally been using ASICs or ASSPs. A critical enabler for such a transition is the availability of a wider range of more complex Silicon IP cores that are proven and optimized in the new FPGA devices. Success will require Silicon IP providers, that have traditionally been providing FPGA IP, to be motivated to address more complex IP requirements and to migrate their IP to the new devices and that the traditional ASIC IP vendors shift their focus to support of FPGA requirements. Is this happening today, and what is most likely to happen in the near future?
Impact of New Super Size FPGAs
Beginning with a BSEE from Purdue University, Mr. Finch has held a variety of engineering, sales, and executive positions with companies including GenRad, Inc., Boreas, Inc., SemiTest, Inc., and the Brown and Sharp Manufacturing Company. His diverse areas of experience include microprocessor test, superconductivity research, semiconductor metrology tools, and defect analysis for the flat panel and semiconductor industries. Since joining CAST in 2001, Bill has helped shaped the evolving IP business with innovative product ideas and new licensing practices.
JOHARI Window based business approach for Marketing IP's and IP's based Solut...
1. The document discusses using the Johari Window model to develop a business approach for marketing intellectual properties and IP-based solutions.
2. It proposes modifying the Johari Window to distinguish between what is known to the company versus the market.
3. The document provides examples of "push" strategies like customization and "pull" strategies like highlighting very specialized applications to maintain the value of IPs over time as the market becomes aware of them.
A Real Future for Innovation in Silicon IP Business Models Using Open Source ...
Crack Semiconductor delivered very high customer value by using Open Source tools to implement and verify a remarkable design for our customer's RSA compute offload requirements in an aging platform. We describe a future where Silicon IP is more commonly developed with Open Source tools.
Over 20 years of embedded software development a third way emerges
The document discusses options for embedded software development, including commercial runtime software, in-house runtime software, and open source runtime software. It also discusses commercial tools versus open source tools. Commercial runtime software and tools provide benefits like being established, reliable, and having technical support, but have downsides like ongoing costs and vendor lock-in. In-house runtime has benefits like control and customization but has high development costs. Open source has advantages of being freely available but has issues like lack of long-term support and responsibility.
The past and the next 20 years? Scalable computing as a key evolution
1) ARM was founded in 1990 with 12 employees and has since grown to over 500 partners in 2011, driven by the success of their 32-bit processors.
2) Advances in silicon technology have led to phenomenal improvements in power, performance, and area over the past 20 years, with the Cortex-M0 being 1/10,000 the size of the original ARM1 processor.
3) The demands on chip design are increasing in terms of power efficiency, hardware and software reuse, and heterogeneous designs to meet the needs of an increasingly connected world where all devices are energy constrained.
7 Steps for IP Community Synergy: A China Market Based View Point
Mark is General Manager and Founder of Jiatao Industrial Co., Ltd. Located in Shanghai, in which their EDA team focusing on provide IP solutions and EDA tools to its customers in the region. Mark has more than 13 years working experience in IT and business consulting field. For the past two years, he was dedicated on marketing and promoting of high performance analogue and mixed signal IP products in great China region. Prior to the establishment of Jiatao, Mark worked for Swiss consulting firm CH-ina (Shanghai) Co., Ltd. as business consultant and project manager. There his main responsibility is to establish new business operations in China for Swiss and European customers. From year 1996 to year 2004 Mark worked as system analyst and project manager for Cyber Data Processing (CDP) Shenzhen, China.
IP's 20 year evolution - adaptation or extinction
From its infancy 20 years ago, the semiconductor IP industry has evolved into the major driving force of today’s semiconductor landscape. This talk will take a historical view of the changes in the industry over the past twenty years, looking at how the landscape (environment) has changed and how individual companies either adapted or simply went away. What will the IP industry and players in the future look like?
Rise and Fall of New Fabless Startups => New Model for IP/ASSP Collaboration
The document discusses the decline in the number of fabless chip startups since 2000 and proposes a new business model called ASAP (A new business model for IP companies) to help address this. The ASAP model involves partnering between an IP startup and Tabula, where Tabula provides the silicon platform, manufacturing, marketing and sales support to help the startup launch application-specific standard products with zero non-recurring engineering costs. This new model could lead to the next wave of growth for fabless startups.
Gda Panel
The panel discussion focused on India emerging as an IP powerhouse. It introduced panelists from three companies - Cosmic Circuits, Softjin, and Ittiam. Cosmic Circuits presented on their analog IP portfolio. Softjin discussed their focus on FPGA-based design services and IP products. Ittiam outlined their multimedia and communications IP and opportunities in licensing specialized IP components. Key opportunities discussed were India's talent base and the benefits of an IP licensing model. Challenges included long ROI cycles and changing market factors.
Panel presentation2
This document summarizes a panel discussion on the past, present, and future of the semiconductor industry in India. The panelists discussed the evolving business model of the semiconductor industry, opportunities for growth in India, gaps in India's semiconductor ecosystem, and how industry bodies, academia, and investment can help boost India's homegrown product companies and entrepreneurs entering the industry. The panel then took questions on topics like how the lack of local fabrication is impacting India's industry scope and how to promote the first success stories of Indian semiconductor companies.
Mymo wireless presentation_30_jul'10
The document summarizes key aspects of 4th generation wireless systems with a focus on 3GPP LTE. It discusses the key drivers for 4G technologies including the growth of cellular users and transition to IP-based networks. It provides an overview of 3GPP LTE as the emerging 4G standard, describing it as a flat IP-based air interface that uses technologies like OFDMA and MIMO. It also summarizes some key LTE technologies such as OFDM and OFDMA and how they work.
Mind tree ip soc
This document discusses challenges in re-engineering intellectual property (IP) for reuse. It outlines IP re-engineering activities like design modifications, verification, and integration. Challenges include porting to new technologies, ensuring quality documentation, and supporting different teams. Using an external team can help with costs and focus but requires capabilities like training and support for various platforms. Standard processes, frameworks, and IP qualification are important for successful IP re-engineering.
Ip so cday_isa_panel_10_scg
The document discusses the evolution of semiconductors in India. It notes some key inventions in semiconductor electronics such as the integrated circuit by Jack Kilby in 1958. It then discusses how semiconductors have impacted various areas like communication, entertainment, healthcare, and more. The document estimates that India's semiconductor market will be around $7 billion in 2010 and notes various growth drivers for the Indian semiconductor industry like handsets, smart cards, LCD TVs, and more. It concludes by stating that the Indian semiconductor market is poised for growth and that nurturing innovation will be key to fueling that growth.
Ip provider life cycle bangalore
The document outlines the life cycle of intellectual property (IP) providers and the semiconductor industry. It discusses the trends driving consolidation in the industry, including rising costs of chip design that favor larger players. It also covers topics like growing use of third-party IP, the realities for small IP providers, patenting strategies, patent wars between companies, and the typical acquisition timelines and sizes for IP providers.
Gda ipsoc blr_hic_final
The document discusses design challenges and trends in high speed interconnect IPs. It covers topics like the rationale for high speed serial interconnects, comparisons of technologies like PCIe, SRIO, and USB 3.0, and challenges in adopting interconnect IPs. It also provides overviews of specific high speed interconnect IPs from GDA like their USB 3.0 and DVB-H solutions, and how their configurable and verified IPs aim to overcome adoption challenges.
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FPGA’s, Addressing New Markets With 44 & 28 nm Devices
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