1. Design Challenges & Trengs in High Speed Interconnect IPsRavi ThummarukudyL&T Infotech/GDA Sept 2010 Confidential | Copyright © Larsen & Toubro Infotech Ltd.

3. Rationale for High Speed Serial Interconnects

4. Comparison of High Speed Connectivity

5. Challenges of IP adoption

6. Software IP

7. USB 3.0 Overview

10. Presence : NA, APAC, Europe, Middle East, Africa

12. Wholly owned subsidiary of Larsen & Toubro Ltd.

13. 7 decade history in India as a premier engineering company

14. Revenues: US$ 9.8 BillionManufacturing – Packaged Goods Product Engineering Services Corporate Certifications

15. Product Engineering Services

17. PS >1Kwatt

18. Chip Cost

19. System Cost

20. Multi-Core CPU-GPU

21. Pins

22. Power Awareness

23. Application Awareness

24. Connectivity Requirements

25. Process Nodes

26. SiP

27. SOC

29. OCTEON II – Block Diagram Source: Cavium Website

31. X2 10GbE (XAUI Based )

33. Security Engine (10Gb/S)

35. eNodeB

36. Enterprise Gateways

37. Mobile Broadband RNC ApplicationsSource: LSI Logic Website

38. Next Gen Wireless Baseband Processor SOC Source: Mind speed Website

39. PCI Express Interconnect

40. MIPI IPs Camera Tx Display Rx DSI -1 CSI -2 Tx Application Processor SoC Rx Display Rx Co-Processor SoC Tx Tx D-PHY D-PHY DSI -2 Base Band Processor SOC MPHY PA RF DIG RF

41. USB – Super Speed Interconnect Source: USB IF

42. High Speed Interconnects – Comparison PCIe 2.5 Gb/s – 8Gb/s SRIO – Rev 1.3 supports 1.0Gbps; Rev 2.0 - 3.125Gbps, 5Gbps & 6.125Gbps XAUI – 3.125Gbps – 6.125Gbps USB 3.0 – 5Gbps MULTI – PROTOCOL SERDES 1Gb/s – 10Gb/s – PHY’s 13

43. Memberships

44. IP Channels ASIC/Design Service Companies IP Vendor Silicon Vendors OEM/ODM IP IP Integration Services

45. HW Interconnect IP Portfolio Hyper Transport Cave Tunnel Host Bridge Switch Port PCI Express* Endpoint Root Complex Switch port/Switch AMBA Bridge Rapid IO* Serial Parallel AXI Bridge Processor* IBM Power PC 405 Power PC 460 Ethernet* 10/100/1G MAC 10G MAC HiGig DDR3/2 Controller Interlaken DP/HDMI MIPI* SPI 4.2* Single channel Multi channel Security IPs 3DES, AES, MD5, RSA, SHA2, HDCP, BISS-E USB3.0 Device Host Hub GPON OLT MAC

46. IP Portfolio AMBA 3 AXI & AMBA 2.0 AHB HDMI Controller Memory DDR3/2 CTRL Power PC ARM IPMI Display Port Controller DLNA LTE- UE USB 2.0/3.0 Host, Hub Device X86 DSP MIPS DVB-H TRO69 SoftwareIP PCIe Gen1/2/3 Controller HT SRIO Ethernet MIPI/UNIPRO HW IP

47. INTERCONNECT APPLICATIONS

48. HW IP Reference Platforms PCIe Platform DDR Memory Platform Market Leader in Interconnect IP Reference Platforms USB 3.0 Platform 10-GbE Platform MIPI Platform

49. Integration Quality Verification Qualifying IP Cost Lack of Stds Timing Reuse Vendor Relation 0% 5% 10% 15% 20% 25% 30% IP Adoption Challenges Top 3 Issues Source: Gartner Percentage of Survey Respondents

50. Confidential | Copyright © Larsen & Toubro Infotech Ltd. 21

52. FDD Mode operation

53. PHY and OS agnostic protocol stack

54. Protocol abstraction for allowing inter-operability with 3rd party applications

55. APIs for MAC-PHY interfaceCommercial Grade UE stack compliant to 3GPP Rel.8 March’09 specs 22

57. This components is completely modular in architecture and ANSI C compliant

58. Support for JSR 272

59. This component can be easily portable to various OS

60. Windows Mobile, Symbian

62. PSI/SI

63. ESG Engine

64. OS Abstraction Layer

65. Receiver Abstraction Layer for tuner abstraction

66. Integration Layers for XML, Media Player and Zip

67. Application APIs

68. OMA-BCAST and IPDC support

69. IPv4 and IPv6 support .

71. ACS initiated dynamic provisioning of CPE

72. Diagnostics information reporting from CPE and diagnostic test

73. Web identity management for customizing web content

74. Configurable transport level security

75. Authentication with shared secrets and MD5 Digest

76. Platform independent – integration layers

77. APIs and Parameter Mapping for device specific integration

78. Vendor specific parameter support

79. Data Models support - IGD, STB, VoIP, NAS, PON devices

80. TR-069 CWMP v1.1 Amendment 2

81. TR-111 LAN device management

82. HTTP v1.1

83. SSL 3.0 / TLS 1.0

84. SOAP v1.1 (Using GSOAP v2.7.10)

85. Linux kernel v2.6

86. Supported Data Models:

87. TR-098, TR-106 (IGD)

88. TR-104, TR-110 (VoIP)

89. TR-135 (STB)

90. TR-140 (NAS)

91. TR-142 (PON)Confidential | Copyright © Larsen & Toubro Infotech Ltd. 24

92. USB 3.0 (Super Speed) 25

94. Backwards compatible to USB 2.0

95. Almost 2X more power over cable

96. Similar connector foot print

97. New power management features

99. Newer applications demanding faster connectivity between PC and peripherals

100. HD Video applications in Net books, Portable Media Players, Mobile phones etc

101. Better energy efficiency overall

102. Stay ahead of competing technologies

104. USB 2.0 vs. USB 3.0

105. USB3.0 Design Challenges Integration of Design IP, VIP and SW Stack Legacy Integration Verification and Validation Compliance and Interoperability Performance, Latency Low Power Software Support

106. Pravega USB3 Device/Host Solution PBUS/APB Interface Application Interface ROM Interface DMA/xHCI EP0 Processor Application Layer Pravega SuperSpeed Core USB2.0 Controller (Optional) PRX PTX PCTL Protocol Layer Speed Select USB3 & USB2 Device xHCI Host Dual Mode Hub 32 & 64 DP* 8/16/32 Bit PIPE LRX LCTL LTX Link Layer Receive Control Transmit USB3 PIPE IF UTMI /ULPIIF PCS USB2 PHY PMA USB2 IF USB3 IF

107. Confidential © L&T Infotech / GDA Technologies, Inc. Pravega USB3 Hub Solution PBUS Interface ROM Interface USB3 PIPE IF Receive Transmit Control LRX LTX LCTL Link Layer R E G I S T E R S E T PRX PCTL PTX Protocol Layer Pravega SuperSpeed DPN Pravega SuperSpeed DP0 PRX PTX PRX PTX PCTL PCTL Pravega SuperSpeed UP Protocol Layer Protocol Layer PNPI USB3 Hub 32 & 64 DP* 8/16/32 Bit PIPE Hub Core Matrix Header Aggregator EP0 Processor Header Router LRX LCTL LRX LCTL LTX LTX Link Layer Link Layer PNPI Receive Control Transmit Receive Control Transmit PNPI USB3 PIPE IF USB3 PIPE IF

109. Provides huge options for Hardware and Software configurability

110. Verified against 3rd Party VIPs

111. Interoperated with USB3 PIPE Compliant PHYs

112. Passes Protocol Compliance tests (USB3CV)

113. In-House Validation platform for Device, Host and Hub functionality and Application Drivers

115. GDA USB Validation Platform Xilinx Virtex5-xcv110T-2 FPGA or xcv200T-2 One USB3 STD A Host Receptacle One USB3 STD B Device Receptacle USB PIPE Connector On board micron ONFI Flash One PCIe Edge Connector One PCIe Slot Connector

116. Pravega Device Controller Validation Setup

118. There are many challenges in IP adoption and careful planning and verification is the key

119. Configurability , Compliance and inter operability are key requirements in selecting the right IP

120. Questions?