The document discusses design challenges and trends in high speed interconnect IPs. It covers topics like the rationale for high speed serial interconnects, comparisons of technologies like PCIe, SRIO, and USB 3.0, and challenges in adopting interconnect IPs. It also provides overviews of specific high speed interconnect IPs from GDA like their USB 3.0 and DVB-H solutions, and how their configurable and verified IPs aim to overcome adoption challenges.

1. Design Challenges & Trengs in High Speed Interconnect IPsRavi ThummarukudyL&T Infotech/GDASept 2010Confidential | Copyright © Larsen & Toubro Infotech Ltd.

2. AgendaIntroduction and Background

3. Rationale for High Speed Serial Interconnects

4. Comparison of High Speed Connectivity

5. Challenges of IP adoption

6. Software IP

7. USB 3.0 Overview

8. Answer any questions on the above topicsTop 100 innovative service providers,2009- Global ServicesCompany OverviewGlobal provider of comprehensive, end-to-end

9. software & hardware services & solutionsManufacturing – Hi Tech ProductsInsurance15+ years of international experience

10. Presence : NA, APAC, Europe, Middle East, Africa

11. Company Strength: 11,000+; Revenue: US$ 432MEnergy & Petrochemical25 Fortune-100 customersIndustry PresenceBanking & Financial ServicesAmongst India’s Leading software companies

12. Wholly owned subsidiary of Larsen & Toubro Ltd.

13. 7 decade history in India as a premier engineering company

14. Revenues: US$ 9.8 BillionManufacturing –Packaged GoodsProduct Engineering ServicesCorporate Certifications

15. Product Engineering Services

16. PerformanceCostSpacePowerINCREASEREDUCTIONREDUCTIONREDUCTIONHigh Speed Interconnect RationaleCabling

17. PS >1Kwatt

18. Chip Cost

19. System Cost

20. Multi-Core CPU-GPU

21. Pins

22. Power Awareness

23. Application Awareness

24. Connectivity Requirements

25. Process Nodes

26. SiP

27. SOC

28. Integration & BandwidthSOC versus SiP TradeoffsIP CoresDFT LogicGlue LogicProcessor CoresBus ArchitectureMemoryEmbedded CoreCommunication & Interface PeripheralsAnalogCircuitry

29. OCTEON II – Block DiagramSource: Cavium Website

30. Multicore Communications Processor SOCFeatures:PowerPC Processor Up to Quad PowerPC 476 CoresSerial High-Speed Interfaces:x1/x4 SRIO upto 3.125Gb/s

31. X2 10GbE (XAUI Based )

32. X1/x2/x4 PCIeupto 5Gb/s upto 3 portsAcceleration Engines: Packet Processing (20Gb/s)

33. Security Engine (10Gb/S)

34. Traffic Manager/Scheduler ( upto 6levels of hierarchy )Applications: 3G/4G Mobile Access Systems