Curtiss-Wright has a long history with its roots dating back to the Wright brothers' first flight in 1903 and continues that path of innovation and advanced engineering, applying that expertise to mission critical applications in aerospace, naval and land markets. The Avionics & Electronics division (CWC-AE) invests heavily in research and development to ensure it maintains the technology leadership required to deliver high performance COTS and custom engineered products to the aerospace market. CWC-AE has over two decades experience in developing FTI solutions including data acquisition, Ethernet, recording and real-time ground station. Our customers include all of the major aerospace prime contractors and test agencies with products supplied to over 300 platforms in 40 countries worldwide.
For more details visit www.cwc-ae.com
CWC-AE provides the most widely-installed FTI system in the world with more flight hours than any other. We lower risk by supplying COTS hardware that has been proven on every platform type in all environmental conditions and delivers data reliably every time thanks to its ‘works once, works always’ finite state machine construction. The COTS design results in short lead times ensuring the hardware is delivered quickly.
Traditional vs. SoC FPGA Design Flow A Video Pipeline Case StudyAltera Corporation
This presentation compares the impact of traditional FPGA engineering design flow to one employed with an SoC FPGA. The two approaches will be contrasted in terms of their impacts on system architecture design, debugging, risk mitigation, system integration, bring-up, feature enhancements, design obsolescence, and engineering effort. A case study is presented that explores these impacts within a video pipeline development effort.
High Speed Data Connectivity: More Than Hardware (Design Conference 2013)Analog Devices, Inc.
In wireless communications and data acquisition systems, there is more to consider when designing and implementing a complete solution beyond simply physically connecting a high speed analog module to an FPGA platform. Available hardware description language (HDL) components and software are critical to establish an interface, which is necessary for practical system integration. This session starts with a top-level overview of various physical interfaces that are typically used and provides an in-depth focus on high speed serial JESD204B. Prototype HDL used for these types of boards is covered, along with the specific board components and how they are used to interface to high speed ADCs and DACs. Linux device drivers for the HDL components as well as for the ADI components are presented. This includes a short introduction into the Industrial I/O (IIO) framework, the benefits it offers, and how it can be used in end designs.
Curtiss-Wright has a long history with its roots dating back to the Wright brothers' first flight in 1903 and continues that path of innovation and advanced engineering, applying that expertise to mission critical applications in aerospace, naval and land markets. The Avionics & Electronics division (CWC-AE) invests heavily in research and development to ensure it maintains the technology leadership required to deliver high performance COTS and custom engineered products to the aerospace market. CWC-AE has over two decades experience in developing FTI solutions including data acquisition, Ethernet, recording and real-time ground station. Our customers include all of the major aerospace prime contractors and test agencies with products supplied to over 300 platforms in 40 countries worldwide.
For more details visit www.cwc-ae.com
CWC-AE provides the most widely-installed FTI system in the world with more flight hours than any other. We lower risk by supplying COTS hardware that has been proven on every platform type in all environmental conditions and delivers data reliably every time thanks to its ‘works once, works always’ finite state machine construction. The COTS design results in short lead times ensuring the hardware is delivered quickly.
Traditional vs. SoC FPGA Design Flow A Video Pipeline Case StudyAltera Corporation
This presentation compares the impact of traditional FPGA engineering design flow to one employed with an SoC FPGA. The two approaches will be contrasted in terms of their impacts on system architecture design, debugging, risk mitigation, system integration, bring-up, feature enhancements, design obsolescence, and engineering effort. A case study is presented that explores these impacts within a video pipeline development effort.
High Speed Data Connectivity: More Than Hardware (Design Conference 2013)Analog Devices, Inc.
In wireless communications and data acquisition systems, there is more to consider when designing and implementing a complete solution beyond simply physically connecting a high speed analog module to an FPGA platform. Available hardware description language (HDL) components and software are critical to establish an interface, which is necessary for practical system integration. This session starts with a top-level overview of various physical interfaces that are typically used and provides an in-depth focus on high speed serial JESD204B. Prototype HDL used for these types of boards is covered, along with the specific board components and how they are used to interface to high speed ADCs and DACs. Linux device drivers for the HDL components as well as for the ADI components are presented. This includes a short introduction into the Industrial I/O (IIO) framework, the benefits it offers, and how it can be used in end designs.
JESD204B Survival Guide: Practical JESD204B Technical Information, Tips, and ...Analog Devices, Inc.
Free downloadable PDF book for analog and FPGA designers. The guide provides an introduction to JESD204B – the new data converter interface standard – and explains why JESD204B is important, how it is used with high-speed A/D and D/A converters as well as providing trouble shooting tips and how-to articles. By Analog Devices, Inc.
by Analog Devices, Inc. - the World’s Data Converter Market Share Leader
Demystifying the JESD204B High-speed Data Converter-to-FPGA interfaceAnalog Devices, Inc.
Learn all about the JESD204 standard. This presentation provides an overview of the JESD204 serial interface standard from its origin up to the current "B" revision. Common "high-performance metrics" that are associated with high speed serial interfaces are also discussed. by Analog Devices, Inc.
In this Case Study read about Mistral’s expertise in designing a flexible and easily upgrade-able Video recording & processing solution with high resolution and frame rate for defense and aerospace applications.
Acquired analog signals can be manipulated and processed by either the analog or digital portions of a system, for example, through filtering, multiplexing, and gain control. The analog portions of a system can typically provide reasonably simple processing at fairly low cost, power, and overhead. Digital processing can provide far greater analysis power and can alter the nature of the analysis without changing hardware. Sampling theory, however, must be taken into account. This session covers the signal chain basics from signal to sensor to amplifier to converter to digital processor and back out again.
Webinar – Bluetooth Low Energy Power ControlEmbarcados
Bluetooth Low Energy Power Control também é conhecido como LE Power Control (LEPC) foi introduzido na especificação BLE 5.2. Esta funcionalidade permite que a sua aplicação controle o nível de potência do transmissor Bluetooth Low Energy automaticamente para obter o melhor link de rádio frequência com o menor consumo de energia.
Objetivo do Webinar
Aprenda como utilizar o BlueNRG-LP certificado BLE 5.2 e a função LE Power Control , otimize o consumo de energia da sua aplicação e faça sua bateria durar mais tempo.
Reusable Video IP Cores give software engineering service providers flexibility and less time to market while catering to the ever increasing demands of customers. Read on to know more about the Reusable IP Cores developed by NeST Software.
Multi Channel Multi Clock Frequency Speed Rate Real Time Industrial Standard ...theijes
The Aim is for HDL Design Architecture and Implementation of Multi clock frequency synchronized real time industrial standard parallel Hi-tech PRBS CDMA Transceiver Bus Array ASIC SOC /Card for Ultra high Speed real time Industrial Communication Interface Cards/Products like Data Acquisition and Tracking of wireless Data Communication Protocol Interface Cards/SOC’s like Data Serializer, De-serializer, Data Communication Protocol interface ADD on cards/Products, FPGA Cards of Different Data Transfer Baud rate. This Design Consists of multiple parallel C.D.M.A Transmitters and Receiver ASIC I.P Cores , Data Transmission and Reception done by Different Clock Frequencies operated at Mega/Giga / Tera/ Peta/Exa/Zetta/Yotta/Xona/Weka Clock Frequencies. Data Transmission Speed In terms Mega/Giga/Tera/Peta/Exa/Zetta/Yotta/Xona/Weka Bytes/Frames/Super Frames etc. and also Data transmitter and receiver consists of base band signal and Carrier signal generators, Channel Encoder, Decoder, Modulator and Demodulator generates modulation and Demodulation signal by spreading and dispreading through different communication frequency spread Spectrum techniques DSSS Communication, FH , Chaos for high Bandwidth , the design done through parallel distributed computing technique, data transmission and reception done parallel for various data interface cards of different data transfer speed. In this design transmission and reception done by different PRBS Data Pattern Sequences like 2e7 -1, 2e10 -1, 2e15 -1, 2e23 -1, 2e31 -1, 2e48 -1, 2e52 -1, 2e63 -1 etc. H.D.L FPGA Industrial Software Design Flow Process Implementation Done by either Xilinx/Altera. Programming Done by Verilog /VHDL Software and Simulation, Synthesis, ASIC Floor planning and Placement and routing, Reconfiguration and Debugging Done Xilinx ISE 9.2i/10.1i EDA Software and Xilinx /Altera FPGA Development Board/Kit.
Discuss how to navigate in the Military RF Multi Chip Module (MCM) arena using commercial technology.
Discuss how to develop a successful strategy to
support typical Military Product Life Cycles
in conflict with Moore’s Law.
Discuss the Future of Microelectronics Technology
JESD204B Survival Guide: Practical JESD204B Technical Information, Tips, and ...Analog Devices, Inc.
Free downloadable PDF book for analog and FPGA designers. The guide provides an introduction to JESD204B – the new data converter interface standard – and explains why JESD204B is important, how it is used with high-speed A/D and D/A converters as well as providing trouble shooting tips and how-to articles. By Analog Devices, Inc.
by Analog Devices, Inc. - the World’s Data Converter Market Share Leader
Demystifying the JESD204B High-speed Data Converter-to-FPGA interfaceAnalog Devices, Inc.
Learn all about the JESD204 standard. This presentation provides an overview of the JESD204 serial interface standard from its origin up to the current "B" revision. Common "high-performance metrics" that are associated with high speed serial interfaces are also discussed. by Analog Devices, Inc.
In this Case Study read about Mistral’s expertise in designing a flexible and easily upgrade-able Video recording & processing solution with high resolution and frame rate for defense and aerospace applications.
Acquired analog signals can be manipulated and processed by either the analog or digital portions of a system, for example, through filtering, multiplexing, and gain control. The analog portions of a system can typically provide reasonably simple processing at fairly low cost, power, and overhead. Digital processing can provide far greater analysis power and can alter the nature of the analysis without changing hardware. Sampling theory, however, must be taken into account. This session covers the signal chain basics from signal to sensor to amplifier to converter to digital processor and back out again.
Webinar – Bluetooth Low Energy Power ControlEmbarcados
Bluetooth Low Energy Power Control também é conhecido como LE Power Control (LEPC) foi introduzido na especificação BLE 5.2. Esta funcionalidade permite que a sua aplicação controle o nível de potência do transmissor Bluetooth Low Energy automaticamente para obter o melhor link de rádio frequência com o menor consumo de energia.
Objetivo do Webinar
Aprenda como utilizar o BlueNRG-LP certificado BLE 5.2 e a função LE Power Control , otimize o consumo de energia da sua aplicação e faça sua bateria durar mais tempo.
Reusable Video IP Cores give software engineering service providers flexibility and less time to market while catering to the ever increasing demands of customers. Read on to know more about the Reusable IP Cores developed by NeST Software.
Multi Channel Multi Clock Frequency Speed Rate Real Time Industrial Standard ...theijes
The Aim is for HDL Design Architecture and Implementation of Multi clock frequency synchronized real time industrial standard parallel Hi-tech PRBS CDMA Transceiver Bus Array ASIC SOC /Card for Ultra high Speed real time Industrial Communication Interface Cards/Products like Data Acquisition and Tracking of wireless Data Communication Protocol Interface Cards/SOC’s like Data Serializer, De-serializer, Data Communication Protocol interface ADD on cards/Products, FPGA Cards of Different Data Transfer Baud rate. This Design Consists of multiple parallel C.D.M.A Transmitters and Receiver ASIC I.P Cores , Data Transmission and Reception done by Different Clock Frequencies operated at Mega/Giga / Tera/ Peta/Exa/Zetta/Yotta/Xona/Weka Clock Frequencies. Data Transmission Speed In terms Mega/Giga/Tera/Peta/Exa/Zetta/Yotta/Xona/Weka Bytes/Frames/Super Frames etc. and also Data transmitter and receiver consists of base band signal and Carrier signal generators, Channel Encoder, Decoder, Modulator and Demodulator generates modulation and Demodulation signal by spreading and dispreading through different communication frequency spread Spectrum techniques DSSS Communication, FH , Chaos for high Bandwidth , the design done through parallel distributed computing technique, data transmission and reception done parallel for various data interface cards of different data transfer speed. In this design transmission and reception done by different PRBS Data Pattern Sequences like 2e7 -1, 2e10 -1, 2e15 -1, 2e23 -1, 2e31 -1, 2e48 -1, 2e52 -1, 2e63 -1 etc. H.D.L FPGA Industrial Software Design Flow Process Implementation Done by either Xilinx/Altera. Programming Done by Verilog /VHDL Software and Simulation, Synthesis, ASIC Floor planning and Placement and routing, Reconfiguration and Debugging Done Xilinx ISE 9.2i/10.1i EDA Software and Xilinx /Altera FPGA Development Board/Kit.
Discuss how to navigate in the Military RF Multi Chip Module (MCM) arena using commercial technology.
Discuss how to develop a successful strategy to
support typical Military Product Life Cycles
in conflict with Moore’s Law.
Discuss the Future of Microelectronics Technology
SS-CPSIoT 2023_Kevin Mika and Piotr Zierhoffer presentationVEDLIoT Project
VEDLIoT – Accelerated AIoT. Kevin Mika and Piotr Zierhoffer. CPS&IoT’2023 Summer School on Cyber-Physical Systems and Internet-of-Things, Budva, Montenegro, June 2023
High Performance DSP with Xilinx All Programmable Devices (Design Conference ...Analog Devices, Inc.
This session includes a discussion on rapid prototyping concepts using Xilinx All Programmable FPGAs and SoCs with Analog Devices high speed and precision products. Covered in this session will be common use cases for Xilinx devices in DSP applications that interface to high speed analog. An overview will be provided of how Xilinx accelerates development with DSP platforms that can be used to quickly evaluate and prototype systems that include high speed analog, programmable logic, and embedded processing. Also covered will be an introduction to Xilinx’s new Vivado Design Suite development environment that shortens design cycles by providing an IP centric design flow, easy to use design analysis and debug, and high level design flows supporting C/C++ and MATLAB/Simulink.
The TMS320C6472 DSP is a six-core, fixed-point DSP from Texas instrument and two of these are integrated onto the Sundance EVP6472. Each DSP Core is a 700MHz DSP and can used for a many applications, requiring Embedded DSP Processing
For the full video of this presentation, please visit: https://www.edge-ai-vision.com/2022/07/accelerate-tomorrows-models-with-lattice-fpgas-a-presentation-from-lattice-semiconductor/
Hussein Osman, Segment Marketing Director at Lattice Semiconductor, presents the “Accelerate Tomorrow’s Models with Lattice FPGAs” tutorial at the May 2022 Embedded Vision Summit.
Deep learning models are advancing at a dizzying pace, creating difficult dilemmas for system developers. When you begin developing an edge AI system, you select the best available model for your needs. But by the time you’re ready to deploy your product, your original model is obsolete. You’d like to upgrade your model, but your neural network accelerator was designed with previous-generation models in mind and struggles to deliver top performance and efficiency on state-of-the-art models. The solution is hardware that adapts to the needs of whatever algorithms you choose.
Hardware programmability enables Lattice FPGAs to support the latest models and techniques with astounding efficiency, typically consuming less than 200 mW when running visual AI workloads at 30+ frames per second. In this talk, Osman shows how Lattice FPGAs, coupled with our production-proven sensAI solution stack, are being used to quickly develop super-efficient AI implementations that enable groundbreaking features in smart edge devices.
Extreme Manufacturing Solutions
Operations Performance Analytics (OPA)
Business alignment - Over time, the proliferation of devices has created unnecessary complexity. Control Center delivers centralized visibility and granular control of network resources. One click can equal a thousand actions when you manage your network. Control Center can even manage beyond Extreme Networks switching, routing, and wireless hardware to deliver standards-based control of other vendors’ network equipment.
Pairing assets with intelligent sensors to gather, analyze, and communicate data is driving enormous new efficiencies in manufacturing and business operations. Just as in the consumer markets, where the first generation of personal fitness monitors and smart home devices leverage data sets to influence and shape events in the physical world, so too are operational efficiencies borne by the Internet of Things (IoT) generating high returns in manufacturing.
According to McKinsey, “business-to-business applications will account for nearly 70 percent of the value … from IoT in the next ten years.” The firm estimates that of the nearly $11 trillion a year in economic value generated globally, ‘nearly $5 trillion [will] be generated almost exclusively in B2B settings, including factories… such as those in manufacturing, agriculture, and even healthcare environments; work sites across mining, oil and gas, and construction; and, finally, offices.’
More informed decision-making and optimized operations across the extended supply chain are only some of the benefits. Wireless sensors, whether measuring hydrogen levels in the soil or temperature variables on the production line, are eliminating blind spots in traditional manufacturing processes and delivering a constant flow of data that optimize workflows. And while manufacturers have leveraged data in discrete applications for Manufacturing Execution Systems (MES) and Enterprise Manufacturing Intelligence (EMI) systems for years, the growth of sensors, real-time dashboards, cloud-applications, and mobile technologies are delivering new degrees of actionable intelligence to the precise location at the precise time it can be optimally leveraged.
Yet this goal of seamlessly moving data across plant and business functions, and applying analytical tools to enable new insights, requires a new degree of visibility into the performance of manufacturing applications, networks, and systems. Traditionally monitoring tools used in factory environments are often isolated, closed, proprietary, and offer only a keyhole view of IT system performance.
LINKSTAR TECHNOLOGIES LIMITED, based in the USA, with Worldwide Distribution and Sales office in Hongkong is a synergy in Communications Technology, with Design, Development & EMS Facilities (Electronics & Telecommunications) in India. Linkstar provides solutions and value to Manufacturers and System Integrators. LINKSTAR has expertise and resources to design, develop & manufacture “Electronics & Communication” products from concept for System Integrators and OEMs.
Our areas of expertise range from Services in the “Design and Development” (Electronics and Telecommunication”), and EMS (Electronics Manufacturing Services) for OEMs.
We invite Regional Distributors & Channel Partners for our products and services.
Webinar: NVIDIA JETSON – A Inteligência Artificial na palma de sua mãoEmbarcados
Objetivo do Webinar: Venha saber como a plataforma NVIDIA Jetson e suas ferramentas habilitam você a desenvolver e implantar robôs, drones, aplicativos de IVA e outras máquinas autônomas com tecnologia AI que pensam por conta própria.
Apoio: Arrow e NVIDIA.
Convidado: Marcel Saraiva
Gerente de Contas Enterprise da NVIDIA, executivo com 20 anos de expereincia no mercado de TI, teve na sua carreia passagens pela SGI (Silicon Graphics), Intel e Scansource. Engenheiro eletrico formado pela FEI, com pós-graduação em Marketing pela FAAP e MBA em Gestão Empresarial pela FGV.
Link para o Webinar: https://www.embarcados.com.br/webinars/nvidia-jetson-a-inteligencia-artificial-na-palma-de-sua-mao/
UiPath Test Automation using UiPath Test Suite series, part 3DianaGray10
Welcome to UiPath Test Automation using UiPath Test Suite series part 3. In this session, we will cover desktop automation along with UI automation.
Topics covered:
UI automation Introduction,
UI automation Sample
Desktop automation flow
Pradeep Chinnala, Senior Consultant Automation Developer @WonderBotz and UiPath MVP
Deepak Rai, Automation Practice Lead, Boundaryless Group and UiPath MVP
Accelerate your Kubernetes clusters with Varnish CachingThijs Feryn
A presentation about the usage and availability of Varnish on Kubernetes. This talk explores the capabilities of Varnish caching and shows how to use the Varnish Helm chart to deploy it to Kubernetes.
This presentation was delivered at K8SUG Singapore. See https://feryn.eu/presentations/accelerate-your-kubernetes-clusters-with-varnish-caching-k8sug-singapore-28-2024 for more details.
Essentials of Automations: Optimizing FME Workflows with ParametersSafe Software
Are you looking to streamline your workflows and boost your projects’ efficiency? Do you find yourself searching for ways to add flexibility and control over your FME workflows? If so, you’re in the right place.
Join us for an insightful dive into the world of FME parameters, a critical element in optimizing workflow efficiency. This webinar marks the beginning of our three-part “Essentials of Automation” series. This first webinar is designed to equip you with the knowledge and skills to utilize parameters effectively: enhancing the flexibility, maintainability, and user control of your FME projects.
Here’s what you’ll gain:
- Essentials of FME Parameters: Understand the pivotal role of parameters, including Reader/Writer, Transformer, User, and FME Flow categories. Discover how they are the key to unlocking automation and optimization within your workflows.
- Practical Applications in FME Form: Delve into key user parameter types including choice, connections, and file URLs. Allow users to control how a workflow runs, making your workflows more reusable. Learn to import values and deliver the best user experience for your workflows while enhancing accuracy.
- Optimization Strategies in FME Flow: Explore the creation and strategic deployment of parameters in FME Flow, including the use of deployment and geometry parameters, to maximize workflow efficiency.
- Pro Tips for Success: Gain insights on parameterizing connections and leveraging new features like Conditional Visibility for clarity and simplicity.
We’ll wrap up with a glimpse into future webinars, followed by a Q&A session to address your specific questions surrounding this topic.
Don’t miss this opportunity to elevate your FME expertise and drive your projects to new heights of efficiency.
GDG Cloud Southlake #33: Boule & Rebala: Effective AppSec in SDLC using Deplo...James Anderson
Effective Application Security in Software Delivery lifecycle using Deployment Firewall and DBOM
The modern software delivery process (or the CI/CD process) includes many tools, distributed teams, open-source code, and cloud platforms. Constant focus on speed to release software to market, along with the traditional slow and manual security checks has caused gaps in continuous security as an important piece in the software supply chain. Today organizations feel more susceptible to external and internal cyber threats due to the vast attack surface in their applications supply chain and the lack of end-to-end governance and risk management.
The software team must secure its software delivery process to avoid vulnerability and security breaches. This needs to be achieved with existing tool chains and without extensive rework of the delivery processes. This talk will present strategies and techniques for providing visibility into the true risk of the existing vulnerabilities, preventing the introduction of security issues in the software, resolving vulnerabilities in production environments quickly, and capturing the deployment bill of materials (DBOM).
Speakers:
Bob Boule
Robert Boule is a technology enthusiast with PASSION for technology and making things work along with a knack for helping others understand how things work. He comes with around 20 years of solution engineering experience in application security, software continuous delivery, and SaaS platforms. He is known for his dynamic presentations in CI/CD and application security integrated in software delivery lifecycle.
Gopinath Rebala
Gopinath Rebala is the CTO of OpsMx, where he has overall responsibility for the machine learning and data processing architectures for Secure Software Delivery. Gopi also has a strong connection with our customers, leading design and architecture for strategic implementations. Gopi is a frequent speaker and well-known leader in continuous delivery and integrating security into software delivery.
Transcript: Selling digital books in 2024: Insights from industry leaders - T...BookNet Canada
The publishing industry has been selling digital audiobooks and ebooks for over a decade and has found its groove. What’s changed? What has stayed the same? Where do we go from here? Join a group of leading sales peers from across the industry for a conversation about the lessons learned since the popularization of digital books, best practices, digital book supply chain management, and more.
Link to video recording: https://bnctechforum.ca/sessions/selling-digital-books-in-2024-insights-from-industry-leaders/
Presented by BookNet Canada on May 28, 2024, with support from the Department of Canadian Heritage.
State of ICS and IoT Cyber Threat Landscape Report 2024 previewPrayukth K V
The IoT and OT threat landscape report has been prepared by the Threat Research Team at Sectrio using data from Sectrio, cyber threat intelligence farming facilities spread across over 85 cities around the world. In addition, Sectrio also runs AI-based advanced threat and payload engagement facilities that serve as sinks to attract and engage sophisticated threat actors, and newer malware including new variants and latent threats that are at an earlier stage of development.
The latest edition of the OT/ICS and IoT security Threat Landscape Report 2024 also covers:
State of global ICS asset and network exposure
Sectoral targets and attacks as well as the cost of ransom
Global APT activity, AI usage, actor and tactic profiles, and implications
Rise in volumes of AI-powered cyberattacks
Major cyber events in 2024
Malware and malicious payload trends
Cyberattack types and targets
Vulnerability exploit attempts on CVEs
Attacks on counties – USA
Expansion of bot farms – how, where, and why
In-depth analysis of the cyber threat landscape across North America, South America, Europe, APAC, and the Middle East
Why are attacks on smart factories rising?
Cyber risk predictions
Axis of attacks – Europe
Systemic attacks in the Middle East
Download the full report from here:
https://sectrio.com/resources/ot-threat-landscape-reports/sectrio-releases-ot-ics-and-iot-security-threat-landscape-report-2024/
"Impact of front-end architecture on development cost", Viktor TurskyiFwdays
I have heard many times that architecture is not important for the front-end. Also, many times I have seen how developers implement features on the front-end just following the standard rules for a framework and think that this is enough to successfully launch the project, and then the project fails. How to prevent this and what approach to choose? I have launched dozens of complex projects and during the talk we will analyze which approaches have worked for me and which have not.
1. EMS Solutions, Moving from Mind to Market
Contact: Arvind Kumar, Business Development Manager, arvind_kumar@pactroninc.com
2. EMS Solutions, Moving from Mind to Market
Profile
Pactron is a preeminent provider of engineering and
manufacturing services to the electronics industry. With
established expertise in the design and manufacture of
board level solutions, Pactron services a broad range
of industries including semiconductor, medical
devices, telecom, aerospace and defense. Pactron’s
integrated approach from design engineering through
manufacturing, all under one roof, yields dramatic
compression in time to market coupled with lowest total
cost of ownership for projects and programs to its
customers.
Pactron Confidential 2
3. EMS Solutions, Moving from Mind to Market
3
About Pactron
Established in 1988
Headquarters in Santa Clara, CA
Engineering, Design & Manufacturing in Santa Clara
Support centers in Texas, China
Design & Manufacturing Support Centers in India
Employee Headcount : ~300
Registered to ISO9001 & ISO13485
System Level Solutions: Engineering, Design & Manufacturing
Long standing customer base
Semiconductor : Intel, Marvell, Texas Instruments, Cypress, LSI….
OEM’s : Hughes, DRS, Smith & Nephew, Avantis, Asante, Zonare
Medical….
Pactron Confidential
4. EMS Solutions, Moving from Mind to Market
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Pactron’s End to End Service
Board Level
Design & Engineering
Simulation
Analysis
PCBA Test
•Schematic Engineering
•Board Layout
•High Speed Simulation
•Mechanical Design
•FPGA, Firmware Development
•Ansoft HFSS - 3D
Modeling
•Sigrity Power SI and
Power DC
•HSPICE
•SpectraQuest
•PowerPlane Analysis
•Material Management
•Complex PCB Mfg.
•High Density Assembly
•Integrated Rework
•Functional
•Boundary Scan
•Flying Probe
Pactron Confidential
Design & Engineering Manufacturing
5. EMS Solutions, Moving from Mind to Market
Pactron Sample Designs
System/Evaluation
Boards
5Pactron Confidential
6. EMS Solutions, Moving from Mind to Market
System Design Expertise
Schematic Engineering Based on a Block Diagram or requirements from customer
Experience with the following interfaces:
DDR3/2/1, NAND, QDRII/II+, SDRAM, DRAM,SRAM, FIFOs, Intel’s QPI, PCIe Gen2/3, SATA
2.0/3.0, USB2/3 host and device implementation, Gigabit Ethernet, PCI, DVI, Display Port, VGA,
HDMI, LCD Interfaces, SPI, I2C, eMMC, SD, MMC, and etc
Power Supply Design
Design a power distribution system based on the requirements
Switching and Linear Regulators
Battery Charging and Monitoring Circuit
FPGA expertise
Experience with different FPGA implementation like Altera, Xilinx, Lattice and Actel
Ability to account for clock management, power requirement and I/O level setting for various
interfaces
Firmware/FPGA program development
Windows and Linux operating system firmware development
Low Level Device Driver Development for UBoot and Linux Kernel
Porting of Uboot, Linux Kernel, and rootFS into an embedded ARM processor
Boundary Scan Implementation
Design for testability by implementing boundary scan chain
Test Development and Debug
Validate customer BSDL file
Board Design and Signal Integrity Analysis
Constrained driven manual routing
Simulation of high speed buses using IBIS/HSpice models and recommend termination and routing
topology. Perform 3D modeling for any 3D structures on the board (via, connector)
7. EMS Solutions, Moving from Mind to Market
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Enterprise Solid State Hard Drive
Marvell’s Flash Controller
2.5 inch Enterprise SSD
Power Hold-up circuitry using Tantalum Caps
Power Back-up circuitry using Super Caps
SATA Interface – 6 Gb/s
On-Board Discrete DDR3 Devices
Pactron Confidential
8. EMS Solutions, Moving from Mind to Market
PCI–Ex8 HBA
Pactron Confidential 8
• Hardware Architecture,
Schematic & Component
Engineering
• Power Supply/Distribution
Design
• Super Cap Back up
Design
• SI ,PI & Thermal Analysis
• MTBF
• E-DVT
• M-DVT
• Protocol Compliance :
PCI-E, SAS, SATA
• FCC, CE Compliance
• DFM, DFA
9. EMS Solutions, Moving from Mind to Market
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High Speed Transceivers 6.4 gbps
per pair
Altera Stratix IV GX FPGAs
CPLD to support PFL programming
3D Modeling using HFSS for high
speed channel
Hybrid Material – Rogers 4350 and
Nelco
28 layers with blind via technology
because of back to back BGAs
High Dense Placement with 0201
components
5% impedance tolerance on high
speed traces
High Speed I/O Board
9Pactron Confidential
10. EMS Solutions, Moving from Mind to Market
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XAUI 3.125 gbps per pair, PCIe, Gigabit Ethernet, DDR2 SODIMM
Broadcom Switch for XAUI Interface, Cavium and Power PC
Processor, PCIe Switch, Altera CPLD for system management
Boundary Scan Implementation for testability
High Voltage Translation
Line Card
10Pactron Confidential
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11
PCIe Form-Factor Video Protocol Board
PCIe Gen-2 x1 Form Factor
2 DVI Ports
2 Display Ports
2 HDMI Ports
Gigabit Ethernet
Video Out BNC
Discrete DDR3
Pactron Confidential
12. EMS Solutions, Moving from Mind to Market
Birchwood Development Kit
Pactron Confidential 12
The Birchwood System is a low power development/evaluation platform based on the high performance Marvell’s
Armada 300 88F6282 ARMv5TE compliant core with integrated 16 KB L1 Cache and 256 KB L2 cache that can run up
to 2.0 GHz. The system enables users to design and develop innovative embedded products based on the Marvell’s
88F6282 processor. The system has 512 MB (128 MB x 4) DDR3 RAM and 512 MB NAND Flash. The System can be
used by developers as is or Pactron can provide customized industrial designs, hardware and software for your
specific needs.
Features:
The system supports the following features:
•Linux-2.6.31.8 ARM Linux Kernel
•Ubuntu 9.04 Root File System
•16 bit DDR3 SDRAM running at 533 MHz clock rate
•8-bit 512 MB NAND flash boot support
•eSATA 3 Gbps data rate
•SATA 2.5” Hard Drive Interface 3 Gbps Data Rate
•4-bit SD Card Interface
•Two Gigabit Ethernet (10/100/1000 Mbps) ports
•Two PCIe x1 Interface (Standard and Mini-PCIe)
•Seven USB 2.0 Ports
•DVI Video Output
•2x16 Character LCD
•JTAG/UART0 Interface using Mini USB
•RS232/RS485 for UART1 and SMB Bus
Applications:
Single Board Computer
Proxy Server
Security
Point of Sale (PoS)
Industrial controller
Access Point
Routers
VPN
Storage
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Platform CustomizationPlatform Customization
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System Level design
The Ironwood is a low cost router based on Birchwood
.
07/10/13 Pactron Corporation 14
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VRM
Load (DUT) Top Side
Power Plane Noise Amplitude Plot
Noise @ 80MHz
Noise @ 310 MHz
Noise @ 420 MHz
Challenges
Layers - 32 layers
Thickness - 217 mil
Material – Rogers 4350 & FR4 (Hybrid)
SERDES 11Gbps
High Di/Dt and switching freq
Power Integrity Analysis
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Capacitors to be
optimized
Noise
Suppressing
Cap
Noise
Suppressing
Cap
Decoupling capacitor of BGA is
optimized for its location and
value to achieve target power
plane impedance.
Before Optimization
After Optimization
Decoupling Capacitor Optimization
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24 SERDES @ 10GHz
16 to SMA & 8 loopback
RO4350 & FR4
Return Loss > 10db @ 10 GHz
Challenges
Signal Integrity Analysis
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BGA Antipad Optimization in
inner layers for high speed
channels
SMA connector footprint optimization
TDR of the high speed channel
Simulation
Impedance discontinuity minimized at the
press fit connector side
DUT (BGA)
HighSpeedlanes@25GBps
HighSpeedlanes@25GBps
DUT (BGA footprint optimized)
Char Board to verify Interlaken Interface
DUT (BGA)
Serdes lanes to verify
10.3125Gbps operation
Airmax connector
footprint optimization to
minimize impedance
discontinuity
Contactor/Connector Footprint & Via Optimization
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Time Domain Analysis HSPICE by inputting the channel
s-parameter model and driver/reciever IBIS model.
Eye Diagram Analysis for High speed digital lines.
Time Domain & Eye Analysis
TDR of High speed traces
DDR DQ lane Voltage vs. Time plot with input PRBS pattern
To analyze reflection and ground bounce.
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Tools Used
•Ansoft HFSS
•Sigrity Power SI
•Synopsys HSPICE
•Cadence Sigxplorer
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Pactron Manufacturing
and Test Capability
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Capabilities
ISO 9001:2008 & ISO13485:2003
ESD controlled facility
4 fully automated SMT lines
• Rigid, Flex and Rigid Flex assemblies
• Board thickness ranging from 30 to 330 mils (52 layers max)
• Max board size 22 X 24”
• Fine pitch component down to 12 mils, 0201s
• BGA, uBGA re-ball and rework
Automated Optical Inspection & 3D X-Ray
Wave and Selective Wave solder
Aqueous and chemistry based closed loop wash systems
In house BGA/ CSP rework and re-ball capabilities
Cabelling / Box build and Mechanical Enclosures
Flying probe and function test capabilities
DFM/DFT
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Pactron - Manufacturing
Material verification & Control
• Measure and verify passive components before loading on the equipment
• Approved AVL, Alternates and part marking are available through MOS
Paperless factory
• Work instructions are provided in the form of visual aids, pictures etc.,
• Technicians have access to enter any feedback to a centralized system
Integrated Process control and tracking
In process Quality control
• AOI, In line QC, First article, QA
Test Management
All aspects of Process, Quality & Test are fully incorporated
using Aegis (Manufacturing Operations System)
IPC 610, J STD-001 certified
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Paperless Work Instructions
Board level
Traceability
Color coded
Visual aids
Work Instructions
Component
Information
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Defined Manufacturing Process
Each board on the shop floor
is identified using a unique Serial Number
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In-Process Quality
Boards are scanned at
each step of the
process
If defects occur they
are assigned to the
Serial number of the
board and the board is
tagged as failed
System doesn’t let the
boards continue until
the defect is fixed
27. EMS Solutions, Moving from Mind to Market
Test
Flying probe machines
• Locate Board Shorts
• Measure passive and active components like resistors, capacitors, relays,
diodes, etc on a loaded board
• For relay test the Coils are powered on and relay is tested for proper
switching continuity and functionality
• Current Leakage Measurements
• Increases test efficiency by testing thousands of nets in minutes
• With DFT able to obtain 80 % - 100 % coverage of boards.
Boundary Scan
• Assist in checking BGA to board continuity using JTAG scan connectivity
• Increase test coverage
Programming
• IC Programming of Eproms, FPGA programming like Xilinx/Altera
Functional Test Software/Hardware
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In Summary ~ Why Pactron?
• Ideal model for constantly evolving technology
•Broad Level of Engineering Support
•Integrated Engineering Expertise
•Flexible & Agile Manufacturing Strategy
• Integrated Design & Manufacturing
• Low volume Prototyping
• Medium to High Volume Support
•Strategic global presence
• US – Sunnyvale, Dallas
• Asia – India, China
•One Stop Shop for a Engineering & Manufacturing PCBA Project Requirement
Pactron Confidential
A Turn-Key Solutions Provider
High End Designs – Manufacturing - Final Test