A Hetero-Spacer-Dielectric Double-Gate Junctionless Transistor for Enhanced Analog Performance

Int. Journal of Electrical & Electronics Engg. Vol. 2, Spl. Issue 1 (2015) e-ISSN: 1694-2310 | p-ISSN: 1694-2426
NITTTR, Chandigarh EDIT -2015 66
A Hetero-Spacer-Dielectric Double-Gate
Junctionless Transistor for Enhanced
Analog Performance
Swati Choudhary1
, and Gaurav Saini1, 2
1
School of VLSI Design & Embedded Systems, NIT Kurukshetra, Haryana, India
2
Department of ECE, NIT Kurukshetra, Haryana, India
Abstract—In this paper, we propose a hetero-spacer-
dielectric (HSP) double-gate junctionless transistor (DGJLT)
with high-k spacer towards source side and low-k spacer
towards drain side to enhance analog performance at high
drain voltages. The characteristics are revealed through
extensive device simulations and compared with other
DGJLTs, formed by taking all possible combinations of low-k
and high-k spacer dielectrics on both sides of gate. The
proposed HSP DGJLT gives superior values of drain current
(ID), transconductance (Gm), early voltage (VEA) and intrinsic
gain (GmRo) compared to other DGJLTs at high drain
voltages. Simulations reveal an improvement of early voltage
and intrinsic gain by 45.95% and 14.83% respectively
compared to conventional DGJLT having low-k spacer
dielectric on both sides of gate. However, unity gain cut-off
frequency (fT) of HSP DGJLT decreases by 23.49% due to its
high gate capacitance.
Keywords—Double-gate junctionless transistor (DGJLT), high-k
spacer, low-k spacer, spacer (SP) dielectric.
I. INTRODUCTION
HE conventional bulk MOSFETs impose many serious
challenges, such as increased gate leakage and added short
channel effects (SCEs) because of ongoing device scaling.
Several alternatives have been proposed to address these
issues. Multi-gate FET is one of them. It has better scaling
capabilities as multiple gates provide superior control on
the channel region. But requirements of ultra-sharp doping
profile at source/drain (S/D) junction puts another
challenge in front of device manufactures. New doping
techniques and advancements in S/D engineering are
required to create such high doping concentration
gradients. This ultimately leads to increased cost of device
fabrication. Newly proposed junctionless transistor (JLT)
relaxes the constraints associated with doping profile. It
does not require a p-n junction in source-channel-drain
path. JLT works on the principle of depletion-mode device.
It offers many advantages over conventional bulk
MOSFETs such as: 1) Better scalability, 2) Reduced SCEs,
3) Simple fabrication process flow, and 4) Low thermal
budgets after gate formation [1]-[4]. Despite of many
advantages, JLTs experience lower drain current and
transconductance compared to conventional inversion-
mode MOSFETs due to high doping in channel region [1],
[5].
Although JLTs ease the technological requirements of
scaling but they are not totally free from SCEs when
physical gate length of the device reduces to sub-20 nm.
Suresh Gundapaneni et al. [6] reported that for better
electrostatic integrity of such short channel devices, high-k
dielectric spacer can be used. In ON-state, spacer
electrically induces the extension region of underlapped
device and reduces the parasitic resistance. This improves
ON-state current. In OFF-state, spacer increases the
fringing electric field and depletes the device far away
from gate edges. This reduces OFF-state leakage current.
R. K. Baruah et al. [7] reported that ON-state current is
marginally affected with the use of spacer while OFF-state
current is reduced by orders of tens. Hence, ION/IOFF ratio
improves. To explore and boost the effect of spacer
dielectric material on the performance of DGJLT,
simulations are carried out.
This paper introduces a novel double-gate junctionless
transistor (DGJLT) with high-k spacer towards source side
and low-k spacer towards drain side. The effect of
placement of spacer material having different dielectric
constants on the device characteristics has been studied. A
comparison is done among four DGJLTs by considering
different combinations of low-k and high-k spacer
dielectrics: 1) DGJLT with low-k spacer on both sides of
gate (JL-LK), 2) DGJLT with high-k spacer on both sides
of gate (JL-HK), 3) DGJLT with low-k spacer towards
source side and high-k spacer towards drain side (JL-
LHK), and 4) DGJLT with high-k spacer towards source
side and low-k spacer towards drain side (JL-HLK).
Simulation results indicate that the proposed structure can
significantly improve the device performance compared to
other structures at sub-20 nm gate lengths. This paper is
constructed in the following manner. In Section II, all
device structures, their characteristics and simulation
methodology are explained. In Section III, simulation
results and their analysis are presented. At last, conclusions
are drawn in Section IV.
II. DEVICE STRUCTURE AND SIMULATION
A 2-D schematic view of the proposed n-channel hetero-
spacer-dielectric DGJLT is shown in Fig. 1. Uniform and
homogeneous doping of Arsenic (N+
) is done throughout
T

67 NITTTR, Chandigarh EDIT-2015
the device. Raised source/drain structure is used to reduce
contact resistance [8]. Metal is taken as the gate material.
The devices are modified by tuning the work function of
metal (WM) such that all the devices have equal threshold
voltage of 0.3 V. Threshold voltage (Vth) is defined using
constant current method. It is specified as the gate voltage
corresponding to the drain current of 10-7
A/µm at a drain
voltage of 50 mV. The work function values of metal gate
for JL-LK, JL-HK, JL-LHK and JL-HLK are 5.25 eV, 5.15
eV, 5.18 eV and 5.18 eV respectively. Hafnium oxide,
HfO2 (dielectric constant = 22) and Silicon nitride, Si3N4
(dielectric constant = 7.5) are taken as spacer dielectric
materials and Silicon dioxide, SiO2 (dielectric constant =
3.9) is taken as gate-dielectric material. HfO2 and Si3N4 are
referred as high-k and low-k dielectrics respectively. Other
process and device parameters are listed in Table I.
Source
Gate Drain
LSD LSP Gate LSP LSD
Fig. 1. 2-D Schematic view of an n-channel hetero-spacer-
dielectric DGJLT.
TABLE I
DEVICE/ SIMULATION PARAMETERS
Parameter Value
Gate length (LG) 20 nm
Channel thickness (TSi) 10 nm
Source/Drain length (LSD) 50 nm
Doping concentration (ND) 1 × 1019
cm-3
Gate oxide thickness (TOX) 1.7 nm
Spacer length (LSP) 30 nm
Supply voltage (VDD) 1 V
Devices simulations are performed using 2-D TCAD
Sentaurus device simulator [9]. For all simulations,
Quantum model is used which includes two carriers,
doping concentration dependent mobility model and
electric field dependent mobility model. Doping and
temperature dependent Shockley-Read-Hall recombination
model has been included for considering leakage currents.
III. SIMULATION RESULTS
Fig. 2 shows the distribution of electrostatic potential
and electric field along the channel direction at drain
voltage (VDS) = 1 V and gate voltage (VGS) = 1 V.
Electrostatic potential of JL-HLK increases rapidly
compared to other structures which enhances its electric
field. JL-HLK has comparatively higher electric field peak
near source end due to high-k spacer towards source side,
and electron velocity in the channel is controlled by this
peak [10]. Variation of electron velocity along the channel
direction is shown in Fig. 3 and it is observed that
electrons accelerate rapidly in the case of JL-HLK. This
improves carrier transport efficiency which results in high
drain current as shown in Fig. 6. On the other hand, lower
electric field peak near drain end, suppresses SCEs such as
drain-induced barrier lowering (DIBL) and hot carrier
effects.
Fig. 4 shows the variation of drain current with respect
to gate voltage at VDS = 50 mV. High-k spacer enhances
fringing electric field more effectively compared to low-k
spacer [10] and due to this; OFF-state leakage current
reduces. JL-HK gives minimum leakage current followed
by JL-HLK, JL-LHK and JL-LK. In ON-state, ideally JLT
has zero electric field [11], so ON-state current is less
affected with spacer dielectric value. For VGS > 0.5 V, JL-
HLK has highest drain current but near VGS = 1 V, JL-HK
has slightly higher value of drain current due to high-k
spacer on both sides of gate.
Fig. 2. Electrostatic potential and electric field distributions
along the channel direction at VDS = 1 V and VGS = 1 V.
Fig. 3. Electron velocity distribution along the channel direction
at VDS = 1 V and VGS = 1 V.
N
+
N
+
TSi
HK-SP LK-SP
N+
LG
HK-SP LK-SP

Fig. 4. Drain current of JL-LK, JL-HK, JL-LHK and JL-HLK
with respect to gate voltage at VDS = 50 mV.
Fig. 5 shows transconductance and transconductance to
drain current ratio (commonly known as transconductance
generation factor) plotted against gate voltage. These two
parameters are referred as transistor’s figure of merit
(FOM) and their value decides how well a device performs
as a transistor. Transconductance (Gm) indicates how
effectively a device converts voltage into current. It is
given by [12]-
= (1)
Fig. 5. (a) Transconductance with respect to gate voltage at VDS
= 1 V.
Fig. 6. Drain current with respect to drain voltage at VGS = 1 V.
Fig. 8. Early voltage with respect to drain voltage at VGS = 1 V.
For VGS < Vth, all the devices have almost equal (~ zero)
transconductance due to very small value of drain current
in OFF-state. For 0.3 < VGS < 0.6 V, JL-LHK has highest
transconductance because of more DIBL. For VGS > 0.6 V,
JL-HLK has highest transconductance followed by JL-HK,
JL-LHK and JL-LK due to its high drain current. The Gm
values for JL-LK, JL-HK, JL-LHK and JL-HLK are 0.99,
1.09, 1 and 1.11 mS/µm respectively at VGS = 1 V and VDS
= 1V.
Fig. 5. (b) Transconductance to drain current ratio with respect to
gate voltage at VDS = 1 V.

69 NITTTR, Chandigarh EDIT-2015
Fig. 7. Output conductance with respect to drain voltage at VGS =
1 V.
Fig. 9. Intrinsic gain with respect to gate voltage at VDS = 1 V.
Another FOM, Gm/ID is a measure of transistor’s
efficiency to convert DC power into AC frequency. At low
VGS, JL-HK gives highest value of Gm/ID which means
lowest value of subthreshold current. For VGS > 0.3 V, JL-
HLK has highest Gm/ID value but near VGS = 1 V, all the
devices have almost equal Gm/ID value because of their
analogous Gm and ID values. Fig. 6 shows output
characteristics of all the devices. JL-HLK carries highest
output current [10]. Fig. 7 shows output conductance (GD)
plotted against drain voltage. Below drain voltage of 0.5 V,
JL-HLK gives highest output conductance due to highest
drain current. At high VDS, JL-HLK has lowest output
conductance due to its minimum DIBL. At low drain bias,
channel length modulation (CLM) and at high drain bias,
DIBL governs the behavior of output conductance [6]. GD
decreases with drain voltage due to saturation of output
current at high drain bias.
Fig. 8 shows plot of early voltage with respect to drain
voltage. JL-HLK has highest value of early voltage in ON-
state due to reduced SCEs. The early voltage values for JL-
LK, JL-HK, JL-LHK and JL-HLK are 9.1, 9.6, 7.6 and
13.3 V respectively. Similar to GD, at low drain bias, CLM
and at high drain bias, DIBL governs early voltage [6]. The
intrinsic gain of the devices is plotted in Fig. 9 with respect
to gate voltage. The intrinsic gain (AV) of a device is
defined as [12]-
= =
,
(2)
JL-HLK offers highest intrinsic gain compared to other
structures because of its high transconductance and high
early voltage. The intrinsic gain values for JL-LK, JL-HK,
JL-LHK and JL-HLK are 49.7, 50.4, 48.6 and 52.9 dB at
VGS = 0.2 V and 26.4, 27.5, 24.8 and 30.3 dB at VGS = 1 V
respectively.
Fig. 10. Gate capacitance and unity-gain cut-off frequency with
respect to gate voltage at VDS = 1 V.
Total gate capacitance (= + ) for all the
devices is shown in Fig. 10 at VDS = 1 V. Here, CGS and
CGD indicate gate-to-source and gate-to-drain capacitances.
A small-signal AC analysis at a frequency of 1 MHz has
been performed to extract all capacitances. JL-HK has
highest gate capacitance due to higher fringing field of
high-k spacer. At low VGS, JL-LHK and JL-HLK have
nearly equal gate capacitances while at high VGS, JL-HLK
has slightly higher gate capacitance than JL-LHK due to its
high CGS value. JL-LK has minimum gate capacitance due
to low fringing field of low-k spacer. For analog
applications, unity gain cut-off frequency is also an
important FOM. It is given by [12]-
= ( )
(3)
For VGS < 0.25 V, all the devices have almost equal
due to similar values of transconductance. But at high VGS,
is greatly influenced by gate capacitance. JL-LK has
highest unity gain cut-off frequency due to lowest gate
capacitance. The values for JL-LK, JL-HK, JL-LHK
and JL-HLK are 205, 132, 160 and 166 GHz respectively.
Low-k spacers improve but at the cost of high
subthreshold slope (SS).
IV. CONCLUSION
Hetero-spacer-dielectric is incorporated in a DGJLT to
form HSP DGJLT. The device characteristics are studied
and compared for enhanced analog performance. A sincere
comparison with other devices was performed by making
threshold voltage same for all the devices. HSP DGJLT
gives higher values of transconductance, Gm/ID factor, early
voltage and intrinsic gain at high drain voltages. Proposed
structure also reduces SCEs and gives minimum value of
DIBL. However, JL-HLK has inferior compared to JL-
LK. can be improved by using low-k spacer but at the
cost of increased SS. Thus a compromise is made between
and SS.

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A Hetero-Spacer-Dielectric Double-Gate Junctionless Transistor for Enhanced Analog Performance

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A Hetero-Spacer-Dielectric Double-Gate Junctionless Transistor for Enhanced Analog Performance