This document summarizes a study investigating a low leakage junctionless vertical pillar transistor (VPT) for sub-30nm DRAM technologies. Device simulations were conducted on a junctionless VPT with a partially recessed drain design. Results showed this design significantly reduced gate induced drain leakage (GIDL) compared to a normal junctionless VPT or inversion-mode VPT by lowering the peak electric field. Dynamic retention characteristics were also improved by suppressing parasitic bipolar junction transistor current during bit line bias variations. GIDL was reduced to below 10-16 A compared to 10-12-10-13 A for normal designs.