1) The document describes the design and analysis of a junctionless transistor using TCAD simulation tools. A MIGFET-based junctionless transistor structure with two independent gates is modeled.
2) ID-VG characteristics are obtained by varying one gate voltage while keeping the other fixed. The mixer output of the MIGFET junctionless transistor is also analyzed and found to have higher but distorted amplitude compared to a conventional MIGFET.
3) In conclusion, the MIGFET junctionless transistor structure is not suitable for mixer applications due to distortion in the output, though it has higher amplitude. The junctionless transistor design and simulation is performed using Sentaurus TCAD tools.
Analysis of analog and RF behaviors in junctionless double gate vertical MOSFETjournalBEEI
The prime obstacle in continuing the transistor’s scaling is to maintain ultra-shallow source/drain (S/D) junctions with high doping concentration gradient, which definitely demands an advanced and complicated S/D and channel engineering. Junctionless transistor configuration has been found to be an alternative device structure in which the junction and doping gradients could be totally eliminated, thus simplifying the fabrication process. In this paper, a process simulation has been performed to study the impact of junctionless configuration on the analog and RF behaviors of double-gate vertical MOSFET. The result proves that the performance of n-channel junctionless double-gate vertical MOSFET (n-JLDGVM) is slightly better than the junction double-gate vertical MOSFET (n-JDGVM). Junctionless device exhibits better analog behaviors as the transconductance (gm) is increased by approximately 4%. In term of RF behaviors, the junctionless device exhibits 3.4% and 7% higher cut-off frequency (fT) and gain band-width product (GBW) respectively over the junction device.
Analysis of analog and RF behaviors in junctionless double gate vertical MOSFETjournalBEEI
The prime obstacle in continuing the transistor’s scaling is to maintain ultra-shallow source/drain (S/D) junctions with high doping concentration gradient, which definitely demands an advanced and complicated S/D and channel engineering. Junctionless transistor configuration has been found to be an alternative device structure in which the junction and doping gradients could be totally eliminated, thus simplifying the fabrication process. In this paper, a process simulation has been performed to study the impact of junctionless configuration on the analog and RF behaviors of double-gate vertical MOSFET. The result proves that the performance of n-channel junctionless double-gate vertical MOSFET (n-JLDGVM) is slightly better than the junction double-gate vertical MOSFET (n-JDGVM). Junctionless device exhibits better analog behaviors as the transconductance (gm) is increased by approximately 4%. In term of RF behaviors, the junctionless device exhibits 3.4% and 7% higher cut-off frequency (fT) and gain band-width product (GBW) respectively over the junction device.
A Hetero-Spacer-Dielectric Double-Gate Junctionless Transistor for Enhanced ...IJEEE
In this paper, we propose a hetero-spacer- dielectric (HSP) double-gate junctionless transistor (DGJLT) with high-k spacer towards source side and low-k spacer towards drain side to enhance analog performance at high drain voltages. The characteristics are revealed through extensive device simulations and compared with other DGJLTs, formed by taking all possible combinations of low-k and high-k spacer dielectrics on both sides of gate. The proposed HSP DGJLT gives superior values of drain current (ID), transconductance (Gm), early voltage (VEA) and intrinsic gain (GmRo) compared to other DGJLTs at high drain voltages. Simulations reveal an improvement of early voltage and intrinsic gain by 45.95% and 14.83% respectively compared to conventional DGJLT having low-k spacer dielectric on both sides of gate. However, unity gain cut-off frequency (fT) of HSP DGJLT decreases by 23.49% due to its high gate capacitance.
Leakage Power Reduction Techniques Revisited in a CMOS Inverter Circuit at De...idescitation
As CMOS Technology is aiming at miniaturization
of MOS devices, a trend of increase in the static power
consumption is being observed. The main sources of static
power consumption are sub-threshold current and gate oxide
leakage current. In this work, we discuss the major sources of
power consumption, various techniques to reduce leakage
power and their trade-offs in a CMOS inverter logic circuit at
90nm. Three most popular leakage current reduction
techniques are studied with respect to a conventional inverter
circuit. It is seen that the main trade-off is between the area
and the static leakage current. This paper aims to reduce the
static power dissipation with a small compromise in area.
Microelectronic technology
This report briefly discusses the need for Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs), their structure and principle of operation. Then it details the fabrication and characterization of the MOSFETs fabricated at the microelectronic lab at University of Malaya
shows the simulation and analysis of a MOSFET device using the MOSFet tool. Several powerful analytic features of this tool are demonstrated, including the following:
calculation of Id-Vg curves
potential contour plots along the device at equilibrium and at the final applied bias
electron density contour plots along the device at equilibrium and at the final applied bias
spatial doping profile along the device
1D spatial potential profile along the device
Design of Low Power, High PSRR Error Amplifier for Low Drop-Out CMOS Voltage...IJEEE
This paper presents design of an improved Error amplifier (EA) for Low Drop-Out Voltage Regulator. The proposed circuit shows good behaviour as compared to the previous Error Amplifier. The Gain, Unity Gain Bandwidth, Phase Margin, CMRR and PSRR of an Error Amplifier is analysed. The proposed circuit is designed on UMC 180nm CMOS technology with supply voltage of 1.8Volts. All the simulation results are calculated through SPECTRE Simulator of cadence.
NOVEL SLEEP TRANSISTOR TECHNIQUES FOR LOW LEAKAGE POWER PERIPHERAL CIRCUITSVLSICS Design
Static power consumption is a major concern in nanometre technologies. Along with technology scaling down and higher operating speeds of CMOS VLSI circuits, the leakage power is getting enhanced. As process geometries are becoming smaller, device density increases and threshold voltage as well as oxide thickness decrease to keep pace with performance. Two novel circuit techniques for leakage current reduction in inverters with and without state retention property are presented in this work. The power dissipation during inactive (standby) mode of operation can be significantly reduced compared to traditional power gating methods by these circuit techniques. The proposed circuit techniques are applied to inverters and the results are compared with earlier inverter leakage minimization techniques. Inverter
buffer chains are designed using new state retention low leakage technique and found to be dissipating lower power with state retention. All low leakage inverters are designed and simulated in cadence design environment using 90 nm technology files. The leakage power during sleep mode is found to be better by X 63 times for novel method. The total power dissipation has also reduced by a factor of X 3.5, compared to earlier sleepy keeper technique. The state retention feature is also good compared to earlier leakage power reduction methodologies.
Sub-Threshold Leakage Current Reduction Techniques In VLSI Circuits -A SurveyIJERA Editor
There is an increasing demand for portable devices powered up by battery, this led the manufacturers of
semiconductor technology to scale down the feature size which results in reduction in threshold voltage and
enables the complex functionality on a single chip. By scaling down the feature size the dynamic power
dissipation has no effect but the static power dissipation has become equal or more than that of Dynamic power
dissipation. So in recent CMOS technologies static power dissipation i.e. power dissipation due to leakage
current has become a challenging area for VLSI chip designers. In order to prolong the battery life and maintain
reliability of circuit, leakage current reduction is the primary goal. A basic overview of techniques used for
reduction of sub-threshold leakages is discussed in this paper. Based on the surveyed techniques, one would be
able to choose required and apt leakage reduction technique.
Analytical modeling of electric field distribution in dual material junctionl...VLSICS Design
In this paper, electric field distribution of the junctionless dual material surrounding gate MOSFETs
(JLDMSG) is developed. Junctionless is a device that has similar characteristics like junction based
devices, but junctionless has a positive flatband voltage with zero electric field. In Surrounding gate
MOSFETs gate material surrounds the channel in all direction , therefore it can overcome the short
channel effects effectively than other devices. In this paper, surface potential and electric field distribution
is modelled. The proposed surface potential model is compared with the existing central potential model. It
is observed that the short channel effects (SCE) is reduced and the performance is better than the existing
method.
A Hetero-Spacer-Dielectric Double-Gate Junctionless Transistor for Enhanced ...IJEEE
In this paper, we propose a hetero-spacer- dielectric (HSP) double-gate junctionless transistor (DGJLT) with high-k spacer towards source side and low-k spacer towards drain side to enhance analog performance at high drain voltages. The characteristics are revealed through extensive device simulations and compared with other DGJLTs, formed by taking all possible combinations of low-k and high-k spacer dielectrics on both sides of gate. The proposed HSP DGJLT gives superior values of drain current (ID), transconductance (Gm), early voltage (VEA) and intrinsic gain (GmRo) compared to other DGJLTs at high drain voltages. Simulations reveal an improvement of early voltage and intrinsic gain by 45.95% and 14.83% respectively compared to conventional DGJLT having low-k spacer dielectric on both sides of gate. However, unity gain cut-off frequency (fT) of HSP DGJLT decreases by 23.49% due to its high gate capacitance.
Leakage Power Reduction Techniques Revisited in a CMOS Inverter Circuit at De...idescitation
As CMOS Technology is aiming at miniaturization
of MOS devices, a trend of increase in the static power
consumption is being observed. The main sources of static
power consumption are sub-threshold current and gate oxide
leakage current. In this work, we discuss the major sources of
power consumption, various techniques to reduce leakage
power and their trade-offs in a CMOS inverter logic circuit at
90nm. Three most popular leakage current reduction
techniques are studied with respect to a conventional inverter
circuit. It is seen that the main trade-off is between the area
and the static leakage current. This paper aims to reduce the
static power dissipation with a small compromise in area.
Microelectronic technology
This report briefly discusses the need for Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs), their structure and principle of operation. Then it details the fabrication and characterization of the MOSFETs fabricated at the microelectronic lab at University of Malaya
shows the simulation and analysis of a MOSFET device using the MOSFet tool. Several powerful analytic features of this tool are demonstrated, including the following:
calculation of Id-Vg curves
potential contour plots along the device at equilibrium and at the final applied bias
electron density contour plots along the device at equilibrium and at the final applied bias
spatial doping profile along the device
1D spatial potential profile along the device
Design of Low Power, High PSRR Error Amplifier for Low Drop-Out CMOS Voltage...IJEEE
This paper presents design of an improved Error amplifier (EA) for Low Drop-Out Voltage Regulator. The proposed circuit shows good behaviour as compared to the previous Error Amplifier. The Gain, Unity Gain Bandwidth, Phase Margin, CMRR and PSRR of an Error Amplifier is analysed. The proposed circuit is designed on UMC 180nm CMOS technology with supply voltage of 1.8Volts. All the simulation results are calculated through SPECTRE Simulator of cadence.
NOVEL SLEEP TRANSISTOR TECHNIQUES FOR LOW LEAKAGE POWER PERIPHERAL CIRCUITSVLSICS Design
Static power consumption is a major concern in nanometre technologies. Along with technology scaling down and higher operating speeds of CMOS VLSI circuits, the leakage power is getting enhanced. As process geometries are becoming smaller, device density increases and threshold voltage as well as oxide thickness decrease to keep pace with performance. Two novel circuit techniques for leakage current reduction in inverters with and without state retention property are presented in this work. The power dissipation during inactive (standby) mode of operation can be significantly reduced compared to traditional power gating methods by these circuit techniques. The proposed circuit techniques are applied to inverters and the results are compared with earlier inverter leakage minimization techniques. Inverter
buffer chains are designed using new state retention low leakage technique and found to be dissipating lower power with state retention. All low leakage inverters are designed and simulated in cadence design environment using 90 nm technology files. The leakage power during sleep mode is found to be better by X 63 times for novel method. The total power dissipation has also reduced by a factor of X 3.5, compared to earlier sleepy keeper technique. The state retention feature is also good compared to earlier leakage power reduction methodologies.
Sub-Threshold Leakage Current Reduction Techniques In VLSI Circuits -A SurveyIJERA Editor
There is an increasing demand for portable devices powered up by battery, this led the manufacturers of
semiconductor technology to scale down the feature size which results in reduction in threshold voltage and
enables the complex functionality on a single chip. By scaling down the feature size the dynamic power
dissipation has no effect but the static power dissipation has become equal or more than that of Dynamic power
dissipation. So in recent CMOS technologies static power dissipation i.e. power dissipation due to leakage
current has become a challenging area for VLSI chip designers. In order to prolong the battery life and maintain
reliability of circuit, leakage current reduction is the primary goal. A basic overview of techniques used for
reduction of sub-threshold leakages is discussed in this paper. Based on the surveyed techniques, one would be
able to choose required and apt leakage reduction technique.
Analytical modeling of electric field distribution in dual material junctionl...VLSICS Design
In this paper, electric field distribution of the junctionless dual material surrounding gate MOSFETs
(JLDMSG) is developed. Junctionless is a device that has similar characteristics like junction based
devices, but junctionless has a positive flatband voltage with zero electric field. In Surrounding gate
MOSFETs gate material surrounds the channel in all direction , therefore it can overcome the short
channel effects effectively than other devices. In this paper, surface potential and electric field distribution
is modelled. The proposed surface potential model is compared with the existing central potential model. It
is observed that the short channel effects (SCE) is reduced and the performance is better than the existing
method.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
REVIEW PAPER ON NEW TECHNOLOGY BASED NANOSCALE TRANSISTORmsejjournal
Owing to the fact that MOSFETs can be effortlessly assimilated into ICs, they have become the heart of the
growing semiconductor industry. The need to procure low power dissipation, high operating speed and
small size requires the scaling down of these devices. This fully serves the Moore’s Law. But scaling down
comes with its own drawbacks which can be substantiated as the Short Channel Effect. The working of the
device deteriorates owing to SCE. In this paper, the problems of device downsizing as well as how the use
of SED based devices prove to be a better solution to device downsizing has been presented. As such the
study of Short Channel effects as well as the issues associated with a nanoMOSFET is provided. The study
of the properties of several Quantum dot materials and how to choose the best material depending on the
observation of clear Coulomb blockade is done. Specifically, a study of a graphene single electron
transistor is reviewed. Also a theoretical explanation to a model designed to tune the movement of
electrons with the help of a quantum wire has been presented.
REVIEW PAPER ON NEW TECHNOLOGY BASED NANOSCALE TRANSISTORmsejjournal
Owing to the fact that MOSFETs can be effortlessly assimilated into ICs, they have become the heart of the
growing semiconductor industry. The need to procure low power dissipation, high operating speed and
small size requires the scaling down of these devices. This fully serves the Moore’s Law. But scaling down
comes with its own drawbacks which can be substantiated as the Short Channel Effect. The working of the
device deteriorates owing to SCE. In this paper, the problems of device downsizing as well as how the use
of SED based devices prove to be a better solution to device downsizing has been presented. As such the
study of Short Channel effects as well as the issues associated with a nanoMOSFET is provided. The study
of the properties of several Quantum dot materials and how to choose the best material depending on the
observation of clear Coulomb blockade is done. Specifically, a study of a graphene single electron
transistor is reviewed. Also a theoretical explanation to a model designed to tune the movement of
electrons with the help of a quantum wire has been presented.
Performance Evaluation of GaN Based Thin Film Transistor using TCAD Simulation IJECEIAES
As reported in past decades, gallium nitride as one of the most capable compound semiconductor, GaN-based high-electron mobility transistors are the focus of intense research activities in the area of high power, high-speed, and high-temperature transistors. In this paper we present a design and simulation of the GaN based thin film transistor using sentaurus TCAD for the extracting the electrical performance. The resulting GaN TFTs exhibits good electrical performance in the simulated results, including, a threshold voltage of 12-15 V, an on/off current ratio of 6.5×10 7 ~ 8.3×10 , and a subthreshold slope of 0.44V/dec. Sentaurus TCAD simulations is the tool which offers study of comprehensive behavior of semiconductor structures with ease. The simulation results of the TFT structure based on gallium nitride active channel have great prospective in the next-generation flat-panel display applications.
Performance Evaluation of GaN Based Thin Film Transistor using TCAD Simulation Yayah Zakaria
As reported in past decades, gallium nitride as one of the most capable compound semiconductor, GaN-based high-electron mobility transistors are the focus of intense research activities in the area of high power, high-speed, and high-temperature transistors. In this paper we present a design and simulation of the GaN based thin film transistor using sentaurus TCAD for
the extracting the electrical performance. The resulting GaN TFTs exhibits good electrical performance in the simulated results, including, a threshold voltage of 12-15 V, an on/off current ratio of 6.5×10 7 ~ 8.3×10 and a subthreshold slope
of 0.44V/dec. Sentaurus TCAD simulations is the tool which
offers study of comprehensive behavior of semiconductor structures with ease. The simulation results of the TFT structure based on gallium nitride active channel have great prospective in the next-generation flat-panel display applications.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
NOVEL SLEEP TRANSISTOR TECHNIQUES FOR LOW LEAKAGE POWER PERIPHERAL CIRCUITSVLSICS Design
Static power consumption is a major concern in nanometre technologies. Along with technology scaling down and higher operating speeds of CMOS VLSI circuits, the leakage power is getting enhanced. As process geometries are becoming smaller, device density increases and threshold voltage as well as oxide thickness decrease to keep pace with performance. Two novel circuit techniques for leakage current reduction in inverters with and without state retention property are presented in this work. The power dissipation during inactive (standby) mode of operation can be significantly reduced compared to traditional power gating methods by these circuit techniques. The proposed circuit techniques are applied to inverters and the results are compared with earlier inverter leakage minimization techniques. Inverter
buffer chains are designed using new state retention low leakage technique and found to be dissipating lower power with state retention. All low leakage inverters are designed and simulated in cadence design environment using 90 nm technology files. The leakage power during sleep mode is found to be better by X 63 times for novel method. The total power dissipation has also reduced by a factor of X 3.5, compared to earlier sleepy keeper technique. The state retention feature is also good compared to earlier leakage power reduction methodologies.
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The use of nanometer CMOS technologies (below 90nm) however brings along significant challenges for circuit design (both analog and digital). By reducing the dimensions of transistors many physical phenomenon like gate leakage, drain induced barrier lowering and many more effects comes into picture. Reducing the feature size in the technology of device with the addition of ever more interconnect layers, the density of the digital as well as analog circuit will increase while intrinsic gate switching delay is reduced . We have simulated conventional and DMG MOSFET at 30nm scale using Silvaco TAD tool and obtained result. A two dimensional device simulation was carried out and observed that DMG MOSFET has a low leakage current as compared to conventional MOSFET and find suitable application in analog circuits.
Recovery method to mitigate the effect of NBTI on SRAM cellsIJERA Editor
NBTI stands for Negative Bias Temperature Instability. NBTI basically affects the parameter at the device level
and hence affects the performance of the device. This paper explains what NBTI is and its effect on the SRAM
cells while also dealing with the leakage current that is supposed to be one of the important factors affecting any
circuit. Not just that but this paper also puts forth a method called recovery mode which explains a different
approach to overcome this effect of NBTI on the 6T SRAM cell.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
THRESHOLD VOLTAGE CONTROL SCHEMES IN FINFETSVLSICS Design
Conventionally polysilicon is used in MOSFETs for gate material. Doping of polysilicon and thus changing the workfunction is carried out to change the threshold voltage. Additionally polysilicon is not favourable as gate material for smaller dimensional devices because of its high thermal budget process and degradation due to the depletion of the doped polysilicon, thus metal gate is preferred over polysilicon. Control of workfunction in metal gate is a challenging task. The use of metal alloys as gate materials for variable gate workfunction has been already reported in literature. In this work various threshold voltage techniques has been analyzed and a novel aligned dual metal gate technique is proposed for threshold voltage control in FinFETs.
Similar to RBL paper _Design_of_MIGFET_based_junctionless_transistor (20)
RBL paper _Design_of_MIGFET_based_junctionless_transistor
1. Design of MIGFET Based Junctionless Transistor
1
Hema.N
SENSE Department, VIT University
Tamil Nadu, India
1
hema.n2013@vit.ac.in
Abstract— This paper describes about a novel device called
junctionless transistor. The properties of junctionless transistor
is analysed using TCAD tool. ID-VG characteristics of junctonless
transistor is obtained and analysed. ID-VG characteristics of
MIGFET based junctionless transistor is finally analysed with
various curves by fixing one of the gate voltage and varying
voltage in other gate. Mixer output is taken from mixer in
MIGFET based junctionless transistor. Designing of MIGFET
based junctionless transistor is done using TCAD tool.
Keywords— Junction-less, MIGFET, TCAD
I. INTRODUCTION
The semiconductor world is now focusing on to the scaling
down of transistor sizes. But mainly designers know how
difficult it is to fabricate a transistor with such a low
nanometre scale, since its having different doping levels
which form source and drain junctions. So they have to be
very specific and accurate while designing which makes the
whole fabrication process very complex. [1] Here comes the
role of the novel device called Junctionless transistors that too
with multiple independent gates. The multigate device
employing independent gate electrodes at times is called
as Multiple Independent Gate Field Effect
Transistor (MIGFET).
Junctionless transistor is a heavily doped silicon nanowire
with independent gate electrodes. The semiconductor layer
must be thin and narrow enough to allow for full depletion of
carriers when the device is turned off and the semiconductor
layer needs to be heavily doped to allow for a reasonable
amount of current flow when the device is turned on. [2] N-
channel accumulation –mode devices have N+ -N –N+ doping
for the source, channel and drain region, respectively. Similar
is the case for P-channel devices. In junction transistor, the
major carriers in channel region make itself a barrier to carrier
scattering. But, here junctionless transistor does not have this
problem. With every technology node scaling is getting
challenging.[3]
The advantages of juntionless transistor includes lack of
abrupt junctions that can be hardly controlled at the nanometer
scale and has simpler fabrication process. It has a channel
region which is highly doped and of same carrier type as that
of source and drain regions and is turned off by body
depletion using a suitable gate work function.[4]
At nanometre sizes it is very hard to control the sharp
source/drain-channel junctions from the device fabrication
point of view. The use of channel with corners leads to
another effect called corner effect. In inversion mode devices
lightly doped channel is used to avoid this.
Moore’s law tells the number of transistors on integrated
circuits doubles approximately every two years. The period is
often quoted as eighteen months. Gordon E. Moore, the Intel
co-founder, after whom this law is named, described the trend
in his 1965 paper. [5] He predicted that this trend would
continue for atleast ten years. But for doubling the number of
transistors,we have to reduce the size of the transistors.
A. Scaling
The device performance has been steadily improved by
scaling to smaller physical dimensions. When we scale down
the power supply by increasing channel doping, then that will
cause the width of the depletion region to scale with the
device dimensions. Oxide thickness and depletion widths are
decreased by the same factor. [6] So all the electric fields
within the device remain constant. It is difficult to design the
board level design for chips to operate at different voltages.
Also scaling the power supply hurts the performance. So the
chip foundries avoid the power supply scaling as long as
possible. In inversion mode transistors, as we move the source
and drain physically together, it becomes more and more
difficult to electrically isolate them. Thus the problem of
scaling arises. They are short channel effects and Drain
Induced Barrier Lowering (DIBL). To a great extend this
problems are resolved while we use junctionless transistors.
[2]
B. Short Channel Effects
Short-channel effects are predicted to be less important in
junctionless devices. In inversion mode transistor, as channel
length is reduced, the device threshold becomes dependent on L
and VDS. This deviations from the ideal threshold model in L is
called as short channel effect and that in VDS is called as DIBL.
In an inversion mode transistor, with physical gate length L
physical the effective gate length is Leff when the device is on,
and the effective gate length is LSCE when the device is off.
Now, LSCE < Leff, which means that the effective channel length
when the device is off is shorter than when it is on. In the
junctionless transistor, we know that the doping concentration is
constant across the device. [7] The electrostatic squeezing of the
channel in the off device propagates into the source and drain and
as a result, Leff > Lphysical when the device is off. When the device
is on, the squeezing effect is removed, and then it becomes Leff
= Lphysical. As a result, Leff is larger on the off state than in the on
state, which improves the short-channel effects. But it is worth
noting that the longer effective gate length of junctionless device
is not the reason for it’s better short channel characteristics.
2. C. DIBL
Drain Induced Barrier Lowering (DIBL) is a short channel
effect which causes the reduction of threshold voltage of the
transistor at higher drain voltages. This reduction of threshold
voltage is taking place as a consequence of charge neutrality.
The combined charge in the depletion region of the device and
that in the channel of the device is balanced by three electrode
charges. [8] They are the gate, the source and the drain. As
drain voltage is increased, the depletion region of the pn-
junction between the drain and the substrate increases in size
and it extends under the gate. So the drain assumes a greater
portion of the burden of balancing depletion region charge,
leaving a smaller burden for the gate. As a result, the charge
on the gate retains charge balance by attracting more carriers
into the channel, which causes the reduction of threshold
voltage. Thus the potential energy barrier for electrons in the
channel is lowered. Thus it’s called as Drain Induced Barrier
Lowering.
D. Working
The simple fabrification of junctionless transistor is due to
the elimination of junction implantation and annealing. So this
simple process results in a reduced cost. Since here for
junctionless transistor, the channel is having N-type doping,
The simple fabrification of junctionless transistor is due to the
elimination of junction implantation and annealing.[3] So this
simple process results in a reduced cost. Since here for
junctionless transistor, the channel is having N-type doping,
an N-channel junctionless device requires a gate material with
a high work function, so as to achieve a suitable threshold
voltage value. Thus use of a metal as a gate material is
preferable for gate resistance reduction purposes.Working
Entire Si nanowire is heavily n-doped excellent conductor.
Gate is P-doped. It deplete the number of electrons in the
region of nanowire under the gate. Voltage is applied across
the nanowire. Current will get squeezed at depletion region
below the gate. This squeezing effect is reduced when we
apply voltage to gate and then the current starts flowing.[9]
Energy which is necessary to extract an electron from the
valance band of the metal is called the work function, m.
Similarly the work function in semiconductor is denoted as
sc.. To make the electrons leave from the semiconductor the
work function of gate is made higher than the work function
of semiconductor. Thus in N-type, m > sc and in P-type, m
< sc.
II. TCAD SIMULATOR
TCAD simulator refers to the performance of all the
simulations. The modeling of the fabrication is termed
Process TCAD, while the modeling of the device operation is
termed Device TCAD. [10] Modules of TCAD used here are
the following.
Sentaurus structure editor (SDE) : To create 2D and 3D
device structures, to import structures from a prior process
simulation step and to generate mesh structures.
Sentaurus device simulator (SDEVICE) : To perform all
DC, AC simulations.
Sentaurus visual & inspect : To view the structures and
results generated from the process and device simulations.
[11]
The TableI below shows the dimension of junctionless
transistor.[1]
TABLE I
PARAMETERS OF JUNCTIONLESS TRANSISTOR
Process/device parameters Junctionless transistor
Channel doping 8×1019
/cm3
Gate oxide thickness 1nm
Gate work function 5.5eV
Wfin 10nm
Lg 30nm
Structure of junctionless transistor is viewed using TCAD
tool. This is illustrated in Fig1.
Fig. 1 SDE structure of Junctionless transistor in TCAD
Upper and lower parts show the source, channel and drain
of junctionless transistor. The portion between the source and
drain forms the channel .Interfaces are given fine meshing to
get more accurate characteristics. Either parts of channel has
silicon dioxide and over that gate metal. Channel length is
taken as 30nm with a gate of work function 5.5eV.
The use of junctionless does not direct source-to-drain
tunnelling in very short channel devices. The use of additional
source and drain doping concentration structure improves the
current drive significantly in junctionless devices. This is done
because in accumulation mode devices a reduction of channel
doping concentration is required to achieve suitable threshold
and sub threshold values when the fin width is increased. So
that source and drain resistance increases which reduces the
current drive. This is corrected by classical spacer formation
and by an additional source and drain implantation.
The fin width of junctionless devices must be small
enough for the channel region to be completely depleted of
carriers when a gate voltage is applied to turn the device off.
The actual minimum fin size value of junctionless devices is
dependentant of the channel doping concentration. In
accumulation mode the influence of fin width variation on
threshold voltage is larger.
3. In MIGFET, the thin silicon channel is controlled by
multiple gate electrodes, that are separated from each other.
For designing MIGFET based junctionless transistor, two
gates with independent voltages are applied to the junctionless
transistor.
Fig. 2 SDE structure of junctionless transistor with independent gate
voltages in TCAD
Here one of the gate voltage is kept fixed and other
varies.Fig.1 represents the schematic view of junction less
transistor with independent gates. This independently controls
the channel region of the transistor.
Mixer mixes two input signals, here sine and square, such
that the output frequency is either the sum frequency or
difference frequency of inputs. Signal should not get clipped
from the channel while mixing, because that may lead to the
loss of information.
III. RESULTS AND DISCUSSION
Fig.3 shows the simulated ID-VG characteristic of junctionless
device.
Fig. 3 ID-VG plot
The Ion and Ioff values are calculated from curve data and
are obtained as,
Ion = 982µA
Ioff = 4.22nA
Ion/Ioff = 232.70 × 103
In MIGFET based junctionless transistor, as in Fig.2 two
gates with independent voltages are given. In this, one of the
gate is kept fixed and other gate is varied from -1V to
1V.Then following graph Fig . 4 is obtained. Here from top to
bottom curve varies from -1V to 1V.
Fig. 4 ID-VG graph of MIGFET based junctionless transistor (log scale)
Fig. 5 ID-VG graph of MIGFET based junctionless transistor (linear
scale)
From this graph threshold voltages(Vth),
transconductances(gm) and subthreshold slopes(ss) were
calculated and compared. Subthreshold slope was calculated
by using the formula.