Tunnel Field-Effect Transistor
Next-generation Transistors
Presented by
Tsu-Wen Sung
OUTLINE
Introduction
ComparisonSimulation
INTRODUCTION
P+ N+
Intrinsic
Dielectric
Gate
Source
Bulk
Drain
Similar Structure
Switching Mechanism Differs
(From Wiki)
SIMULATION
Direct Bandgap III-V
Kane-Sze Model
a, b : Material-dependent parameter
f : Determines the onset of current
E : Maximum electric field across the tunnel
Vtw : tunneling potential across the tunnel window
Kane-Sze
Model
NDR
Ambipolor
Esaki
Diode
VGS
VDS
Choose
InAs Homojunction TFET
Gate
Intrinsic InAs Channel
P+ InAs
Source
N+ InAs
Drain
TCh
LG
TOX
High-Performance
NMOS
InAs Homojunction
TFET
W = 1 um ; L = 20nm W = 1 um ; L = 20nm
Si InAs
Unified Model Kane-Sze Model
High-Performance
NMOS
InAs Homojunction
TFET
COMPARISON
Combine
High-Performance
NMOS
InAs Homojunction
TFET
On/Off ratio: 105 ~ 1019
Power: 3*10-3 W
Subthreshold Swing: 60mV/dec
On/Off ratio: 103 ~ 104
Power: 3*10-4 W
Subthreshold Swing: 50mV/dec
Q&A

Tunnel field effect transistor