This document discusses latchup and electrostatic discharge (ESD) in CMOS integrated circuits. It begins by defining latchup as the creation of a low impedance path between power supply rails, which is caused by triggering parasitic bipolar transistors within the circuit. It then discusses how latchup occurs via the regenerative process in a parasitic pnpn structure, and how it can be triggered by current or voltage. The document provides guidelines for preventing latchup through techniques like guard rings and layout optimizations. It also defines ESD as the discharge of static electricity and discusses how it can damage integrated circuits if the built-up charge is not properly dissipated.

1. Lecture 080 – Latchup and ESD (3/24/10) Page 080-1
LECTURE 080 – LATCHUP AND ESD
LECTURE ORGANIZATION
Outline
• Latchup
• ESD
• Summary
CMOS Analog Circuit Design, 2nd Edition Reference
Pages 48-52 and new material
CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 080 – Latchup and ESD (3/24/10) Page 080-2
LATCHUP
What is Latchup?
• Latchup is the creation of a low impedance path
between the power supply rails.
• Latchup is caused by the triggering of parasitic
bipolar structures within an integrated circuit
when applying a current or voltage stimulus on
an input, output, or I/O pin or by an over-voltage
on the power supply pin.
• Temporary versus true latchup:
070221-01
Excessive Current
VDD
A temporary or transient latchup occurs only while the pulse stimulus is connected
to the integrated circuit and returns to normal levels once the stimulus is removed.
A true latchup remains after the stimulus has been removed and requires a power
supply shut down to remove the low impedance path between the power supply rails
CMOS Analog Circuit Design © P.E. Allen - 2010

2. Lecture 080 – Latchup and ESD (3/24/10) Page 080-3
Latchup Testing
The test for latchup defines how the designer must think about latchup.
• For latchup prevention, you must consider where a current limited (100mA), 10ms
pulse is going to go when applied to a pad when the voltage compliance of the pad is
constrained to 50% above maximum power supply and to 2V below ground. (Higher
temperatures, 85C°and 125°C, are more demanding, since VBE is lower.)
050727-06
VDD
100mA
10ms
• Latchup is sensitive to layout and is most often solved at the physical layout level.
CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 080 – Latchup and ESD (3/24/10) Page 080-4
How Does Latchup Occur?
Latchup is the regenerative process that can occur in a pnpn structure (SCR-silicon
controlled rectifier) formed by a parasitic npn and a parasitic pnp transistor.
Anode
p
n
p
n
Cathode
Anode
vPNPN
Cathode
To avoid latchup
vPNPN VS
Triggering by
increasing V
DD
vPNPN
iPNPN 1/Slope =
Limiting
Resistance
V
DD
Hold Current, IH
Avalanche
Breakdown
Sustaining
voltage, VS
050414-01
Hold
Voltage, VH
iPNPN
Body diode
(CMOS)
Important concepts:
• To avoid latchup, vPNPN VS
• Once the pnpn structure has latched up, the large current required by the above i-v
characteristics must be provided externally to sustain latchup
• To remove latchup, the current must be reduced below the holding current
CMOS Analog Circuit Design © P.E. Allen - 2010

3. Lecture 080 – Latchup and ESD (3/24/10) Page 080-5
Latchup Triggering
Latchup of the SCR can be triggered by two different mechanisms.
1.) Allowing vPNPN to exceed the sustaining voltage, VS.
2.) Injection of current by a triggering device (gate triggered)
Injector
Anode
SCR
npn
Gate
050414-03
Pad VDD
SCR
Cathode
pnp
Gate
Gate
Current
Injector
Gate
Current
Pad
Note: The gates mentioned above are SCR junction gates, not MOSFET gates.
From the above considerations, latchup requires the following components:
1.) A four-layer structure (SCR) connected between VDD and ground.
2.) An injector.
3.) A stimulus.
CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 080 – Latchup and ESD (3/24/10) Page 080-6
Necessary Conditions for Latchup
1.) The loop gain of the relevant BJT configuration must exceed unity.
+fb
loop VDD ii βn βp io
050414-04
Loop gain:
io
ii
pn
2.) A bias condition must exist such that both bipolars are turned on long enough for
current through the “SCR” to exceed its switching current.
3.) The bias supply and associated circuits must be capable of supplying the current at
least equal to the switching current and at least equal to the holding current to maintain
the latched state.
CMOS Analog Circuit Design © P.E. Allen - 2010

4. Lecture 080 – Latchup and ESD (3/24/10) Page 080-7
Latchup Trigger Modes
Current mode (Positive Injection Example):
When a current is applied to a pad, it can flow through
an injector and trigger latchup of an SCR formed from
parasitic bipolar transistors.
SCR gate current injection parasitic can occur in p-well
or n-well technology.
Voltage mode:
When the power supply is increased
above the nominal value, the SCR formed from
parasitic bipolar transistors can be triggered.
Pad
VDD
Gate
Current
Injector
050414-05 SCR
SCR
VAnode
VDD VAnode Vabs,max
050414-06
VDD
CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 080 – Latchup and ESD (3/24/10) Page 080-8
How does Latchup Occur in an IC?
Consider an output driver in CMOS technology:
v vOUT IN VDD
n-
p+ p p- n n+ Oxide Poly 1 Poly 2 Nitride Salicide Metal 050416-02
VDD
vOUT
vIN
Assume that the output is connected to a pad.
CMOS Analog Circuit Design © P.E. Allen - 2010

5. Lecture 080 – Latchup and ESD (3/24/10) Page 080-9
Parasitic Bipolar Transistors for the n-well CMOS Inverter
vOUT vIN VDD
Rw1 Rw2
Rw3
R s1
LT1
VT2 VT1 n-
LT2
Rs2 Rw4
Rs3 Rs4
p+ p p- n n+ Oxide Poly 1 Poly 2 Nitride Salicide Metal 050416-03
Parasitic components:
Lateral BJTs LT1 and LT2
Vertical BJTs VT1 and VT2
Bulk substrate resistances Rs1, Rs2, Rs3, and Rs4
Bulk well resistances Rw1, Rw2, Rw3, and Rw4
CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 080 – Latchup and ESD (3/24/10) Page 080-10
Current Source Injection
Apply a voltage compliant current source to the output pad (vOUT VDD).
Voltage Compliant
Current Source
v vOUT IN VDD
Rs LT1
VT2 VT1 Rw
n-
LT2
p+ p p- n n+ Oxide Poly 1 Poly 2 Nitride Salicide Metal 050416-04
Loop gain:
iout
iin
= P1
Rw
Rw+rP1 N1
Rs
Rs+rN1
= P1N1
P1Vt
IP1
Rw
Rw+
Rs
Rs+
N1Vt
IP2
CMOS Analog Circuit Design © P.E. Allen - 2010

6. Lecture 080 – Latchup and ESD (3/24/10) Page 080-11
Current Sink Injection
Apply a voltage compliant current sink to the output pad (vOUT 0).
Voltage Compliant
v vOUT IN VDD
Rw3
Current Sink
Rs LT1
VT2 VT1 Rw
n-
LT2
p+ p p- n n+ Oxide Poly 1 Poly 2 Nitride Salicide Metal 050416-07
Loop gain:
iout
iin
= P1
Rw
Rw+rP1 N1
Rs
Rs+rN1
= P1N1
P1Vt
IP1
Rw
Rw+
Rs
Rs+
N1Vt
IP2
CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 080 – Latchup and ESD (3/24/10) Page 080-12
Latchup from a Transmission Gate
The classical push-pull output stage is only one of the many configurations that can lead
to latchup. Here is another configuration:
Transmission
VDD
VDD
Gate
Pad
Internal
Core
Circuits
Clk
Driver
Internal Core
Circuitry
Pad
VClk DD
Injectors Receiver
Transmission Gate Clock Driver
050416-09 p+ p p- n n n+ Oxide Poly 1 Poly 2 Nitride Salicide Metal -
The two bold solid bipolar transistors in the transmission gate act as injectors to the npn-pnp
parasitic bipolars of the clock driver and cause these transistors to latchup. The
injector sites are the diffusions connected to the pad.
CMOS Analog Circuit Design © P.E. Allen - 2010

7. Lecture 080 – Latchup and ESD (3/24/10) Page 080-13
The Influence of Shallow Trench Isolation on Latchup
As seen below, the STI causes the parasitic betas to be smaller.
Protective Insulator Layer
VDD OUTPUT
GRD
Metal Vias Metal Via
Tungsten Plugs
Sidewall
Spacers Polycide
Salicide Salicide Salicide
p+ p+ n+ n+
n+ p+
Shallow
Trench
Isolation
n-well p-well
Tungsten
Plug
Shallow
Trench
Isolation
Substrate
GRD
p+
Tungsten
Plugs
Tungsten
Plugs
Shallow
Trench
Isolation
Oxide p+ p p- n- n n+ Salicide Metal
Poly
Top
Metal
Second
Level
Metal
First
Level
Metal
Inter-mediate
Oxide
Layers
060406-01
Polycide
Salicide
Gate Ox
CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 080 – Latchup and ESD (3/24/10) Page 080-14
Preventing Latch-Up
1.) Keep the source/drain of the MOS device not in the well as far away from the well as
possible. This will lower the value of the BJT betas.
2.) Reduce the values of RN- and RP-. This requires more current before latch-up can
occur.
3.) Surround the transistors with guard rings. Guard rings reduce transistor betas and
divert collector current from the base of SCR transistors.
n-channel transistor
FOX FOX FOX FOX FOX FOX
Figure 190-10
p+ guard bars
p-well
p-channel transistor
n+ guard bars
VDD VSS
n- substrate
FOX
CMOS Analog Circuit Design © P.E. Allen - 2010

8. Lecture 080 – Latchup and ESD (3/24/10) Page 080-15
What are Guard Rings?
Guard rings are used to collect carriers flowing in the silicon. They can be designed to
collect either majority or minority carriers.
Guard rings in n-material: Guard rings in p-material:
n+ guard ring
Collects
minority
carriers
p+ guard ring
Collects majority
carriers VDD
Decreased bulk
resistance
p+ p p- n n n+ 051201-01 -
VDD
p+ guard ring
Collects
minority
carriers
n+ guard ring
Collects
majority
carriers
Decreased bulk
resistance
p p- n- n n+ 051201-02
p+
Also, the increased doping level of the n+ (p+)guard ring in n (p) material decreases the
resistance in the area of the guard ring.
CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 080 – Latchup and ESD (3/24/10) Page 080-16
Example of Reducing the Sensitivity to Latchup
Start with an inverter with no attempt to minimize latchup and minimum spacing between
the NMOS and PMOS transistors.
vIN
vOUT
VDD
Note minimum separation
n-
Rs
Rw
p+ p p- n n+ Oxide Poly 1 Poly 2 Nitride Salicide Metal 050427-03
CMOS Analog Circuit Design © P.E. Allen - 2010

9. Lecture 080 – Latchup and ESD (3/24/10) Page 080-17
Example of Reducing the Sensitivity to Latchup by using Guard Rings
Next, place guard rings around the NMOS and PMOS transistors (both I/O and logic) to
collect most of the parasitic NPN and PNP currents locally and prevent turn-on of
adjacent devices.
vIN
p+ guard vOUT
VDD
ring
Note increased separation
n-
Rs
Rw
n+ guard
ring
p+ p p- n n+ Oxide Poly 1 Poly 2 Nitride Salicide Metal 050427-04
VDD
• The guard rings also help to reduce the effective well and substrate resistance.
• The guard rings reduce the lateral beta
Key: The guard rings should act like collectors
CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 080 – Latchup and ESD (3/24/10) Page 080-18
Example of Reducing the Sensitivity to Latchup by using Butted Contacts
Finally, use butted source contacts to further reduce the well resistance and reduce the
substrate resistance.
vIN
p+ guard vOUT
VDD
ring
VDD
n-
Rs
n+ guard
ring
Rw
p+ p p- n n+ Oxide Poly 1 Poly 2 Nitride Salicide Metal 050427-05
CMOS Analog Circuit Design © P.E. Allen - 2010

10. Lecture 080 – Latchup and ESD (3/24/10) Page 080-19
Guidelines for Guard Rings
• Guard rings should be low resistance paths.
• Guard rings should utilize continuous diffusion areas.
• More than one transistor of the same type can be placed inside the same well inside the
same guard ring as long as the design rules for spacing are followed.
• Only 2 guard rings are required between adjacent PMOS and NMOS transistors
• The well taps and/or the guard ring should be laid out as close to the MOSFET source
as possible.
• I/O output NMOSFET should use butted composite for source to bulk connections
when the source is electrically connected to the p-well tap. If separate well tap and
source connections are required due to substrate noise injection problems, minimize the
source-well tap spacing. This will minimize latch up and early snapback of the output
MOSFETs with the drain diffusion tied directly (in metal) to the bond pad.
CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 080 – Latchup and ESD (3/24/10) Page 080-20
ESD IN CMOS TECHNOLOGY
What is Electrostatic Discharge?
Triboelectric charging happens when 2 materials come in contact and then are separated.
An ESD event occurs when the stored charge is discharged.
CMOS Analog Circuit Design © P.E. Allen - 2010

11. Lecture 080 – Latchup and ESD (3/24/10) Page 080-21
ESD and Integrated Circuits
• ICs consist of components that are very sensitive to excess current and voltage above
the nominal power supply.
• Any path to the outside world is susceptible to ESD
• ESD damage can occur at any point in the IC assembly and packaging, the packaged
part handling or the system assembly process.
• Note that power is normally not on during an ESD event
050727-01
CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 080 – Latchup and ESD (3/24/10) Page 080-22
ESD Models and Standards
• Standard tests give an indication of the ICs robustness to withstand ESD stress.
• Increased robustness:
- Reduces field failures due to ESD
- Demanded by customers
• Simple ESD model:
- VSE = Charging Voltage
- Key parameters of the model:
VSE
t=0 RLim
+ i(t)
− C
IC
o Maximum current flow
o Time constant or how fast the ESD event
discharges
Current
o Risetime of the pulse
Imax
Time constant (τ)
≈ RLimC
0 t
070210-01
Risetime
0
CMOS Analog Circuit Design © P.E. Allen - 2010

12. Lecture 080 – Latchup and ESD (3/24/10) Page 080-23
ESD Models
• Human body model (HBM): Representative of an ESD
event between a human and an electronic component.
• Machine model (MM): Simulates the ESD event when a
charged “machine” discharges through a component.
050423-02
040929-03
• Charge device model (CDM): Simulates the
ESD event when the component is charged
and then discharges through a pin. The
substrate of the chip becomes charged and
discharges through a pin.
CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 080 – Latchup and ESD (3/24/10) Page 080-24
ESD Influence on Components
An ESD event typically creates very high values of current (1-10A) for very short periods
of time (150 ns) with very rapid rise times (1ns).
Therefore, components experience extremely high values of current with very little power
dissipation or thermal effects.
Resistors – become nonlinear at high currents and will breakdown
Capacitors – become shorts and can breakdown from overvoltage (pad to substrate)
Diodes – current no longer flows uniformly (the connections to the diodes represent the
ohmic resistance limit)
Transistors – ESD event is only a two terminal event, the third terminal is influenced by
parasitics and many of the transistor parameters are poorly controlled.
• MOSFETs – the parasitic bipolar experiences snapback under an ESD event
• BJTs – will experience snapback under ESD event
CMOS Analog Circuit Design © P.E. Allen - 2010

13. Lecture 080 – Latchup and ESD (3/24/10) Page 080-25
Objective of ESD Protection
• There must be a safe low impedance path between every combination of pins to sink the
ESD current (i.e. 1.5A for 2kV HBM)
• The ESD device should clamp the voltage below the breakdown voltage of the internal
circuitry
• The metal busses must be designed to survive 1.5A (fast transient) without building up
excessive voltage drop
• ESD current must be steered away from sensitive
circuits
• ESD protection will require area on the chip (busses
and timing components)
VDD
Limiting
Resistor
Sensitive
Circuits
VSS
ESD
Power
Rail
Clamp
041008-01
CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 080 – Latchup and ESD (3/24/10) Page 080-26
ESD Protection Architecture
Internal
Circuits
Input
Pad
Rail based protection
Output
Pad
Local
Clamp
Local
Clamp
Local
Clamp
Local
Clamp
VDD
VSS
ESD
Power
Rail
Clamp
040929-06
Local clamp based protection
Local clamps – Conducts ESD current without loading the internal (core) circuits
ESD power rail clamps – Conducts a large amount of current with a small voltage drop
ESD Events:
Pad-to-rail (uses local clamps only)
Pad-to-pad (uses either local or local and ESD power rail clamps)
CMOS Analog Circuit Design © P.E. Allen - 2010

14. Lecture 080 – Latchup and ESD (3/24/10) Page 080-27
Example of an ESD Breakdown Clamp
A normal MOSFET that uses the parasitic lateral BJT to achieve a snapback clamp.
Normally, the MOSFET has the gate shorted to the source so that drain current is zero.
S G
D
B
i - + DS
vDS
n+ n+
iDS
Shallow
Trench
Isolation
Shallow
Trench
Isolation
p-substrate
Rsub
iC
B
Device destruction
Second Breakdown
Snapback Region
First Breakdown
Avalanche
Region
vDS
Negative TC
Positive TC
Linear Region
Saturation Region
Vt2 Vt1
041217-04
p+
iSub
Issues:
• If the drain voltage becomes too large, the gate oxide may breakdown
• If the transistor has multiple fingers, the layout should ensure that the current is
distributed evenly.
CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 080 – Latchup and ESD (3/24/10) Page 080-28
Example of a Non-Breakdown Clamp
NMOS Clamp:
R
C
VDD
Speed-up
Capacitor
NMOS
Clamp
Trigger
Circuit
Inverter
Driver
Operation:
VSS
041001-03
• Normally, the input to the driver is
high, the output low and the NMOS clamp off
• For a positive ESD event, the voltage increases across R causing the inverter to turn on
the NMOS clamp providing a low impedance path between the rails
• Cannot be used for pads that go above power supply or are active when powered up
• For power supply turn-on, the circuit should not trigger (C holds the clamp off during
turn-on)
Also, forward biased diodes serve as non-breakdown clamps.
CMOS Analog Circuit Design © P.E. Allen - 2010

15. Lecture 080 – Latchup and ESD (3/24/10) Page 080-29
IV Characteristics of Good ESD Protection
Goal: Sink the ESD current and clamp the voltage.
ESD Clamp
Protected
Device
Voltage
Case 2 - Protected Device Fails
ESD Clamp
Protected
Device
Voltage
Case 4 - Protected Device Fails
070221-02
Current
ITarget
Current
ITarget
ESD Clamp
Case 1 - Okay
Current
ITarget
Protected
Device
Voltage
ESD Clamp
Case 3 - Okay
Current
ITarget
Protected
Device
Voltage
ESD
Clamp
Protected
Device
CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 080 – Latchup and ESD (3/24/10) Page 080-30
Comparison Between the NMOS Clamp and the Snapback Clamp
Increasing the width of theNMOS clamp will reduce the clamp voltage.
Increasing
snapback W
Vc Vc Vc
Voltage
Target
Iesd
Current
Max operating voltage
Holding
voltage
Trigger
voltage
Increasing
NMOS W
NMOS Vt
Note that the NMOS clamp does not normally exceed the absolute maximum voltage.
NMOS clamps should be used with EPROMs to avoid reprogramming during an ESD
event.
CMOS Analog Circuit Design © P.E. Allen - 2010

16. Lecture 080 – Latchup and ESD (3/24/10) Page 080-31
ESD Practice
General Guidelines:
• Understand the current flow requirements for an ESD event
• Make sure the current flows where desired and is uniformly distributed
• Series resistance is used to limit the current in the protected devices
• Minimize the resistance in protecting devices
• Use distributed (smaller) active clamps to minimize the effect of bus resistance
• Understand the influence of packaging on ESD
• Use guard rings to prevent latchup
Check list:
• Check the ESD path between every pair of pads
• Check for ESD protection between the pad and internal circuitry
• Check for low bus resistance
- Current: Minimum metal for ESD 40 x Electromigration limit
- Voltage: 1.5A in a metal bus of 0.03/square of 1000μm long and 30μm wide gives
a voltage drop of 1.5V
• Check for sufficient contacts and vias in the ESD path (uniform current distribution)
CMOS Analog Circuit Design © P.E. Allen - 2010
Lecture 080 – Latchup and ESD (3/24/10) Page 080-32
SUMMARY
• Latchup is the creation of a low impedance path between the power supply rails
resulting in excessive current.
• The conditions for latchup are:
- A four-layer, pnpn structure connected between power supply rails
- An injector (any diffusion connected to a pad)
- A stimulus
• Latchup is prevented by:
- Keeping the NMOS and PMOS transistors separated
- Reducing the well resistance with appropriate well ties
- Surrounding the transistors with guard rings
• ESD is caused by triobelectric charging which discharges through the IC when the
power is off
• The current produced by an ESD event must be controlled – uniform current flow,
minimum voltage drop, and must not flow through sensitive circuitry
• An ESD event turns on very quickly (1ns), has a high peak current (1A), and lasts for
approximately 100 ns.
• ESD clamps consist of breakdown clamps (snapback) and non-breakdown clamps.
CMOS Analog Circuit Design © P.E. Allen - 2010