This document discusses the construction of an arithmetic logic unit (ALU) using a hardware description language and field programmable gate arrays. Specifically, it simulates and analyzes various parameters of ALUs built using VHDL on the Xilinx ISE 9.2i software and a SPARTAN 3E FPGA board. It also discusses using FPGAs to implement sub-systems for an open-source FPGA-based mobile telephone handset as part of a long-term and complex project. A focus of this project is developing an Ethernet controller and memory mapped I/O interface for an Ethernet PHY.

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ABSTRACT
This paper primarily deals with the construction of arithmetic Logic Unit (ALU) using
Hardware Description Language (HDL) using Xilinx ISE 9.2i and implement them on
Field Programmable Gate Arrays (FPGAs) to analyze the design parameters.ALU of
digital computers is an aspect of logic design with the objective of developing
appropriate algorithms in order to achieve an efficient utilization of the available
hardware. The hardware can only perform a relatively simple and primitive set of
Boolean & arithmetic operations and are based on a hierarchy of operations that are
built by using algorithms employing the hardware. Speed, power and utilization of
ALU are the measures of the efficiency of an algorithm. In this paper, we have
simulated and synthesized the various parameters of ALUs by using VHDL on Xilinx
ISE 9.2i and SPARTAN 3E FPGA board. Keywords: FPGA, ALU, XILINX
Today, open-source software covers a wide range of applications that form part of
everyday life, and which are available to modify and implement it in enhance way for
further uses. Similarly, this Project is based on FPGA (Xilinx Nexys4 used – with its
build Artix7 FPGA chip in it) and will be released under open-source licenses so that
the community can make use of it. One particularly interesting FPGA-based project is
the GNU Radio software-defined radio. This is of interest to the C65GS project as the
basis for a completely open-source FPGA-based mobile telephone handset. This is a
complex and ambitious long-term project. The short-term plan is to implement
various sub-systems in FPGAs to progress towards this goal using the C65GS retro-
computer as a test-bed. Ethernet controller is the focus of this project, which will be
integrated, with C65GS project in future. Secondly, this project specially focuses on
addresses creating, the C65GS compatible memory mapped I/O interface for the
MDIO control interface for the LAN8720A 100mbit Ethernet PHY.