Shantanu Telharkar is pursuing a Master of Science in Electrical Engineering from San Jose State University with a specialization in digital systems and logic design. He has relevant experience as an FPGA systems design intern at MathWorks and as an FPGA design intern at Atria Logic and Interface Design Associates Private Limited. His technical skills include programming languages like C, C++, Verilog, VHDL, and SystemVerilog as well as tools like Xilinx Vivado, MATLAB, and SIMULINK.

1. SHANTANU TELHARKAR
Boston, MA | shantanu.telharkar@sjsu.edu | linkedin.com/in/shantanutel | +1 (669) -236-9423
Education:
SAN JOSE STATE UNIVERSITY (GPA: 3.70/4.0) JAN 2016 - DEC 2017(EXPECTED)
• Master of Science in Electrical Engineering. Specialization: Digital Systems and LogicDesign.
• Coursework: SOC Design and Verification with System Verilog, UVM, ASIC CMOS Design, Advanced Computer
Architecture Embedded SOC Design, Digital Design and Synthesis.
UNIVERSITY OF MUMBAI (GPA: 3.53/4.0) AUG 2011 - JUNE 2015
• Bachelor of Science in Electronics Engineering.
Experience:
FPGA SYSTEMS DESIGN INTERN IN TEST| MATHWORKS | NATICK, MASSACHUSETTS JUNE 2017 – PRESENT
• Testing of Simulink toolbox. Created test harness in MATLAB to test Simulink tool for FPGA modelling.
• Implemented tests to verify functionality of the tool for FPGA memory models having AXI 4 Lite Protocol.
• Gained insights in FPGA memory models and developed MATLAB skills.
• Device: Xilinx Arty. Software tools: MATLAB, Simulink.
FPGA DESIGN INTERN | ATRIA LOGIC | SUNNYVALE, CALIFORNIA FEB 2017 – MAY 2017
• Designed SSD controllers for enabling the SSD device to communicate with NVMe over fabrics protocol.
• Responsible for Board bring up (booting Linux in APU of Zynq MPSOC) and high level block design in XilinxVivado.
• Device: Xilinx MPSoC Ultrascale+.
• Software tools: Xilinx Vivado, Xilinx SDK and PetaLinuxTool.
FPGA DESIGN INTERN | INTERFACE DESIGN ASSOCIATES PRIVATE LIMITED | MUMBAI, INDIA MAY 2014 – AUG 2014
• FPGA Implementation of a stepper motor controller with SPI bus protocol.
• Device: Xilinx Spartan-6. Software tool: Xilinx ISE. Learnt complete FPGA Design Cycle thoroughly.
Projects:
Algorithm to eliminate the redundant sequences and generate automated sequences for Register Testing (UVM, Python)
o Developing an algorithm that eliminates sequences that are redundant to testing. Additionally, tracking the coverage
information of registers in order to ensure that the coverage bins are only hit once, saving simulation time.
Motion estimation on ARM NEON SIMD processor (C, XilinxZybo) March 2017
o Implemented motion estimator using SAD (Sum of absolute differences) on ARM NEON SIMD processor (Xilinx Zybo).
o Gained 5.3x speedup due to vector optimizations.
Sobel filter with OpenMP acceleration (C, DSP) Dec 2016
o Implemented a Sobel Filter to detect edges in an image using Xilinx Zynq board in OpenCV.
Bus master for network on chip (SystemVerilog) Aug 2016
o Developed a network on chip interface for a CRCgenerating machine.
o Developed a bus master that communicates with external memory to fetch data and generate CRC code for it.
o The CRC block was embedded inside this bus mater. Communicates on an 8-bit custom busprotocol.
Functional verification of UART transmitter (UVM) May 2017
o Verified full functionality of UART transmitter of Atmel 328p using UVM.
Floating point adder & multiplier (Verilog) March 2016
o This RTL design performs Box-Muller transform on two random inputs uniformly distributed (0 to1).
o Multiplication and addition was done in a pipelined fashion using floating point adder andmultiplier.
FPGA Implementation of Motion Control Interface (Verilog, Research publication) Summer 2014
o Developed an FPGA Slave precise stepper motor controller that takes instructions from a master (typically a
microprocessor). It communicates over SPI protocol and has arrangements to control 8 motors at atime.
Technical Skills:
Programming languages and HDLs: C, C++, Verilog, VHDL, SystemVerilog, MATLAB, Python, Perl, Embedded C.
Skills: Static Timing Analysis, CDC. Bus protocols: AHB, I2C, UART, PCIe, SPI, APB.
Libraries and Extensions: OpenMP, OpenACC, MPI, CUDA, UVM.
Tools: MATLAB, SIMULINK, Xilinx Vivado, Xilinx SDK, Synopsys VCS Simulator, Altera Quartus, GVIM.