This document summarizes the design and implementation of a 64-bit ALU on an FPGA. The aims were to design a 64-bit ALU that can perform 14 distinct operations using VHDL, capture the design using software tools, verify it through simulation, and test the synthesized design on an FPGA board. Block diagrams and flow charts illustrate the top-level design, instruction selection, and VHDL source code flow. Test results demonstrate arithmetic, logical, and shift operations working as intended. Recommendations include adding multiplication and division capabilities. The conclusion discusses how FPGAs allow modeling, simulating, and reliably implementing complex digital designs in an efficient way.