1. SHANTANU TELHARKAR
San Jose, California | shantanu.telharkar@sjsu.edu | linkedin.com/in/shantanutel | +1 (669)-236-9423
Education:
SAN JOSE STATE UNIVERSITY (GPA: 3.7/4.0) JAN 2016 - DEC 2017 (EXPECTED)
 Master of Science in Electrical Engineering. Specialization: Digital Systems and Logic Design.
 Coursework: SOC Design and Verification with System Verilog, UVM, ASIC CMOS Design, Advanced Computer
Architecture, Embedded SOC Design, Digital Design and Synthesis.
UNIVERSITY OF MUMBAI (GPA: 3.53/4.0) AUG 2011 - JUNE 2015
 Bachelor of Science in Electronics Engineering.
Experience:
FPGA DESIGN INTERN | ATRIA LOGIC | SUNNYVALE, CALIFORNIA FEB 2017 – MAY 2017
 Incorporating SSD controllers on FPGA for enabling the SSD device to communicate with NVMe over fabrics protocol.
 Responsible for hardware block design in Xilinx Vivado, Board bring up (boot Linux) and bare metal tests in Xilinx SDK.
 Achieved Linux boot up successfully with PCIe rootport and 25GMAC Ethernet port.
 Device: Xilinx MPSoC Ultrascale+.
 Software tools: Xilinx Vivado, Xilinx SDK and PetaLinux Tool.
FPGA DESIGN INTERN | INTERFACE DESIGN ASSOCIATES PRIVATE LIMITED | MUMBAI, INDIA MAY 2014 – AUG 2014
 FPGA Implementation of a stepper motor controller with SPI bus protocol.
 Device: Xilinx Spartan-6. Software tool: Xilinx ISE. Complete FPGA Design Cycle was learnt from this internship.
Projects:
Automated sequence generator for code coverage maximization (Python scripting, On going) May 2017
o Developing Python based automated UVM sequence generator that maximizes coverage of a specific family of DUTs.
Bus master for network on chip (SystemVerilog) Aug 2016
o Developed a network on chip interface for a CRC generator machine.
o Developed a bus master that communicates with external memory to fetch data and generate CRC code for it.
o The CRC block was embedded inside this bus mater. Communicates on an 8-bit custom bus protocol.
Floating point adder & multiplier (Verilog) March 2016
o This RTL design performs Box-Muller transform on two random inputs uniformly distributed (0 to 1).
o The sine and square root values required for the Box-Muller transform were pulled from a lookup table.
o Multiplication and addition was done in a pipelined fashion using floating point adder and multiplier.
Sobel filter with OpenMP acceleration (C, Xilinx Zynq-7000 FPGA) Dec 2016
o Implemented a Sobel Filter to detect edges in an image using Xilinx Zynq board in C language.
o Accelerated it using OpenMP compiler directives. Speed gain: 2.5x.
Motion estimation on ARM NEON SIMD processor (C, Xilinx Zynq-7000 FPGA) Nov 2016
o Implemented motion estimator using SAD (Sum of absolute differences) on ARM NEON SIMD processor (Xilinx Zynq).
o Accelerated it using ARM vector optimizations. Speed gain: 5.3x.
Sobel Filter (MATLAB) May 2016
o Implemented a Sobel filter in MATLAB to detect edges of an image.
Research Publication:
FPGA Implementation of Motion Control Interface (Verilog, Xilinx Spartan-6 FPGA) May - Aug 2014
o Developed an FPGA Slave precise stepper motor controller that takes instructions from a master (typically a
microprocessor). It communicates over SPI protocol and has arrangements to control 8 motors at a time.
Technical Skills:
Programming languages and HDLs: C, C++, Verilog, VHDL, SystemVerilog, Assembly Language, Python, Tcl, Embedded C.
Skills: AHB, I2C, UART, PCIe, SPI, APB | Libraries and Extensions: OpenMP, OpenACC, MPI, UVM.
Tools: Xilinx Vivado, Xilinx SDK, Synopsys VCS Simulator, Altera Quartus, Linux/UNIX command line, GVIM, MATLAB.
Key skills: Logic optimization, Functional verification, Coverage analysis, ASIC Design, DFT, Static Timing Analysis (STA).