Shantanu Telharkar

San Francisco Bay Area United States

FPGA Systems Design Intern at MathWorks

Actively seeking full time jobs starting January 2018. I possess deep interest in building digital designs and verifying them. I am eagerly looking to delve for such opportunities to work at interesting places. I am currently pursuing Master's in Electrical Engineering at San Jose State University with Specialization in Digital Systems and Logic Design. To the world, I project myself as a fast paced individual who loves to solve problems with a practical approach. To build skill in the area of my interest, I am actively seeking internship opportunities in the fields of ASIC FPGA Design and Verification, Computer Architecture. → HDL and Verification Methodologies: UVM, Verilog, SystemVe...