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Fet basics-1
The document discusses Field Effect Transistors (FETs). It begins by defining some key characteristics of FETs, including that they are unipolar devices controlled by voltage and have very high input impedance. It then describes different types of FETs, including JFETs, MOSFETs, and discusses their characteristics such as transfer curves. The document provides examples of biasing circuits used for FETs and analyzing FET amplifiers at mid-frequency.
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Fet basics-1
- 1. FET ( FieldEffect Transistor) 1. Unipolar device i. e. operation depends on only one type of charge carriers (h or e) 2. Voltage controlled Device (gate voltage controls drain current) 3. Very high input impedance (≈109 -1012 Ω) 4. Source and drain are interchangeable in most Low-frequency applications 5. Low Voltage Low Current Operation is possible (Low-power consumption) 6. Less Noisy as Compared to BJT 7. No minority carrier storage (Turn off is faster) 8. Self limiting device 9. Very small in size, occupies very small space in ICs 10. Low voltage low current operation is possible in MOSFETS 11. Zero temperature drift of out put is possiblek Few important advantages of FET over conventional Transistors
- 2. Types of FieldEffect Transistors (The Classification) » JFET MOSFET (IGFET) n-Channel JFET p-Channel JFET n-Channel EMOSFET p-Channel EMOSFET Enhancement MOSFET Depletion MOSFET n-Channel DMOSFET p-Channel DMOSFET FET
- 3. Figure: n-Channel JFET. TheJunction Field Effect Transistor (JFET)
- 4. Gate Drain Source SYMBOLS n-channel JFET Gate Drain Source n-channel JFET Offset-gatesymbol Gate Drain Source p-channel JFET
- 5. Figure: n-Channel JFETand Biasing Circuit. Biasing the JFET
- 6. Figure: The nonconductivedepletion region becomes broader with increased reverse bias. (Note: The two gate regions of each FET are connected to each other.) Operation of JFET at Various Gate Bias Potentials
- 7. P P + - DCVoltage Source + - + - N N Operation of a JFET Gate Drain Source
- 8. Figure: Circuit fordrain characteristics of the n-channel JFET and its Drain characteristics. Non-saturation (Ohmic) Region: The drain current is given by − −= 2 2 2 2 DS DSPGS P DSS DS V VVV V I I −= 2 2 PGS P DSS DS VV V I I 2 1and −= P GS DSSDS V V II Where, IDSS is the short circuit drain current, VP is the pinch off voltage Output or Drain (VD-ID) Characteristics of n-JFET Saturation (or Pinchoff) Region: −< PGSDS VVV −≥ PGSDS VVV
- 9. Figure: n-Channel FETfor vGS = 0. Simple Operation and Break down of n-Channel JFET
- 10. Figure: If vDGexceeds the breakdown voltage VB, drain current increases rapidly. Break Down Region N-Channel JFET Characteristics and Breakdown
- 11. Figure: Typical draincharacteristics of an n-channel JFET. VD-ID Characteristics of EMOS FET Saturation or Pinch off Reg. Locus of pts where ( )PGSDS VVV −=
- 12. Figure: Transfer (orMutual) Characteristics of n-Channel JFET 2 1 −= P GS DSSDS V V II IDSS VGS (off)=VP Transfer (Mutual) Characteristics of n-Channel JFET
- 13. JFET Transfer Curve Thisgraph shows the value of ID for a given value of VGS
- 14. Biasing Circuits usedfor JFET • Fixed bias circuit • Self bias circuit • Potential Divider bias circuit
- 15. JFET (n-channel) BiasingCircuits 2 1 −= P GS DSSDS V V II 0, ===+= GGSGSGGGG IFixedVVRIV DDSDDDS P GS DSSDS RIVV V V II −= −= and 1 2 S GS DS SDSGS R V I RIV −=∴ =+ 0 For Self Bias Circuit For Fixed Bias Circuit Applying KVL to gate circuit we get and Where, Vp=VGS-off & IDSS is Short ckt. IDS
- 16. JFETJFET BiasingBiasing CircuitsCount…Circuits Count… or Fixed Bias Ckt.
- 17. JFET Self (orSource) Bias Circuit 2 1and −= P GS DSSDS V V II S GS P GS DSS R V V V I −= −∴ 2 1 021 2 =+ +− S GS P GS P GS DSS R V V V V V I This quadratic equation can be solved for VGS & IDS
- 18. The Potential (Voltage)Divider Bias 01 2 = − − −∴ S GSG P GS DSS R VV V V I DSGS IVgivesequationquadraticthisSolving and
- 19. A Simple CSAmplifier and Variation in IDS with Vgs
- 20. FET Mid-frequency Analysis: g s rd gmvπ vi= vπ ii io vo d s + + _ _ mid-frequency CE amplifier circuit RD RLRThvs + _ is ' 'o o i vi m L L d D L vs vi i s s i i i Th Th 1 2 i Analysis of the CS mid-frequency circuit above yields: v v Z A = = -g R , where R = r R R A = = A v v R + Z v Z = = R , where R = R R i L o i I vi i L o o o d D P vi I o iseen by R i Z A = = A i R v p Z = = r R A = = A A i p A common source (CS) amplifier is shown to the right. Rs Ci RL Co CSS vi vo + + vs + _ _ _ io ii D S G VDD VDD R1 RSS RD R2 The mid-frequency circuit is drawn as follows: • the coupling capacitors (Ci and Co) and the bypass capacitor (CSS) are short circuits • short the DC supply voltage (superposition) • replace the FET with the hybrid-π model The resulting mid-frequency circuit is shown below.
- 21. FET Mid-frequency Analysis: g s rd gmvπ vi= vπ ii io vo d s + + _ _ mid-frequency CE amplifier circuit RD RLRThvs + _ is ' 'o o i vi m L L d D L vs vi i s s i i i Th Th 1 2 i Analysis of the CS mid-frequency circuit above yields: v v Z A = = -g R , where R = r R R A = = A v v R + Z v Z = = R , where R = R R i L o i I vi i L o o o d D P vi I o iseen by R i Z A = = A i R v p Z = = r R A = = A A i p A common source (CS) amplifier is shown to the right. Rs Ci RL Co CSS vi vo + + vs + _ _ _ io ii D S G VDD VDD R1 RSS RD R2 The mid-frequency circuit is drawn as follows: • the coupling capacitors (Ci and Co) and the bypass capacitor (CSS) are short circuits • short the DC supply voltage (superposition) • replace the FET with the hybrid-π model The resulting mid-frequency circuit is shown below.
- 22. Procedure: Analysis ofan FET amplifier at mid-frequency: 1) Find the DC Q-point. This will insure that the FET is operating in the saturation region and these values are needed for the next step. 2) Find gm. If gm is not specified, calculate it using the DC values of VGS as follows: 3) Calculate the required values (typically Avi, Avs, AI, AP, Zi, and Zo. Use the formulas for the appropriate amplifier configuration (CS, CG, CD, etc). ( ) ( ) DSSD m GS P2 GS P D m GS T GS GS 2II g = = V - V (for JFET's and DM MOSFET's) V V I g = = V - V (for EM MOSFET's) V (Note: Uses DC value of V ) K ∂ ∂ ∂ ∂
- 23. PE-Electrical Review Course- Class 4 (Transistors) Example 7: Find the mid-frequency values for Avi, Avs, AI, AP, Zi, and Zo for the amplifier shown below. Assume that Ci, Co, and CSS are large. Note that this is the same biasing circuit used in Ex. 2, so VGS = -0.178 V. The JFET has the following specifications: ΙDSS = 4 mA, VP = -1.46 V, rd = 50 k 10 k Ci 8 k Co CSS vi vo + + vs + _ _ _ io ii D S G 18 V 18 V 800 k 2 k 500 400 k
- 24. FET Amplifier Configurationsand Relationships: ' ' ' m L vi m L m L ' m L ' L d D L d D L SS L i Th SS Th m o d D d D SS m i i i vs vi vi vi s i s i s i i i i I vi vi vi L L L P vi I vi I CS CG CD g R A -g R g R 1 g R R r R R r R R R R 1 Z R R R g 1 Z r R r R R g Z Z Z A A A A R + Z R + Z R + Z Z Z Z A A A A R R R A A A A A + vi I Th 1 2 A A where R = R R VCC RD S R2 RSS Rs Ci RL Co C2 vi vo + + vs + _ __ io ii Common Gate (CG) Amplifier R1 D G Note: The biasing circuit is the same for each amp. Rs Ci RL Co CSS vi vo + + vs + _ _ _ io ii D S G VDD VDD R1 RSS RD R2 Common Source (CS) Amplifier Rs Ci vi + vs + _ _ ii G VDD VDD R1 RSS R2 Common Drain (CD) Amplifier (also called “source follower”) RL Co vo + _ io D S
- 25. Figure: Circuit symbolfor an enhancement-mode n-channel MOSFET.
- 26. Figure: n-Channel EnhancementMOSFET showing channel length L and channel width W.
- 27. Figure: For vGS< Vto the pn junction between drain and body is reverse biased and iD=0.
- 28. Figure: For vGS>Vto a channel of n-type material is induced in the region under the gate. As vGS increases, the channel becomes thicker. For small values of vDS ,iD is proportional to vDS. The device behaves as a resistor whose value depends on vGS.
- 29. Figure: As vDSincreases, the channel pinches down at the drain end and iD increases more slowly. Finally for vDS> vGS -Vto, iD becomes constant.
- 30. Current-Voltage Relationship of n-EMOSFET Locusof points where
- 31.
- 32. Figure: This circuitcan be used to plot drain characteristics.
- 33. Figure: Diodes protectthe oxide layer from destruction by static electric charge.
- 34. Figure: Simple NMOSamplifier circuit and Characteristics with load line.
- 35. Figure: Drain characteristicsand load line
- 36. Figure vDS versustime for the circuit of Figure 5.13.
- 37. Figure Fixed- plusself-bias circuit.
- 38. Figure Graphical solutionof Equations (5.17) and (5.18).
- 39. Figure Fixed- plusself-biased circuit of Example 5.3.
- 40. Figure The morenearly horizontal bias line results in less change in the Q-point.
- 41. Figure Small-signal equivalentcircuit for FETs.
- 42. Figure FET small-signalequivalent circuit that accounts for the dependence of iD on vDS.
- 43. Figure Determination ofgm and rd. See Example 5.5.
- 44.
- 45. For drawing ana c equivalent circuit of Amp. •Assume all Capacitors C1, C2, Cs as short circuit elements for ac signal •Short circuit the d c supply •Replace the FET by its small signal model
- 46. Analysis of CSAmplifier LgsmLoo gs o v RvgRiv v v A −==∴ =gain,Voltage dDLLm gs o v rRRRg v v A =−==∴ , Dd Dd Ddo Rr Rr RrZ + ==imp.,putOut 21 imp.,Input RRRZ Gin == A C Equivalent Circuit Simplified A C Equivalent Circuit
- 47. Analysis of CSAmplifier with Potential Divider Bias )R||(rgAv Ddm−= D R10rD,m d RgAv ≥−≅ )R||(rgAv Ddm−= This is a CS amplifier configuration therefore the input is on the gate and the output is on the drain. 21 R||RZi = Dd R||rZo = Dd D 10Rr RZo ≥ ≅
- 48. Figure vo(t) andvin(t) versus time for the common-source amplifier of Figure 5.28.
- 49. Figure Common-source amplifier. AnAmplifier Circuit using MOSFET(CS Amp.)
- 50. Figure Small-signal equivalentcircuit for the common-source amplifier. A small signal equivalent circuit of CS Amp.
- 51. Figure vo(t) andvin(t) versus time for the common-source amplifier of Figure 5.28.
- 52. Figure Gain magnitudeversus frequency for the common-source amplifier of Figure 5.28.
- 53.
- 54. Figure Small-signal acequivalent circuit for the source follower.
- 55. Figure Equivalent circuitused to find the output resistance of the source follower.
- 56.
- 57. Figure See Exercise5.12.
- 58. Figure Drain currentversus drain-to-source voltage for zero gate-to-source voltage.
- 59. Figure n-Channel depletionMOSFET.
- 60. Figure Characteristic curvesfor an NMOS transistor.
- 61. Figure Drain currentversus vGS in the saturation region for n-channel devices.
- 62. Figure p-Channel FETcircuit symbols. These are the same as the circuit symbols for n-channel devices, except for the directions of the arrowheads.
- 63. Figure Drain currentversus vGS for several types of FETs. iD is referenced into the drain terminal for n-channel devices and out of the drain for p-channel devices.