Field Effect Transistor

FET
(FIELD EFFECT
TRANSISTOR)
Engr. Jess Rangcasajo
jessrangcasajo@gmail.com
ECE 321 Instructor

FET’S VS. BJT’S
Similarities:
Amplifiers
Switching Device
Impedance Matching Circuits

DIFFERENCES
 Voltage controlled devices
 Higher input impedance
 Less sensitive to temp.
variations
 Unipolar device
 Smaller/ Easily Integrated
Chips
 Current controlled devices
 Lower impedance
 Higher sensitive
 Bipolar device
 Bigger IC
FET’s BJT’s

TYPES OF FET
1. JFET (Junction FET)
2. MESFET (metal-semiconductor FET)
3. MOSFET (metal-oxide-semiconductor FET)
a. D-MOSFET (Depletion)
b. E-MOSFET (Enhancement)

DR. IAN MUNRO ROSS
&
G.C DACEY
- Jointly developed an experimental
procedure for measuring the
characteristics of FET in 1955

CONSTRUCTION AND CHARACTERISTICS OF
JFET
 Is a three-terminal device with one terminal capable
of controlling the current between the other two.
3 terminals are:
1. DRAIN (D)
2. SOURCE (S) – connected to n-channel
3. GATE (G) – connected to p-channel

Two types of JFET
1.n-channel
2.p-channel
Note:
 n-channel is more widely used.
Drain
Gate
Source
Drain
Gate
Source

n-channel p-channel
D
G
S
D
G
S

•Drain (D) and Source (S) are connected to the n-channel
•Gate (G) is connected to the p-type material

JFET OPERATING
CHARACTERISTICS

JFET is always operated with the gate-
source PN junction reversed biased.
Reverse biasing of the gate source
junction with the negative voltage
produces a depletion region along the PN
junction which extends into the n-channel
and thus increases its resistance by
restricting the channel width as shown in
the preceding figure.

𝑽 𝑮𝑺 = 𝟎, 𝑽 𝑫𝑺 SOME POSITIVE VALUE
When 𝐕𝐆𝐒 = 𝟎 𝐚𝐧𝐝 𝐕 𝐃𝐒 is increased from 0
to a more positive voltage.
 The depletion region between p-gate
and n-channel increases
 Increasing the depletion region,
decreases the size of the n-channel
which increases the resistance of the n-
channel.
 Even though the n-channel resistance is
increasing, the current (ID) from source
to drain through the n-channel is
increasing. This is because VDS is
increasing.
Recall from DIODE discussion:
- The greater the applied reverse bias, the wider is the depletion region.
IG = 0

REGIONS OF JFET ACTION
1. Ohmic Region – linear region
 JFET behaves like an ordinary resistor
2. Pinch Off Region
 Saturation or Amplifier Region
 JFET operates as a constant current device because Id is
relatively independent of Vds
 Idss – drain current with gate shorted to source.
3. Breakdown Region
 If Vds is increased beyond its value corresponding to Va –
avalanche breakdown voltage.
 JFET enters the breakdown region where Id increases to
an excessive value.

4. Cut Off Region
 As Vgs is made more and more negative, the gate
reverse bias increases which increases the thickness of
the depletion region.
 As negative value of Vgs is increased, a stage comes
when the 2 depletion regions touch each other.
Vgs (off) = -Vp
/Vp/ = /Vgsoff/

JFET OPERATING CHARACTERISTICS: PINCH OFF
 If VGS = 0 and VDS is further
increased to a more positive
voltage, then the depletion zone
gets so large that it pinches off the
n-channel.
 As VDS is increased beyond |VP |,
the level of ID remains the same
(ID= IDSS)

𝑽 𝑮𝑺 ≥ 𝟎
 Voltage from gate to source is
controlling voltage of the JFET.
 As 𝐕 𝐆𝐒 becomes more negative, the
depletion region increases.
 The more negative 𝐕 𝐆𝐒, the resulting
level for 𝐈 𝐃 is reduced.
 Eventually, when 𝐕 𝐆𝐒 = 𝐕𝐩 [Vp = VGS
(off)], ID is 0 mA. (the device is
“turned off”.

JFET OPERATING CHARACTERISTICS
n-Channel JFET characteristics with IDSS = 8 mA and VP = -4 V.

JFET OPERATING CHARACTERISTICS: VOLTAGE-
CONTROLLED RESISTOR
The region to the left of the pinch-
off point is called the ohmic
region/Voltage controlled
resistance region.
The JFET can be used as a variable resistor, where VGS controls the drain-
source resistance (rd). As VGS becomes more negative, the resistance (rd)
increases

where ro is the resistance with VGS=0 and rd is the
resistance at a particular level of VGS.

1. For an n-channel JFET with 𝑟𝑜 = 10𝑘Ω 𝑉𝐺𝑆 =
FOR EXAMPLE:
𝑟𝑑 =
10𝑘Ω
(1 −
−3
−6
)2
𝑟𝑑 = 40𝑘Ω

P-CHANNEL JFETS
The p-channel JFET behaves the same as the n-
channel JFET, except the voltage polarities and
current directions are reversed.

P-CHANNEL JFET CHARACTERISTICS
Also note that at high levels of VDS
the JFET reaches a breakdown
situation: ID increases uncontrollably
if VDS > VDSmax

JFET SYMBOLS
JFET symbols: (a) n-channel; (b) p-channel.

SUMMARY:
Important parameters to remember:
VGS = 0V, ID = IDSS
Cutoff (𝐼 𝐷 = 0𝐴)
𝑉𝐺𝑆 less than the pinch
off level

𝐼 𝐷 is between 0 A and 𝐼 𝐷𝑆𝑆 𝑓𝑜𝑟 𝑉𝐺𝑆 ≤
0𝑉 𝑎𝑛𝑑 𝑔𝑟𝑒𝑎𝑡𝑒𝑟 𝑡ℎ𝑎𝑛 𝑡ℎ𝑒 𝑝𝑖𝑐𝑛ℎ 𝑜𝑓𝑓 𝑙𝑒𝑣𝑒𝑙.

JFET TRANSFER CHARACTERISTICS
In a BJT, 𝛽 indicates the relationship between 𝐼 𝐵 (input) and 𝐼 𝐶 (output).
𝐼 𝐶 = 𝑓 𝐼 𝐵 = 𝛽𝐼 𝑏
Constant
Control variable
In a JFET, the relationship of 𝑉𝐺𝑆 (input) and 𝐼 𝐷 (output) is defined by
Shockley’s Equation
𝐼 𝐷 = 𝐼 𝐷𝑆𝑆 1 −
𝑉𝐺𝑆
𝑉𝑝
2
Constant
Control variable

William Bradford Shockley
(1910–1989)
Co-inventor of the first
transistor and formulator of
the “field effect” theory
employed in the development
of the transistor and the FET

This graph shows the value of 𝑰 𝑫 for a given value of 𝑽 𝑮𝑺.

PLOTTING THE JFET TRANSFER CURVE
Using 𝐼 𝐷𝑆𝑆 and 𝑉𝑝 (𝑉𝐺𝑆(𝑜𝑓𝑓)) values found in a specification sheet, the transfer
curve can be plotted according to these three steps:
Step 1:
Solving for 𝑉𝐺𝑆 = 0, 𝐼 𝐷 = 𝐼 𝐷𝑆𝑆 1 −
𝑉𝐺𝑆
𝑉𝑝
2
, ID = IDSS
Step 2:
Solving for 𝑉𝐺𝑆 = 𝑉𝑝(𝑉𝐺𝑆 𝑜𝑓𝑓 ), 𝐼 𝐷 = 𝐼 𝐷𝑆𝑆 1 −
𝑉𝐺𝑆
𝑉𝑝
2
, ID = 0 A
Step 3:
Solving for 𝐼 𝐷 if we substitute 𝑉𝐺𝑆 = −1 𝑉 , 𝐼 𝐷𝑆𝑆 = 8mA and 𝑉𝑝 =-4
𝑉𝐺𝑆
𝑉𝑝
2
, 𝐼 𝐷 = 8𝑚𝐴 1 −
(−1)
(−4)
2
,
ID = 4.5mA

Conversely, for a given
𝐼 𝐷, 𝑉𝐺𝑆 can be obtained:
𝑉𝐺𝑆 = 𝑉𝑝 1 −
𝐼 𝐷
𝐼 𝐷𝑆𝑆
𝑉𝐺𝑆
𝑉𝑝
2
Shorthand
Method:
𝐼 𝐷 =
𝐼 𝐷𝑆𝑆
4
𝑉𝐺𝑆 =
𝑉𝑝
2
𝑉𝐺𝑆 ≅ 0.3𝑉𝑝 𝐼 𝐷 =
𝐼 𝐷𝑆𝑆
2

Sketch the transfer curve defined by 𝐼 𝐷𝑆𝑆 = 12𝑚𝐴 and 𝑉𝑝 = −6𝑉.
For Example:
By shorthand method,
𝑉𝐺𝑆 =
𝑉𝑝
2
= −6
2 = −𝟑𝑽
𝐼 𝐷 =
𝐼 𝐷𝑆𝑆
4
= 12𝑚𝐴
4 = 𝟑𝒎𝑨
@
@
𝐼 𝐷 =
𝐼 𝐷𝑆𝑆
2
= 12𝑚𝐴
2 = 𝟔𝒎𝑨
𝑉𝐺𝑆 ≅ 0.3𝑉𝑝 = 0.3 −6𝑉 = −𝟏. 𝟖𝑽

MOSFET
(METAL-OXIDE-
SEMICONDUCTOR FET)

THERE ARE TWO TYPES OF MOSFETS:
 Depletion-Type
 Enhancement-Type

DEPLETION-TYPE MOSFET CONSTRUCTION
 The Drain (D) and Source (S)
connect to the to n-doped regions.
 These n-doped regions are
connected via an n-channel.
 This n-channel is connected to the
Gate (G) via a thin insulating layer
of SiO2.
 The n-doped material lies on a p-
doped substrate that may have an
additional terminal connection
called Substrate (SS).
n-Channel depletion-type
MOSFET
Dielectric
insulator

SILICON DIOXIDE:
 Insulator refer to as DIELECTRIC.
 It sets up opposing electric field within the dielectric
when exposed to an externally applied field.
 The fact that SiO2 layer is an insulating layer means
that:
There is no direct electrical connection between the gate terminal and
the channel of a MOSFET.
It is the insulating layer of SiO2 in the MOSFET construction that
accounts for the very desirable high input impedance of the device

WHY MOSFET?
 Metal:
 For the drain, source, and gate connection for the proper surface
– in particular, the gate terminal and the control to be offered by
the surface area of the contact.
 Oxide:
 For the Silicon dioxide insulating layer.
 Semiconductor:
 For the basic structure on which the n- and p-type region are
DIFFUSED.
MOSFET is also called
INSULATED GATE-FET or IGFET

DEPLETION-TYPE MOSFET :BASIC OPERATION
AND CHARACTERISTICS
 VGS = 0 and VDS is applied
across the drain to source
terminals.
 This results to attraction of
free electrons of the n-
channel to the drain, and
hence current flows.

Continuation….
 𝑉𝐺𝑆 is set at a negative voltage such as
-1 V
 The negative potential at the gate
pressure electrons toward the p-type
substrate and attract the holes for the
p-type substrate.
 This will reduce the number of free
electrons in the n-channel available for
conduction.
 The more negative the 𝑉𝐺𝑆 , the
resulting level of drain current 𝐼 𝐷 is
reduced.
 When 𝑉𝐺𝑆 is reduced to 𝑉𝑃 (pinch off
voltage), then 𝐼 𝐷 = 0𝑚𝐴.

When 𝑉𝐺𝑆 is reduced to 𝑉𝑃 (pinch off) {i.e 𝑉𝑃 = −6𝑉} then 𝐼 𝐷 = 0𝑚𝐴.
For positive values of 𝑉𝐺𝑆, the positive gate will draw additional electrons
(free carriers from the p-type substarte and hence 𝐼 𝐷 increases.)

DEPLETION-TYPE MOSFET CAN OPERATE IN TWO
MODES:
 Depletion mode
 Enhancement mode

D-TYPE MOSFET IN DEPLETION MODE
The characteristics are similar to a
JFET.
 When 𝑉𝐺𝑆 = 0𝑉, 𝐼 𝐷 = 𝐼 𝐷𝑆𝑆
 When 𝑉𝐺𝑆 < 0𝑉, 𝐼 𝐷 < 𝐼 𝐷𝑆𝑆
𝑉𝐺𝑆
𝑉𝑝
2

D-TYPE MOSFET IN ENHANCEMENT MODE
@ 𝑉𝐺𝑆 > 0
𝐼 𝐷 increase above the 𝐼 𝐷𝑆𝑆
𝑉𝐺𝑆
𝑉𝑝
2
Note:
𝑉𝐺𝑆 is now positive polarity

ENHANCEMENT-TYPE MOSFET CONSTRUCTION
 The Drain (D) and Source (S)
connect to the to n-doped
regions.
 The Gate (G) connects to the p-
doped substrate via a thin
insulating layer of SiO2
 There is no channel
 The n-doped material lies on a p-
doped substrate that may have
an additional terminal connection

 For 𝑉𝐺𝑆 = 0, 𝐼 𝐷 = 0(no channel)
 For 𝑉𝐷𝑆 some positive voltage and 𝑉𝐺𝑆
= 0, two reversed biased n-junctions
and no significant flow between drain
and source.
 For 𝑉𝐺𝑆 > 0 and 𝑉𝐺𝑆 > 0, the positive
voltage at gate pressure holes to enter
deeper regions of the p-substrate, and
the electrons in p-substrate and the
electrons in p-substrate will be
attracted to the positive gate.
 The level of 𝑉𝐺𝑆 that results in the
significant increase in drain current in
called:
THRESHOLD VOLTAGE (Vt)
 For 𝑉𝐺𝑆 < 𝑉𝑇, 𝐼 𝐷 = 0𝑚𝑎

BASIC OPERATION OF THE E-TYPE MOSFET
Note:
The enhancement-type
MOSFET operates only in the
enhancement mode
 𝑉𝐺𝑆 is always positive
 As 𝑉𝐺𝑆 increases, 𝐼 𝐷 increases
 As 𝑉𝐺𝑆 is kept constant and 𝑉𝐷𝑆 is
increased, then 𝐼 𝐷 saturates (𝐼 𝐷𝑆𝑆)
and the saturation level, 𝑉𝐷𝑆𝑠𝑎𝑡 is
reached.
 𝑉𝐷𝑆𝑠𝑎𝑡 can be calculated by
𝑉𝐷𝑠𝑎𝑡 = 𝑉𝐺𝑆 − 𝑉𝑇

E-TYPE MOSFET TRANSFER CURVE
To determine 𝐼 𝐷 given 𝑉𝐺𝑆:
Where,
𝑉𝑇 is the threshold voltage or voltage at which the MOSFET turns on.
𝑘, a constant, can be determined by using values at a specific point and the
formula:

FOR EXAMPLE:
Substituting 𝐼 𝐷(𝑜𝑛) = 10𝑚𝐴 𝑤ℎ𝑒𝑛 𝑉𝐺𝑆(𝑜𝑛) = 8𝑉
The level of 𝑉𝑇 is 2V, as revealed by the
fact that the drain current has dropped
to 0 mA.
𝑘 =
10𝑚𝐴
(8𝑉 − 2𝑉)2
= 𝟎. 𝟐𝟕𝟖𝒙𝟏𝟎−𝟑 𝑨
𝑽 𝟐

Note:
For values of 𝑉𝐺𝑆 less than the threshold level, the drain current of an enhancement
type MOSFET is 0 mA.
Substituting the 𝑉𝐺𝑆 from the general equation:
𝐼 𝐷 = 𝑘(𝑉𝐺𝑆 − 𝑉𝑇)2
𝑘 = 0.278𝑥10−3
𝐼 𝐷 = 0.278𝑚𝐴/𝑉2(𝑉𝐺𝑆 − 2𝑉)2
i.e substituting 𝑉𝐺𝑆 = 4𝑉, we find that
𝐼 𝐷 = 0.278𝑚𝐴/𝑉2
(4𝑉 − 2𝑉)2
𝑰 𝑫 = 𝟏. 𝟏𝟏𝒎𝑨

VMOS CHARACTERISTICS:
 Compared with commercially available planar
MOSFETs, VMOS FETs have reduced channel
resistance levels and higher current and power
ratings
 VMOS FETs have a positive temperature
coefficient that will combat the possibility of thermal
runaway
 The reduced charge storage levels result in faster
switching times for VMOS construction compared
to those for conventional planar construction

CMOS CHARACTERISTICS:
 Extensive application in computer logic
design
 Relatively high input impedance
 Fast switching speeds
 Lower operating power levels – CMOS
logic design

Reference
 Boylestad, R. L., Nashelsky, L., & Li, L. (2002). Electronic devices and circuit
theory (Vol. 11). Englewood Cliffs, NJ: Prentice Hall.
 Boylestad, R. L. (2010). Introductory circuit analysis. Pearson Education.

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