basic electronics presentation made from various books

1. B .E Pre s e nt a t oi n

3. Invention
• In 1947, John Bardeen, Walter
Brattain, and William Schockly,
researchers at Bell Lab, invented
Transistor.
• They found Transistor Effect: “when
electrical contacts were applied to a
crystal of germanium, the output
power was larger than the input.”
• Awarded the Nobel Prize in physics
(1956)
• Revolutionized portability and
efficiency of electronic devices
John Bardeen, Walter
Brattain, and William
Schockly
First model of Transistor, 1947

4. FET
JFET
MOSFE
T
N-
channel
P-
channel
D-
MOSFET
E-
MOSFET
P-channel P-
channel
N-
channel
N-
channel

5. FIELD-EFFECT
TRANSISTORS
Field-effect transistors (FETs) follow
an other principle than bipolar
junction transistors
Meaning of “Field Effect” ,An electric field
is develop by the charges , this electric
field controls the conduction path of the
output ckt . So there is an effect due to
electric field and because of this reason
we call the device field effect
FETs controlled by voltage

6. Similarities:
• Amplifiers
• Switching Device
• Impedance Matching Circuits

7. DIFFERENCES
• Voltage controlled devices
• Higher input impedance
• Less sensitive to temp.
variations
• Unipolar device
• Smaller/ Easily Integrated
Chips
• Current controlled devices
• Lower impedance
• Higher sensitive
• Bipolar device
• Bigger IC
FET’s BJT’s

8. GENERAL OVERVIEW
• Basic Concept :
• The terminals of a FET refer to their function: Gate (G), Source
(S), Drain (D)
• FETs are voltage-controlled by the voltage between gate and
source terminal
• Voltage effects the electric field of the transistor which enlarges
or diminishes the channel

9. CONSTRUCTION OF FET
• Source: The source is the terminal through which majority
carriers enter the Silicon Bar
• Drain: Terminal through which Majoroty carriers leave the bar
• Gate: controls Drain current and is always reverse biased

10. ANALOGY OF FET WITH WATER
• The operation of FET can be compared to the water flow
through a flexible pipe
• When One end is pressed the cross sectional area decreases
hence water flow decreases
• In a FET drain is similar to outlet
• Gate is similar to control in the figure below:

12. ++++
++++
++++
+++
-----
-----
-----
-----
----
P N
Concept of
diode
V(in
)
V(ou
t)
Forwar
d
Biased

13. V(in
)
V(out
)
V(in
)
V(out
)
P N
P N
Reverse
d
Biased
Reverse
d
Biased

14. THE
CONCLUSION
IS…….
A PN Junction with reversed biased..
Establish “depletion region”
There is no current through the junction
As the increased in voltage , the wider
the deption region.
Depletion region has no free charges.
Depletion region has fixed space.

16. JUNCTION FIELD-EFFECT TRANSISTORS
(JFETS)
• Simplest type of FET
• Long channel semiconductor
• Either p- or n-doped (p-type, n-type)
• A contact at each ends at source and drain terminals
• Gate terminal surrounds the channel and is doped opposite to
the doping of the channel

18. N PP
Gate
Source
Drain
JFET

19. N PP
Gate
Sourc
e
Drain
N
channel
I(ds)
v(ds)
Reversed bias
V(gs)
increased
V(GS)= 0
V(GS)=-0.5
V(GS)=-1
V(GS)=-1.5
V(GS)=-2
V(GS)=-2.5
I
(ds)

20. N PP
Gate
Sourc
e
Drain
N
channel
Reversed bias Pinch off
I
(ds)

22. if VDD is increased from 0 V, Id will increase
proportionally, as shown in the graph of Figure .In
this area, the channel resistance is essentially
constant because the depletion region is not large
enough to have significant effect. This is called
the ohmic region because VDS and ID are related
by Ohm’s law
when ID begins
to increase
very rapidly with
any
further increase
in VDS.
Breakdown can
result in
irreversible
damage to the
device, so JFETs
are always
operated below
breakdown and
within the active

23. • VGS Controls ID : If VGS is set to increase by adjusting
VGG . ID decreases as the magnitude of VGS is increased
to larger negative values because of the narrowing of the
channel
Regions :
 Ohmic Region – linear region
• JFET behaves like an ordinary resistor

24. • Saturation or Amplifier Region
• JFET operates as a constant current device because Id is relatively
independent of Vds
Breakdown Region
• If Vds is increased beyond its value corresponding to Va – avalanche
breakdown voltage.
• JFET enters the breakdown region where Id increases to an
excessive value.
Cut Off Region
• As Vgs is made more and more negative, the gate reverse bias
increases which increases the thickness of the depletion region.
• As negative value of Vgs is increased, a stage comes when the 2
depletion regions touch each other. Vgs (off) = -Vp /Vp/ =

25. T

26. METAL OXIDE SEMICONDUCTOR FET:
MOSFET
• As Compared to BJT, MOS transistor can be made
quiet small and their manufacturing process is
relatively simple.
• MOSFET also known as insulated-gate field-effect
transistors (IGFET) is preferred in power electronics
due to its ability of fast switching especially in timing
circuits.
• MOSFET has a "Metal Oxide" gate(silicon dioxide-

27. •This isolation of the controlling gate makes the
input resistance of the MOSFET extremely high
in the Mega-ohms region (infinite), thus
switching loss at input side can controlled and
stabilized.
•As the gate terminal is isolated from the main c
urrent carrying channel "No current flows into
the gate” so MOSFET acts as a voltage
controlled resistor (like JFET).
•MOSFET is specially used in digital

28. N-CHANNEL E-MOSFET SHOWING CHANNEL
LENGTH LAND CHANNEL WIDTH W

29. Substrate
Channel Drain
Insulator
Gate
OPERATION OF A TRANSISTOR
VSG > 0
n type operation
Positive gate bias attracts electrons into channel
Channel now becomes more conductive
More
electrons
Source
VSD
VSG
VSD

30. • Gate is insulated from the
body of FET so it is called
insulated gate FET(IGFET)
• Structurally there exits no
channel between source and
drain .
• Because a thin layer of P-
type substrate touching the
metal oxide film provides
channel for electrons and
hence acts like N-type
material.
N CHANNEL
ENHANCEMENT
MOSFET
MOSFET
ARCHITECTURE

31. • It consists of a lightly doped p type
substrate in to which two heavily
Doped n type material are diffused.
• The surface is coated with a layer of
silicon dioxide(Sio2 )
• Holes are cut through the Sio2 to
make contact with n-type blocks.
N CHANNEL
ENHANCEMENT
MOSFET
CONSTRUCTIO
N…….

32. WORKING OF THE ENHANCEMENT MOSFET
• Drain is made positive with
respect to the source and no
potential is applied to the gate as
shown in figure.
• The two n-blocks and p-type
substrate form back to back pn
junctions connected by the
Resistance of the p-type material.
• Both the junctions cannot be
forwarded at the Same time so
N CHANNEL
ENHANCEMENT
MOSFET

33. WORKING OF THE ENHANCEMENT MOSFET
• So MOSFET is cut off when
gate source voltage Is zero
• The gate is made positive
with respect to source
substrate as shown in figure
• A channel of electrons (n-
channel) is formed in
between the source and
drain regions.
N CHANNEL
ENHANCEMENT
MOSFET

34. • Consequently positive
charges appears on the gate
and negative charges
appears in the substrate
between the drain and
source.
• As VGS no. electrons in
the channel ID .
N CHANNEL
ENHANCEMENT
MOSFET

35. E-MOSFET
TRANSFER
CHARACTERISTI
C
• E-MOSFET does not have a
significant IDss parameter
• t there is ideally no drain
current until VGS reaches a
certain nonzero value
called the threshold
voltage, VGS(th).
• the curve starts at VGS(th)
rather than VGS(off)
• The equation for the E-
MOSFET transfer
characteristic curve is

36. OF THE E-TYPE
MOSFET
• 𝑉𝐺𝑆 is always positive
• As 𝑉𝐺𝑆 increases, 𝐼𝐷
increases
• As 𝑉𝐺𝑆 is kept constant and
𝑉𝐷𝑆 is increased, then 𝐼𝐷
saturates (𝐼𝐷𝑆𝑆 ) and the
saturation level, 𝑉𝐷𝑆𝑠𝑎𝑡 is
reached.
• 𝑉𝐷𝑆𝑠𝑎𝑡 can be calculated by
• 𝑉𝐷𝑠𝑎𝑡 = 𝑉𝐺𝑆 − 𝑉T

37. TRIODE REGION
A VOLTAGE-CONTROLLED RESISTOR @SMALL VDS
G
p
n+n+
metal
S DB
oxide
+-
+++
+++
- - - -
VGS1>Vt
p
n+n+
metal
S DB
oxide
+-
+++
+++
+++
- - - - - -
VGS2>VGS1
p
n+n+
metal
S DB
oxide
+-
+++
+++
+++
- - - - - - - - -
VGS3>VGS2
+++
ID
VDS
0.1 v
increasing
VGS
Increasing VGS puts more
charge in the channel, allowing
more drain current to flow
cut-off

38. SATURATION REGION
OCCURS AT LARGE VDS
p
n+n+
metal
source
S
gate
G
drain
D
body
B
oxide
+
-
+++
+++
+++
VDS large
As the drain voltage increases, the difference in
voltage between the drain and the gate becomes
smaller. At some point, the difference is too small
to maintain the channel near the drain  pinch-off

39. Saturation Region
occurs at large VDS
p
n+n+
metal
source
S
gate
G
drain
D
body
B
oxide
+
-
+++
+++
+++
VDS large
The saturation region is when the MOSFET
experiences pinch-off.
Pinch-off occurs when VG - VD is less than VT.

40. Saturation Region
occurs at large VDS
p
n+n+
metal
source
S
gate
G
drain
D
body
B
oxide
+
-
+++
+++
+++
VD>>Vs
VGS - VDS < VT or VGD <
VDS > VGS - VT
VT

41. SATURATION REGION
ONCE PINCH-OFF OCCURS, THERE IS NO
FURTHER INCREASE IN DRAIN CURRENT
ID
VDS
0.1 v
increasing
VGS
triode
saturation
VDS>VGS-VT
VDS<VGS-VT

42. CONSTRUCTION OF N
CHANNEL DEPLETION
MOSFET
• An n-type channel is obtained by
diffusion between N+ type
source and drain in an n-channel
MOSFET.
• In depletion MOSFET a lightly
doped n-type channel has been
introduced between to heavily
doped source& drain blocks,.
• •In depletion MOSFET a lightly
doped n-type channel has been
introduced between to heavily
doped source& drain blocks.

43. CONSTRUCTION OF P
CHANNEL DEPLETION
MOSFET
• An p-type channel is obtained by
diffusion between p+ type source
and drain in an p channel
MOSFET.
• In p-channel depletion MOSFETs
are made by using n-type
substrate and diffusing a lightly
doped p-type channel between
two heavily doped P-type source
& drain blocks

44. WORKING
• Negative gate
• When Vgs =0 electrons can flow freely from
source to drain through the conducting
channel. since a channel exists between drain &
source, Id flows even when Vgs =0
• With negative voltage a depletion MOSFET
behave like JFET.
• The action of negative voltage on gate is to
deplete the channel of free n-type charge
carriers so named as depletion MOSFET.
• The negative potential at the gate pressure
electrons toward the p -type substrate and
attract the holes for the p-type substrate
• When 𝑉𝐺𝑆 is reduced to 𝑉𝑃 (pinch off voltage),
then
N CHANNEL
DEPLETION MOSFE

45. DRAIN CHARACTERISTICS
• When the gate source voltage is zero
considerable drain current flows.
• When the gate is applied with negative
voltage, positive charge are induced in
the n channel through the SiO2 layer
of the gate capacitor.
• The conduction in n channel FET is due
to electrons i.e., the majority carriers
• Therefore the induced positive charges
make the n-channel less conductive.
• The voltage drop due to the drain
current causes the channel region
nearer to the drain to be more
depleted than the region due to the

46. The transfer characteristics are similar to the JFET
In Depletion Mode operation:
When VGS = 0V, ID = IDSS
When VGS < 0V, ID < IDSS
When VGS > 0V, ID > IDSS
The formula used to plot the Transfer Curve, is:
The transfer characteristics are similar to the JFET
In Depletion Mode operation:
When VGS = 0V, ID = IDSS
When VGS < 0V, ID < IDSS
When VGS > 0V, ID > IDSS
The formula used to plot the Transfer Curve, is:  
 
 
2
GS
D DSS
P
V
I = I 1-
V

47. The depletion MOSFET can also be
operated in enhancement mode
simply by applying a positive
voltage to the gate

48. DUAL-GATE MOSFETS
• The dual-gate MOSFET can be either a depletion or an enhancement
type.
The only difference is that it has two gates
Advantage of the dual-gate:
•Capacitance is reduced
• Used for Automatic gain control (AGC)

50. COMPARISON OF MOSFET AND JFET
• JFET Gate is not insulated
from the channel
• Channel and gate forms two
pn junctions
• There are only 3 leads
• Can be operated in depletion
mode only
• Input impedance is high
• MOSFET or IGFET is insulated
from the channel
• Channel and gate forms
parrallel plate capacitor.
• There are 4 leads
• Can be operated in both
depletion and enhancement
mode
• Input impedance is very high
JFET MOSFET

51. Summary Table