Using the Verilog HDL, SPI Protocol was implemented to transfer eight bits from a master to slave at eight different clock pulses.

1. Designing of FIFO and Serial Peripheral
Interface Protocol using Verilog HDL
By:
Jay R. Baxi
Intern
Tech Vulcan Solutions
India PVT LTD
jay.baxi@techvulcan.com
Guided By:
Vikas Billa
Engineer - VLSI
Tech Vulcan Solutions
India PVT LTD
vikas.billa@techvulcan.com
Faculty Guide:
Prof. Usha Mehta
Professor
Institute of Technology,
Nirma University
usha.mehta@nirmauni.ac.in

2. Flow of the Presentation
− Introduction
− Motivation
− Background
− FIFO
− Implementation: Design Block
− Stimulus
− Serial Peripheral Interface
− Data Trasmission
− Architecture
− Verilog Implementation
− Waveforms
− Dataflow
− Conclusion & Future Scope
− References

3. Introduction
− The main aim of the internship was to design an IP, using a
Verilog HDL. Once, the concepts of Verilog HDL were clarified,
certain small level examples like Vending Machine, simplified
parameterized comparator, were done to evaluate the
understanding.
− Once concluded, the Serial Peripheral Interface (SPI) Protocol
was undertaken, the understanding and concepts of which use
the First In First Out (FIFO) logic.
− Hence, prior to the completion of SPI, the development of FIFO
was done.

4. Motivation
− Three basic problems in any Architecture are to minimize area and
power requirements and increase the speed as much as possible.
− In this Architecture, due to reduced number of registers, the power
and area are considerably reduced. And due to relatively less
processing, the speed is increased.
− Serial ports are asynchronous.
− If two devices work on different clocks, the output maybe garbage.
− Furthermore, if the Slave reads data at wrong time, wrong bits will be
read.
− Complex and Costly hardware.
− Other Architectures defined have a complex implementation of large
number of registers, thereby reducing readability and understanding
of the protocol.

5. Background
− What is SPI?
− SPI stands for Serial Peripheral Interface. SPI is a protocol, a way to
send data from device to device in a serial fashion (bit by bit). This
protocol is used for things like SD memory cards, MP3 decoders,
memory devices and other high speed applications.
− It is Synchronous.
− It operates in Full Duplex mode.
− Communication mode: Master/Slave.
− Uses Clocks, Data lines and chip select signals to read/write data.
− SPI allows each of the slave devices to have an independent slave select
line, that allows any number of virtual slave connections. (Hardware
doesn’t allow though.)

6. First In First Out
−FIFOs are commonly used in electronic circuits for buffering
and flow control which is from hardware to software.
−In its hardware form, a FIFO primarily consists of a set of read
and write pointers, storage and control logic.
−Storage may be SRAM, flip-flops, latches or any other suitable
form of storage.
−For FIFOs of non-trivial size, a dual-port SRAM is usually used,
where one port is dedicated to writing and the other to reading.

7. First In First Out
−A synchronous FIFO is a FIFO where the same clock is used for
both reading and writing. An asynchronous FIFO uses different
clocks for reading and writing.
−Examples of FIFO status flags include: full, empty, almost full,
almost empty, etc.
−A hardware FIFO is used for synchronization purposes. It is
often implemented as a circular queue, and thus has two
pointers:
− Read Pointer/Read Address Register
− Write Pointer/Write Address Register

8. First In First Out
− FIFO Empty:
−When the Read Address Register equals the Write Address Register, the
FIFO is termed as EMPTY.
− FIFO Full:
− When the read address LSBs equal the write address LSBs and the
extra MSBs are different, the FIFO is full.

9. FIFO : Design Block
module syn_fifo #(
parameter D_WIDTH = 8,
ADDR_WIDTH = 3,
DEPTH = 1 << ADDR_WIDTH
)
(
input clk ,
input rst ,
input [D_WIDTH - 1 : 0] wdata ,
input wr_en ,
output full ,
input rd_en ,
output [D_WIDTH - 1 : 0] rdata ,
output empty
);
reg [D_WIDTH - 1 : 0] mem [0 : DEPTH - 1];
reg [ADDR_WIDTH : 0] rd_ptr ;
reg [ADDR_WIDTH : 0] wr_ptr ;
wire [ADDR_WIDTH : 0] rd_addr ;
wire [ADDR_WIDTH : 0] wr_addr ;
assign full = (rd_ptr ==
{~wr_ptr[ADDR_WIDTH],wr_ptr[ADDR_WIDTH - 1 : 0]}) ;
assign empty = (rd_ptr == wr_ptr) ;
assign rd_addr = rd_ptr[ADDR_WIDTH - 1 : 0]
;
assign wr_addr = wr_ptr[ADDR_WIDTH - 1 : 0]
;
assign rdata = mem[rd_addr]

10. FIFO : Design Block
//Update Write Pointer
always @(posedge clk , negedge rst)
begin
if(!rst)
wr_ptr <= 0;
else if (! full && wr_en)
wr_ptr <= wr_ptr + 1;
end
//Write Operation
always @(posedge clk)
begin
if(! full && wr_en)
mem[wr_addr] = wdata;
end
//Update Read Pointer
always @(posedge clk, negedge rst)
begin
if(!rst)
rd_ptr <= 0;
else if (! empty && rd_en)
rd_ptr <= rd_ptr + 1;
end
endmodule

11. FIFO : Test Bench
`include "fifo_115.v"
module stimulus;
wire [7:0] rdata ;
wire full ;
wire empty ;
reg [7:0] wdata ;
reg clk ;
reg wr_en ;
reg rd_en ;
reg rst ;
syn_fifo SF(
.rdata (rdata ),
.full (full ),
.empty (empty ),
.wdata (wdata ),
.clk (clk ),
.wr_en (wr_en ),
.rd_en (rd_en ),
.rst (rst )
);

12. FIFO : Test Bench
initial
begin
clk = 0;
forever #5 clk = ~clk;
end
Initial begin
rst = 1'b1;
wr_en = 1'b0;
rd_en = 1'b0;
#10 rst = 1'b0;
#10 wr_en = 1'b1;
#100 wr_en = 1'b0;
#150 rd_en = 1'b1;
end
always @(posedge clk)
begin
if(rst)
wdata <= 0;
else if (!full && wr_en)
wdata <= wdata + 1;
end
endmodule

13. FIFO : Waveforms

14. SPI Protocol
−SPI follows four logic signals [1]
− 1.) SCLK: Serial Clock
− 2.) MOSI: Master Output/Slave Input
− 3.) MISO: Master Input/Slave Output
− 4.) SS(Active Low): Slave Select
− Active Low: The slave is activated only when it is provided with low
logic level/“0” logic level.

15. SPI Protocol
Slave1 Slave2 SlaveN
Interrupt
Master
< < <
< < <
> > >
MISO: Master In – Slave Out
MOSI: Master Out – Slave In
SS: Slave Select (Active Low)
>
>>
>
> >
Clock
> > >
^

16. SPI Protocol
Memory
Memory
SCK
MOSI
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
MISO
MASTER SLAVE

17. SPI Protocol
−Data Transmission:
− The master first configures the clock with a frequency less than or
equal to that of the slave which is obtained from the data sheet of the
slave devices. (usually in MHz)
− The desired Slave Select is turned on by passing the logic “0” through
it.
− There can be delays, if explicitly mentioned.
− During each clock cycle, a full duplex communication occurs
The master sends a bit to the MOSI line, the slave reads it.
The slave sends a bit to the MISO line, the master reads it.

18. SPI Protocol
−Data Transmission(cont.):
− Transmission includes two shift register at the two ends, connected in
a RING topology.
− Data is shifted out of the MSB (leftmost bit) and taken in through the
LSB (rightmost bit).
− Transmission can occur at any number of clock cycles. Usually, once
the data is transmitted, the master stops the toggling of the clock. It
then deselects the slave.
− Every slave on the bus that hasn't been activated using its chip select
line must disregard the input clock and MOSI signals, and must not
drive MISO. The master must select only one slave at a time.

19. SPI Protocol
Courtesy: https://encrypted-tbn0.gstatic.com/images?q=tbn:ANd9GcRmApQqMDI7xBkXRAstEOI-
32b2RnQR4VthEd1snQkw5vATpDzI

20. SPI Protocol
Courtesy: http://www.ermicro.com/blog/wp-content/uploads/2009/06/avrspi_03.jpg

21. SPI Protocol : Architecture
−Architecture:
− As mentioned the Architecture uses two registers of 32 bits each.
− The data is transferred in fixed 8-bit form.
− The data is divided in form of 8 bits, he remaining bits left towards the
end are appended with ‘0’s at the MSB location to make it a multiple of
8.
− The three registers used and their functioning is mentioned as below:
− 1.) Global Control Register (SPIGCR)
− 2.) Transmit Receive Register (TX-RXDATA)

22. SPI Protocol : Architecture
1.) SPI – Global Control Register (SPIGCR):
31 30 29 28 27 26 25 24 23 16
RST ENA OVRN TBUF RBUF INTR CPOL CPHA
1 bit 1 bit 1 bit 1 bit 1 bit 1 bit 1 bit 1 bit
15 14 13 12 10 9 7 6 4 3 0
M/S MOSI MISO SETUP DELAY HOLD DELAY TIMER CHARLEN
1 bit 1 bit 1 bit 3 bits 3 bits 3 bits 4 bits
−RESET [31]:
RESERVED
8 bits
− The reset bit when set to 1 for at least one clock cycle, acts as a refresh
button. All the buffers will be emptied. All the flags will be set to their
default state. For the operation to proceed it is important that the reset bit
become 0.

23. SPI Protocol : Architecture
− ENABLE [30]:
− The Enable is set to 1, to ensure the functioning of the protocol. It can be set only when the RESET
bit is set to 0.
− When set to 0, no data transmission occurs.
− OVERRUN [29]:
− The Overrun bit is set to 1, when data is overrun. That is the next read operation takes place before
the previous bit is written. This is one of the methods to have the flow control, given the fact that
there is no external flow control provided by the SPI protocol, for itself.
− TBUF [28]:
− This bit when set to 1, indicates that TBUF is full and it is ready to send the data to the receiver.
− This bit when set to 0, indicates that TBUF is empty and more data can be loaded, (if any), before
sending it to the receiver
− RBUF [27]:
− This bit when set to 1, indicates that RBUF is full and it is ready to receive the data from the
receiver.
− This bit when set to 0, indicates that RBUF is empty and more data can be loaded, from the
transmitter.

24. SPI Protocol : Architecture
−INTERRUPT [26]:
− When an external interrupt register sends an interrupt signal this bit is
turned on. This indicates that the current transmission should be
paused and continued only after the interrupt bit turns low.
−CPOL | CPHA [25-24]:
− The clock polarity and Clock Phase gives the user a choice of four
different options giving him a choice as to when does he want the
receiver to sample the data. The following table briefly explains the
working of the bits.

25. SPI Protocol : Architecture
CPOL CPHA Description
0 0 Data is output on the falling edge of the SCK. Input data is latched on the
falling edge.
0 1 Data is output one half-cycle before the first rising edge of SCK and on
subsequent falling edges. Input data is latched on the rising edge of SCK.
1 0 Data is output on the falling edge of SCK. Input data is latched on the rising
edge.
1 1 Data is output one half-cycle before the first falling edge of SCK and on
subsequent rising edges. Input data is latched on the falling edge of SCK.

26. SPI Protocol : Architecture
1.) Phase = 0, Polarity = 0;

27. SPI Protocol : Architecture
2.) Phase = 1, Polarity = 0;

28. SPI Protocol : Architecture
3.) Phase = 0, Polarity = 1;

29. SPI Protocol : Architecture
4.) Phase = 1, Polarity = 1;

30. SPI Protocol : Architecture
−RESERVED [23-16]:
− These are reserved bits, when read it gives 1 and produces no output in case
of write.
−M/S [15]: The Master mode of the device is active high. While the
Slave mode is active low.
− If 1 is selected it is in Master mode.
− If it is set to 0, it is in Slave mode.
−MISO [14]: If the data is sent to the MISO line it is set to 1. For
Master register this bit is set to 0, for Slave mode it is set to 1.
−MOSI [13]: If the data is sent to the MOSI line it is set to 1. For
Master register this bit is set to 1, for Slave mode it is set to 0.

31. SPI Protocol : Architecture
−SETUP_DELAY [12-10] and HOLD_DELAY [9-7]:
− There may be a case when the clock takes some delay before coming to
a stable high state. This is when the TIMER will calculate the delay and
store the value with an appropriate value in the SETUP_DELAY
register.
− For cases in which, the clock has to hold a certain value before coming
to a low state, the timer calculates the delay and stores it in the
HOLD_DELAY.
−TIMER [6-4]: Time out Operations
−CHARLEN [3-0]: The 4-bit CHARLEN register stores the length
of the data that is to be sent in bit format.

32. SPI Protocol : Architecture
2.) SPI – Transmit Receive Register(TX-RXDATA):
31 16
15 0
TXDATA (15-8)
8 bits
−RESERVED [31-16]:
Reserved (31-16)
RXDATA (8-0)
8 bits
16 bits
− These bits are reserved, produce 1 on read and 0 on output.

33. SPI Protocol : Architecture
−TXDATA [15-8]:
− When working in a Master mode, the TXDATA transmits the data to
the Slave by this register through the MOSI line.
− When working in a Slave mode, the TXDATA transmits the data back
to the Master by this register through the MISO line.
−RXDATA [7:0]:
− When working in a Master mode, the RXDATA receives the data from
the Slave on this register through the MISO line.
− When working in a Slave mode, the RXDATA receives the data from
the master on this register through the MOSI line.

34. SPI Protocol : Verilog Implementation
module master(
input RST ,
input ENA ,
input INTR ,
input MISO ,
output reg MOSI ,
output reg CSbar ,
output reg SCK
);
reg [7:0] data_m ;
reg [7:0] data_init;
reg temp ;
initial
begin
SCK = 1'b0;
forever #10 SCK = ~SCK;
end
initial
begin
data_m = 8'b10101101;
data_init = data_m ;
$display("Initial Data at Master: %b",data_m);
end

35. SPI Protocol : Verilog Implementation
always@(posedge SCK, negedge RST)
begin
if(RST)
data_m = data_init ;
else if (ENA && !INTR)
begin
MOSI = data_m[7] ;
temp = MISO ;
data_m = data_m << 1 ;
data_m = {data_m[7:1],temp};
$display("Data at Master: %b",data_m);
end
end
always @(posedge SCK, negedge RST)
begin
CSbar = 1'b0 ;
if(INTR)
$display("Interrupt is Processing") ;
end
endmodule

36. SPI Protocol : Verilog Implementation
module slave(
input RST ,
input ENA ,
input SCK ,
input INTR ,
input MOSI ,
output reg MISO ,
input CSbar
);
reg [7:0] data_s ;
reg [7:0] data_init;
reg temp ;
integer count = 0 ;
always@(posedge SCK, negedge RST) begin
if(!CSbar) begin
if(RST)
data_s = data_init ;
else if (ENA && !INTR) begin
MISO = data_s[7] ;
temp = MOSI ;
data_s = data_s << 1 ;
data_s = {data_s[7:1],temp};
count = count + 1 ;
if(count == 10)
$stop;
$display("Data at Slave: %b",data_s);
end
end
end

37. SPI Protocol : Verilog Implementation
always @(posedge SCK, negedge RST)
begin
if(INTR)
$display("Interrupt is Processing") ;
end
endmodule
module stimulus;
reg RST ;
reg ENA ;
reg INTR ;
wire MISO ;
wire MOSI ;
wire CSbar ;
wire SCK ;

38. SPI Protocol : Verilog Implementation
initial
begin
RST = 1'b1;
ENA = 1'b0;
INTR = 1'b0;
#5 RST = 1'b0;
#2 ENA = 1'b1;
#12 RST = 1'b1;
#6 ENA = 1'b0;
#4 RST = 1'b0;
#8 ENA = 1'b1;
#80 INTR = 1'b1;
#6 INTR = 1'b0;
end
master M(
.RST (RST ),
.ENA (ENA ),
.SCK (SCK ),
.INTR (INTR ),
.MOSI (MOSI ),
.MISO (MISO ),
.CSbar(CSbar)
);

39. SPI Protocol : Verilog Implementation
slave S(
.RST (RST ),
.ENA (ENA ),
.SCK (SCK ),
.INTR (INTR ),
.MOSI (MOSI ),
.MISO (MISO ),
.CSbar(CSbar)
);
endmodule

40. SPI Protocol : Waveforms

41. SPI Protocol : Dataflow

42. Conclusion & Future Scope
−SPI offers reduced overhead as compared to Serial
and I2C protocols, with a flaw of more number of pins
required.
−However, the mere advantage of unlimited number of
theoretical slave devices eclipses the fact.
−The data transfer is relatively simple, with extremely
simple hardware.
−It is one of the fastest synchronous protocol.

43. References
[1] www.wikipedia.org/wiki/Serial_Peripheral_Interface_Bus
(As on March 12, 2014)
[2] https://learn.sparkfun.com/tutorials/serial-peripheral-interface-spi/all
(As on March 14, 2014)
[3] http://tronixstuff.com/2011/05/13/tutorial-arduino-and-the-spi-bus/
(As on March 17, 2014)
[4] https://learn.sparkfun.com/tutorials/i2c
(As on March 17, 2014)
[5] KeystoneArchitecture – Serial Peripheral Interface (SPI) Texas Instruments.
Literature Number: SPRUGP2A, March 2012.
[6] Serial Peripheral Interface – User’s Guide, Texas Instruments Literature
Number: SPRUEM2A, October 2007.