This document discusses the differences between tasks and functions in Verilog. Tasks can contain timing statements while functions cannot. Tasks can have multiple input/output arguments but functions can only have one input argument and do not return output. Functions execute in zero time while tasks can execute in non-zero time. The document also provides examples of tasks like bitwise operators and asymmetric sequence generators. It discusses automatic tasks that prevent issues with shared variables. Functions are used for combinational logic and examples given are parity calculation and shifting. Recursive functions and constant/signed functions are also explained.

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Notes: Verilog Part 5
8 CHAPTER 8:
8.1 DIFFERENCE BETWEEN FUNCTION AND TASKS
Functions
A function can enable another function but not
another task.
Function always executes in 0 simulation time.
Functions must not contain any delay, event or
timing control statements.
Functions must have at least one input
argument. They can have more than one
arguments.
Functions always return a single value. They
cannot have output or inout arguments.
Tasks
A task can enable another task as well as a
function.
Tasks may execute in non-zero simulation time.
Tasks may contain any delay, event or timing
control statements.
Tasks may have zero arguments of type input,
output or inout.
Tasks do not return with a value, but can pass
multiple values through output and inout
arguments.
 Both Tasks and functions must be defined in a module and are local to the module.
 Tasks are useful for common Verilog problems that contain any event, delay, timing or
multiple argument constructs.
 Functions are used in purely combinational circuits that are to be executed in zero
simulation time.
 Tasks or Functions cannot have wires. They contain behavioural statements only.
 They do not contain initial or always blocks but can be called from always, initial or other
tasks and functions.
8.2 TASKS
 They are used with the keywords task and endtask. They are used if any one of the following
condition is true for the procedure.
 There are delay, timing or event control constructs in the procedure.
 The procedure has zero or more than one output arguments.
 The procedure has no input arguments.
 Task declaration and task invocation syntax is given as Syntax.
 Examples
 TASK: Bitwise Oper Module Operator
 Assymetric Sequence Generator
 Automatic Tasks:
 Tasks are normally static in nature. Hence when task is called
concurrently at two places in a code, there are chances that the task
calls will operate on the same task variables.
 This results in incorrect results.
 Hence we use automatic task. Here both the task calls are given
dynamic variables upon invocation.
Notes: Verilog Part 5
Prepared By: Jay Baxi

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

Thus because of these independent copies of variables correct
results are obtained.
For example: Automatic (Re-entrant) Tasks.
8.3 FUNCTIONS
 Functions are declared within keywords function and endfunction.
 They are used when all of the following condition are true for procedure:
 There are no delay, timing or event control constructs in the
procedure.
 The procedure returns a single value.
 There is at least one input argument.
 There are no output or inout arguments.
 There are no nonblocking assignments.
8.3.1
Function Declaration and Invocation
 The syntax for the function declaration and invocation are as
Function Declaration and Invocation.
 When a function is declared a register name function_identifier is
implicitly formed.
 The output is passed by setting the value of register
function_identifier.
 The function is invoked by specifying the name and argument. The
return value is placed where the function was invoked.
 Range_or_type specifies the width of the internal register. If it is not
defined, the default bit width is 1.
8.3.2 Function Examples
 Parity Calculation
 Left/Right Shifter
8.3.3
Recursive Functions
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8.3.4
If a function is concurrently called from two different locations, the
result is non deterministic, because both calls operate on same
variables.
Verilog provides automatic to declare a recursive function where all
function declarations are dynamically allocated for each call.
They cannot be accessed by hierarchical references, however, they
can be invoked.
An example of Recursive Function: Factorial
Constant and Signed Functions
 A constant function is a normal Verilog function with certain
restrictions.
 It can be used to reference complex values and can be used instead
of constants.
 Signed Functions allow signed operations to be performed on the
function return values. It uses the keyword signed.
Notes: Verilog Part 5
Prepared By: Jay Baxi