Fundamentals of HDL (first 4 chapters only) - Godse

A. P. Goclse
D.A.Goclse
Technical Publications Punes

Fundamentals of HDL
ISBN 9788184314052
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Table of Contents
1.1WhyHDL?........................................................................................... 1-1
1.2 A Brief History of HDL ......................................................................... 1 - 2
1.2.1 A Brief History of VHDL . . .. . .... . . .. . ....... . . . ..... . . . . .. . .. . .. . ... . . . ..... 1- 2
1.2.2 A Brief History of Verilog HDL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . 1- 3
1.3 Structure of the HDL Module ............................................................... 1 - 3
1.3.1 Structure of the VHDL Module. . . . . . . . . . . . . . . .. . . . .. . . . . . . . . . . . . . . . . . .. .. . . . . . . 1- 3
1.3.1.1Package. . 1-4
1.3.1.2Entity . . . . . 1 -5
1.3.1.3Architecture . ·. 1- 7
1.3.1.4Configuration. . 1-8
1.3.2 Structure of the Verilog Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1- 9
1.4 Operators ........................................................................................... 1 - 10
1.4.1 Operators in VHDL. . . . . . . . . . . .• . .. . .. . . . . .. . .. . . . . . .. .. . . . . . . .. . . . . . . .. .. . . 1- 1O
1.4.1.1 Logical Operators . 1- 11
1.4.1.2 Relational Operators . . . 1- 12
1.4.1.3ArithmeticOperators . . . 1-13
1.4.1.4 Shift and Rotate Operators . 1-14
1.4.1.SOperatorPrecedence . 1- 14
1.4.2 OperatorsinVerilog HDL..... . . . ............ . .... . ....... . . . .. . . . . .. . ...... . 1-15
1.4.2.1Boolean Logical Operators. . . . 1-15
1.4.2.2 Unary Reduction Logical Operators 1-16
1.4.2.3 Bitwise Logical Operators . 1-16
1.4.2.4 Relational Operators . . 1 - 16
1.4.2.5 Binary Arithmetic Operators 1- 17
1.4.2.6Unary Arithmetic Operators. 1- 17
1.4.2.7 Other Operators . . 1- 17
1.4.2.8 OperatorPrecedence. 1- 18

1.5 Data Types......................................................................................... 1 - 18
1.5.1 VHDL Data Types .... ....... . .. .. .. . .. ... .. . . ... . . . •. . . . . . .......... .. .. .. 1-19
1.5.1.1 Scalar Types . . 1-19
1.5.1.2Comoostte Types. 1-22
1.5.1.3AccessTypes . 1-25
1.5.1.4FileType . . .. 1-25
1.5.1.50therTypes. . . 1- 26
1.5.2Verilog Data Type.. . . . . .. . .. ...... .. .. ..... ............... . . ..... . ......... 1- 27
1.5.2.1 Nets (Wire) and Registers . . . . . . 1-27
1.5.2.2Abstract Data Types :integer,real time . . . . . . . . . . . . . . . . . . . 1-28
1.5.2.3 Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1- 29
1.6 Styles or Types of Descriptions ......................................................... 1 - 29
1.6.1Behavioral Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... . . .. . 1- 30
1.6.2 Dataflow Design Elements.. .. .. . .. .. .. .. .. .............. .................... 1- 31
1.6.3 Structural Design Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1- 32
1.6.4 Switch-Level Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1- 33
1.6.5 Mixed-Type Descriptions . .. .. .. ...... .. ..... .... ...... ...... ... .. . .. . .. . .. .. 1- 34
1.6.6 Mixed Language Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1- 35
1.7 Simulation and Synthesis................................................................... 1 - 36
1.7.1 Synthesis . .. . . .... . .. .... .. . .. . .. .. .. .. . . . .. .. .. . .. ...... ... .. .. .. . . .. ... 1- 36
1.7.2 Simulation. . . .. .......... .. . ..... ..... ...... . .. . ... ............. . . .. . ... . . 1- 37
1.8 Brief Comparison of VHDL and Verilog ............................................. 1 - 38
1.9 Summary of Operators in VHDL and Verilog ..................................... 1 - 39
Review Questions .................................................................................... 1 - 41
2.1 High Lights of Data-Flow Description................................................... 2 - 1
2.2 Structure of the Data-Flow Description ................................................ 2 - 1
2.2.1 Signal Declaration and Assignment Statement .. .. . .. . .... .......... ....... .... .. . 2- 2
2.2.2 Execution ofAssignment Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2- 2
2.2.3 Constant Declaration and Assignment Statement .. .. . . : . . . . . . . . . . . . . . . . . . . . . . . . . . . 2- 4
2.3 Data Type - Vectors ............................................................................. 2 - 8
Review Questions ....................................................................................2 - 26
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3.1 Behavioral Description Highlights ........................................................ 3 - 1
3.2 Structure of the HDL Behavioral Description ....................................... 3 - 1
3.3 The VHDL Variable Assignment Statement......................................... 3 - 4
3.4 Sequential Statements......................................................................... 3 - 4
3.4.1 IF Statement. . .......... . .... . .. ................. . .................... . .... 3- 4
3.4.2Signal and VariableAssignment ...... .. . . . ... . .. . .. . ........ . . . . ... . ...... .. . 3- 10
3.4.3 Case Statement . . ...... . . .. ............. . .. . . .. . ..... . . ........ . . ......... 3-13
3.4.4 Comparison between CASE and IF Statement ... . .... . ..... . . ........... . ...... . 3- 14
3.4.4.1Verilog Casex and Casez . . . . . . . . . . . . . . . . . . . . . . . . 3- 20
3.4.5 Loop Statement . .......... . . . . . . . . .. .. . ... . .. . . . ........... . ............. . 3- 21
3.4.5.1For-LoopStatement. . 3- 21
3.4.5.2 While-Loop Statement. 3-23
3.4.5.3Verilog Repeat. . . 3-23
3.4.5.4 Verilog Forever . . . 3-24
3.4.5.5VHDL Next and Exit. . 3- 24
Review Questions ................................................................................... 3 - 35
4.1 Highlights of Structural Description ....................... .............................. 4 - 1
4.2 Organization of the Structural Description .......................................... 4 - 1
4.3 Binding ................................................................................................. 4 - 4
4.3.1 Binding between Entity and Architecture in VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . 4- 4
4.3.2 Binding between Entity and Component in VHDL . . . . . . . . . . •. . . . . . . . . . . . . . . . .•. . . . . 4- 5
4.3.3 Binding between Library and Modulein VHDL. ................. . .... . ............. 4- 6
4.3.4 Binding between TwoModules in Verilog . . .. . . .. . .. .... .. . . .. . .. . .. . .. . ........ . 4- 8
4.4 State Machine .................................................................................... 4 - 36
4.4.1 Types of Sequential Circuits.... . . . .. .. . . .. . . . . .. . .... .. . .. . . .... .. . . ..... . . . . 4- 37
4.4.1.1 Moore Model . . . . . . . . 4- 37
4.4.1 .2Mealy Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4- 39
4.4.1.3Moore Vs Mealy Circuit Modets . . . . . . . . . . . . . . . . . . . . . . 4-40
4.4.2State Machine Notations . ......... ..... ... .. . . . . ...... . .. ..... .. . ..... . ..... 4- 40
4 4 2 1 State and State Variable 4-40
4422Present State and Next State . . . . . . . . . . . . . . . . . . . . 4-40

4.4.2.3 State Transition Diagram
4.4.2.4 State Table . . . . . .
4-41
4-42
4.4.2.5 Transition Table . 4-43
4.5 Design Equations and Circuit Diagram ............................................. 4 - 43
4.6 Generate (HDL), Generic (VHDL), and Parameter (Verilog) ............ 4 - 53
Review Questions .................................................................................... 4 - 64
5.1 Highlights of Procedures, Tasks and Functions .................................. 5 - 1
5.2 Procedures and Tasks ......................................................................... 5 - 1
5.2.1 Procedures (VHDL) . .. ....·..... . . ..... . ... .... ... .... ........ .. ... ..... ..... 5 - 2
5.2.2Tasks (Verilog) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5- 3
5.2.3 Examples of Procedures and Tasks....... . .. . ... . ... . .. .. . . . ..... ........ . ..... 5 - 4
5.3 Functions ........................................................................................... 5 - 21
5.3.1 VHDL Functions.. .. . . . .... ..... . ......................... ........ ..... .. .. 5-22
5.3.2 Verilog Functions .... ...................................................... 5 •22
5.3.3 Function Examples. .. .. . . .. . .. . ... . .. .. .. .. .. .. .. . .. . .. ..... . .. ............ 5 - 23
5.4 Advanced HDL Descriptions : File Processing .................................. 5 - 27
5.4.1VHDL FileProcessing .. ........................................ ............ 5 - 27
5.4.2 Verilog File Processing...... .. ...... . .. . .. .. ..... .. .. . .. .. ......... . .. . .. .. . 5- 30
5.5 Examples of File Processing.............................................................. 5 - 33
5.5.1 Examples of VHDL File Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 - 33
5.5.2 Example of Verilog FileProcessing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 · 40
Review Questions .............................................................................,,..,, 5 - 41
6.1 Why Mixed-Type Description? ............................................................ 6 - 1
6.2 VHDL User-Defined Types .................................................................. 6 - 1
6.3 VHDL Package .................................................................................... 6 - 2
6.3.1 Implementation of Arrays .. . .. . ... . .. .. .. .. .. . ... . .. . .. . .. .... . ..... .. . . ... . .. 6 - 4
6.3.1.1 Single-Dimensional Arrays in VHDL . . . 6-4
6.3.1.2 Single- Dimensional Arrays inVerilog . . . . . . . . . . . . . . . . . . . . 6-5
6.3.2.3 Two-Dimensional Arrays. . . . . . . . . . . . . . . . . . . . . . . . . 6-11

6.4 Mixed-Type Description Examples .................................................... 6 - 12
Review Questions ..................................................................,, 6 - 24
7.1 Highlights of Mixed-Language Description .......................................... 7 - 1
7.2 How to Invoke One Language from the Other ..................................... 7 - 1
7.2.1 Invoking aVHDL Entity fromaVerilog Module.. .. .. . . . ...... •. .•. . •.. •... .... ... . 7. 1
7.2.2Invoking aVerilog ModulefromaVHDLModule .. . . ..... . ..... ... ... . ...... ... . .. 7• 3
7.3 Mixed-Language Description Examples .............................................. 7 - 4
7.4 Limitations of Mixed Language Description ....................................... 7 - 16
Review Questions .................................... ..,,.................,,...... .... . 7 - 17
8.1 Highlights of Synthesis......................................................................... 8 - 1
8.2 Synthesis Information from Entity and Module .................................... 8 - 3
8.2.1Synthesis Information fromEntity (VHDL) . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . 8•3
8.2.2Verilog SynthesisInformationfrom ModuleInputs/Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . 8•9
8.3 Mapping Process and always in the Hardware Domain .................... 8 - 11
8.3.1Mappingthe Signal-Assignment Statement toGate-level. . . . . . . . . . . . . . . . . . . . . . . . . . . 8• 11
8.3.2MappingtheVariable-Assignment Statement to Gate-Level Synthesis. . . . . . . . . . . . . . . . . 8• 15
8.3.3 Mapping Logical Operators . . . . . . . .. . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . .. . . . . 8· 16
8.3.4 MappingtheIFStatement .. .. . . ... . •.. •. . . ... .• .. ... •. .•.. •.. •. . . . .. . . . . . . .. 8-19
8.3.5Mapping the Case Statement. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . 8•31
8.3.6Mapping the Loop Statement.. . ... ... . ... . ... . ... ..... . ........ . . . . . ... . . . . . . 8•37
8.3.7 Mapping Procedure or Task.. ... ... . . . . . . .. . . . . ... . . . ... . . . ... ... .. .. .... . ... 8•38
8.3.8 MappingtheFunctionStatement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8•40
Review Questions ................................................................................... 8 - 43
A 1 VHDL Standards ... ... .,,............. .,, .... .......................... ...,, .. .. A - 1
A.2 Predefined Packages .......................................................................... A - 2
A.2.1Standard . . . .... . .. . .. . . . . ... . ... . . ... . . . ...... ... . .. . ..... . .. . . ... ... . . . . A· 2
A.2.2TEXTIO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A•4
A.2.3STD LOGIC 1164 .. .. . . . . . .. . ... . .. . .. . . .. .... ... ... .. ... . . .. .. ....... . .. A· 5

A.2.4 NUMERIC_BIT. . . .. . ... .. .•... .. . . ...... •. .. ........ . .......... •.. •.. ... . . A- 8
A.2.5 NUMERIC STD.. . .. ...... . .. ......... ....... .... . .. ...... . .. ........... .. A-1 1
A.2.6 MATH REAL. .. .......... .. . . .. .. .. . ....... ...... . ........ .. . . . . ... . .. ... A-15
A.2.7 MATH_COMPLEX..... . . ... ................... . ........ ............... ... . A-16
B.1 Decoders in VHDL ............................................................................. B - 1
B 2 Encoders in VHDL. ....... ........ . .. .. .. ............. . B - 5
B.3 Three State Devices in VHDL ............................................................. B - 9
B.4 Multiplexers in VHDL......................................................................... B - 12
B.5 Parity Circuits in VHDL.......................................,.............................. B - 15
B.6 Comparators in VHDL ....................................................................... B - 16
B 7 Adders and Subtracters in VHDL ...................................................... B - 18
B.8 ALU in VHDL..................................................................................... B - 21
B.9 Multipliers in VHDL.....................,...................................................... B - 22
B.1OVHDL Code for Barrel Shifter.......................................................... B - 23
B.10.1Barrel Shifter . . . . . . . . .. . .. . . .. .. .. . .. . .. . .. . . . . . . . . . . . . . . . .. . .. .. . . .. . . . . B- 23
B.10.2 Barrel Shifter using VHDL ... . .. . ... . . .. ...... . . .. .. ... . ... ..... . , . .. ....... B• 25
B.11 VHDL Code for Simple Floating - Point Encoder ........................... B - 26
B.11.1Simple Floating-Point Encoder . . . . .. . . . . .. . . .. . . . . . . . . . . . .. . . . . . . .. . . . .. . . .. B- 26
B.11.2 Simple Floating-Point Encoder in VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B•28
B.12 VHDL Code for Cascadina Comp.:.rators ........................................ B - 28
8.12.1 Cascading Comparators . . . . . . . .. .. .. . .. . . .. . . . .. . . . . . . . . . .. . . . . . . .. .. . . .. . B- 28
B.12.2Cascading Compa1ators in VHDL ....... . ... .. . . . .. .. . . . . .. . .. .. .. . .. . ... .... B. 30
B.13 VHDL Code for Dual Priority Encoder............................................. B - 30
B.14 VHDL code for Ones Counter........................................................ B - 33
B14 1Behavioral VHDL Code for a32-bit Ones Counter . . 8-33
8.14.2Structural VHDL Code for a32-bit Ones Counter . .. . ... . . ...... . .. . .. .. .. . .. .. .. B- 34
B.15 VHDL Code for Binary to Gray Code Converter ............................. B - 38
B.16 VHDL Code for Gray to Binary Code Converter ............................. B - 40
B.17 VHDL Code for Latch ...................................................................... B - 42
B.18 VHDL Code for Flip-Flop................................................................. B - 43
B.18.1VHDL Code for aDFlip-Flop using IF-THEN Statement . . . . . . . . . . . . . . . . . . . . . . . . . . B• 43

B.18.2 VHDL Code for a DFlip-Flop using WAIT-UNTIL Statement . . .................. .. . B- 44
B.18.3 VHDL Code for a DFlip-Flop with Asynchronous ReseliClear . . . . . . . . . . . . . . . . . . . . . . B- 45
B.18.4 VHDL Code fora DFlip-Flop with Synchronous ReseVClear. . . . . . . . . . . . . . . . . . . . . . . B- 45
8.18.5 VHDL code for a DFF with anegative-edge clock and asynchronous dear.. . ... . .. . .. B- 46
8.18.6DFF with Positive-Edge Clock and Synchronous Set ... . . . .... ... ... .. . . ... . .. ... B- 47
8.18.7 DFF with Positive-Edge Clock and Clock Enable . .. .. . .. .. . .. .. . .. .. ... ... .. . .. . B- 48
B.18.8VHDL Code for JK Flip-Flop .. . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . .. . . . B- 48
B.12 VHDL Code for Registers................................................................ B - 49
8.19.1VHDL Code for aFour-bit Register ... ... . ...... . .. . ....... .. .. .. . . ... . .. .. . .. B-49
8.19.2 4-bit Register with Positive-Edge Clock,Asynchronous Set andClock Enable . . . . . . . . . B- 50
8.19.3 VHDL Code for an N-bit Register . .. . ... . .. . .. . ... . .. . ...... . . .... ... . ... . . .. B- 51
8.19.4 VHDL Code for a Shift Register. . ... . ... •.. . ..• . ........ . ...•..•..• .. . . .. . . .. 8 - 52
B.19.4.1Using Sequential Statements . . . . . . B-52
B.19.4.2 Hierarchical Code for a4-bit Shift Register . . . . . . . . . . B-53
B.19.4.3 VHDL Code for an n-bit Left-to-Right Shift Register. . . .... B-54
B.19.4.4 VHDL Codefor aLeft-to-Right Shift Register withan Enable Input. B-55
8.19.5 VHDL Code for a 4-bit Parallel Access Shift Register ... . . . . . . . ............ . .. . ... B- 55
B.19.5.1Using Sequential Statements . . . . . . . . . . . . B- 55
B.19.5.2 Hierarchical Code for a4-bit Parallel Access Shift Register. . . . . . . . . . . B- 57
8.19.6 8-bit Shift-Left Register with Positive-Edge Clock.
Asynchronous Parallel Load, SeriallN, and Serial OUT. .. . . . . .. . .. . . . . . . . . . . . . . . . B- 60
B.19.7 8-bit Shift-Left Registe:r with Positive-Edge Clock.
Synchronous Parallel Load, Serial IN. and Serial OUT . .. .. .. . .. .. ...... . . ..... ... B- 61
8.19.8 8-bit Shift-Left/Shift-Right Register with Positive-Edge Clock, Serial IN, and Parallel OUT B- 62
B.20 VHDL Code for a Counter ............................................................... B - 62
B.20.1 VHDL Code for a Four-bit Up Counter . . . .. .. .. . .. . ..... • . ...•..•. .. .. •... .. .. B- 62
8.20.2 VHDL Code for a 4-bit Up Counter using Integer Signals . .. . • . . ... .. •..... •.. • . ... B- 63
B.20.3 VHDL Code fora 4-bit Down Counter...... . .. .. . . .. . .. .. . .... .......... .. ... . B- 64
8.20.4 VHDL Code for a 3-bit Asynchronous Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B -65
B.20.5 VHDL Code for Asynchronous Counter with GLITCH. ...... . ..... . .. . .. .. . .. .. .. . 8 - 66
B.20.6 VHDL Code for Synchronous mod-6 Counter . . .. .. . ... . . .... ... ... . .. ...... .. .. B- 67
B.20.7 4-bit Unsigned Up Counter with Asynchronous Load from Primary Input . B- 68
B.20.8 4-bit Unsigned Up Counter with Synchronous Load with a Constant . . . . B- 69
B 21 VHDL Code for State Machines .. ... .. .. ........................... B - 70
B.21.1VHDL Code for Mealy-type State Machines .. . .. . . . .. .... .. .. . . . .. . ... . . . . ... . . B- 72

B.21.1.1 VHDL Code ror aSerial Adder. . . . . . . . . . . . . . . . . . . B-74
B.21.2 VHDLCode for Moore-type State Machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B- 78
B.22 VHDL Code for Guessing Game..................................................... B - 80
8.23 VHDL Code for Traffic Light Controller ........................................... B - 85
B.24 More Examples ............................................................................... B - 89
3.25 VHDL Code to Display Hex Key Input on the LCD Display........... B - 107
B.26 VHDL Code to Display Message on the LCD Display................... B - 114
B.27 VHDL Code to Display Key Input on the LED Display .................. B - 120
B.28 VHDL Code to Display Message on the Multiplexed LED Display B - 122
B.29 VHDL Code for Stepper Motor Interfacing .................................... B - 124
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C.1 Gate Level Modeling ........................................................................... C - 1
C.2 Data Flow Modeling ............................................................................ C - 6
C.3 Behavioral Modeling ........................................................................... C - 7
C.4 Description of D-Latch ........................................................................ C - 8
C.5 Description of Flip-Flops ..................................................................... C - 8
C.6 Description of Sequential Circuits..................................................... C - 11
C.6.1Description of Mealy Circuit .. . .. .. .. . ... ..... ... •.. •.. •.. •.. •.. •. . •. . •. . . ... C- 11
C.6.2 Description of Moore Circuit .. . . . .. . .. . .......... . ..... ... .............. .... . C- 13
C.7 HDL for Registers and Counters....................................................... C - 15
C.7.1 Descriptions or Registers in Verilog HDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C- 16
C.7.2!::ascriptions of Counters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C- 20
C.8 Verilog Code for Generating Waveforms using DAC........................ C - 25
C.9 Verilog Code for Elevator Controller ................................................. C - 31

Programming (using VHDL and Verilog)
I. Write HDL code to realize all the logic ~ates : Refer Section C.l and listing 2.1
2. Write a HDL program for the following combinational designs.
a. 2 to 4 decoder : Refer Section B. l. C.2 and listing 4.12.
b. 8 to 3 (encoder without priority and with priority) : Refer Section B.2 and Listing 3.7.
c. 8 to I multiplexer : Refer Se.ction B.4, C.I and listing.2.3, 2.4.
d. 4 bit binary to gray converter : Refer Section B.I 5.
e. Multiplexer, de-multiplexer, comparator. : Refer Section B.4, B.6. B.12 and Listing 2.7, 4.20.
3. Write a HDL code to describe the functions ofa Full Adder using three modelling styles. :
Refer Section 1.6 and Listing 1.2, 1.3. !.4. 1.5, 1.9 and 1.10.
4. Write a model for ALU. : Refer Section B.8 and Listing C.6.
5. Develop the HDL code for the following flip-flops, SR, D , JK, T . : Refer Section B.18, C.4. C.Sand
listing 3.2. 3.3, 3.4, 3.5. 4.16, 4.18 and 4.19.
6. Design 4-bit binary, BCD counters (Synchronous reset and Asynchronous reset) and "any
sequence" counters. : Refer Section B.20, C.6, C.7 and Listing 3.6, 4.24, 4.26, 6.8. 7.8, 7.9.
7. Write HDL code to display messages on the given seven segment display and LCD and
accepting Hex key pad input data. : Refer Section B.25, B.26, B.27, B.28.
8. Write HDL code to control speed, direction ofStepper motor. : Refer Section B.29.
9. Write HDL code to generate different waveforms (Sine, Square, Triangle, Ramp etc.,) using
DAC change the frequency and amplitude. : Refer Section C.8.
I 0. Write HDL code to simulate Elevator operations. : Refer Section C.9.
Copyngh1ed f"'ater al

Listing 1.1 : Description of circuil using basic gates ......................................... ..................... 1 - 9
Listing 1.2 : Example of VHDL behoviorol description ......................................................... l - 30
Listing 1.3 : Example of Verilog behavioral description ............................. .. ........................ 1 - 31
l isting ·1.4 : Exomple of VHDL dote-flow description ........................................................... 1 - 31
Listing 1.5 : Example of Verilog dole-flow description ..................... .. .................................. 1 - 31
Lisling 1.6 : VHDL swilch-level description........................................................................... I - 33
Lisling 1.7: Verilog switch-level description................................................ ........................ 1 - 34
Listing 1.8 : Exomple of VHDL mixed-type descriplion ................................... ..................... 1 - 34
Lisling 1.9 : Example of Verilog mixed-type descriplion ...................................................... 1 - 35
Lisling 1.10 : Example of mixed language type descriplion .................................................. 1 - 35
Listing 2.1 : HDL code for AND-OR circuit - VHDL and Verilog ...... ..... .................................. 2 - 1
Listing 2.2 : HDL code for holf-odder-VHDL and Verilog ................ ........... . ......................... 2 • 6
Listing 2.3 : HDL code of o 2 x 1 mulliplexer • VHDL ond Verilog. ......................................... 2 - 7
Listing 2.4 : HDL code of o 4 x l mvlliplexer - VHDL and Verilog... ..................................... 2 - 10
Lisling 2.5 : HDL code for o 2 x 2 unsigned combinational array multiplier
VHDL and Verilog. ........................................................................................2 • 13
Lisling 2.6 : HDL code for a D-lolch.VHDL and Verilog. ......................................................2 - 15
Lisling 2.7 : HDL code of o 2 x 2 magnitude comparator - VHDL and Verilog....................... 2 - 19
Listing 2.8 : 4-bit ripple-corry odder case slvdy - VHDL ond Verilog .....................................2 - 20
Listing 2.9 : 4-bil cony-lookahead odder - VHDL and Verilog. .............................................2 - 23
Listing 3 .1 : Example of on HDL behoviorol description- VHDL and Verilog............ ................ 3 - 2
Listing 3.2 : VHDL code for behavioral description of D-Lolch using variable - assignment
statements - .................................................................................................. 3 - 10
Listing 3.3 : VHDL code for behavioral description of D-Lotch using signal-assignment
stotemenls........................ ........................... . ... ............. ................. .... . 3 - 11
Listing 3 .4 : Verilog code for behoviorol description of o D-Lotch ......................................... 3 - 11
~~·~twtft~·m fi!m:;nwt~~iih'i&iWli$ii.5W M
Gopyngh' !Cl rr 1 rial

Listing 3.5 : HDL code for o positive edge-triggered JK flip-flop using the case
stotement-VHDL end Verilog......................................................................... 3 . 16
Listing 3.6 : HDL code for a 3-bit binary counter using the cose statement................ ..... ....... 3 . 18
Listing 3.7 : Verilog description for o 4-bit priority encoder.................................................. 3 • 21
l isting 3.8 : HDL code for colculoting the foctoriol of positive integers-VHDL end Verilog .... 3 · 26
listing 3.9 : 4x4-bit booth algorithm- VHDL and Verilog.................................................... 3 - 33
Listing 4.1 : HDL structurol description- VHDL ond Verilog ................................................... 4 · 2
Listing 4.2 : HDL code of hell adder-VHDL end Verilog ............... .......... ........................... .. 4 · 3
Listing 4.3 : Binding between entity ond architecture............................................................. 4 • 5
Listing 4.4 : Binding between entity ond component............................ .................................. 4 · 5
listing 4.5 : Binding between library and module in VHDL. ............. ....................................... 4 • 6
Listing 4.6 : Binding between o library ond component in VHDL............................................. 4 · 7
Listing 4.7 : Binding between two modules in Verilog.................................... ........................ 4 • 8
Listing 4.8: VHDL code for inverter, AND, OR, NOR, NANO XOR gates .......... ... ................... 4 . 9
listing 4.9: HDL description of o 2x1 multiplexer with active low enable. ............................. 4 • 11
Listing 4.10 : HDL description of o 2x4 decoder with enable input....................................... 4 . 14
Listing 4.11 : VHDL behoviorol description of o tri-stote buffer..... ........................................ 4 . 16
Listing 4. 12 : HDl. description of o 2x4 decoder with tri-stote output.................................... 4 • 17
Listing 4.13 : VHDL code for the holf odder. ...................................................................... 4 . 19
Listing 4.14 : HDL description of o lull odder - VHDL ond Verilog ........................... ........ .... 4 · 20
Listing 4.1 5 : HDL description of on SR latch with NOR gates.............................................. 4 · 23
listing 4.16: HDL description of o D lotch-VHDL ond Verilog ......................................... 4 - 24
listing 4.17: HDL description of o SR-Flip-Flop-VHDL ond Verilog........................................4 - 26
l isting 4.18: HDL description of a D flip-flop-VHDl ond Verilog.......................................... 4 · 28
listing 4.19 : HDL description of JK flip-flop .................... .................................................. 4 · 29
listing 4.20 : HDL description of o 3-bit comporotor using adders....................................... 4 • 32
listing 4.Ll : HDL description of SRAM memory cell. ..................... ..................................... 4 • 34
Listing 4.22 : HDL description for given sequential circuit............................... .................... 4 - 46
Listing 4.23 : HDL description for given sequential circuit using • VHDL and Verilog ............. 4 • 49
Listing 4.24 : HDL description for 3-bit synchronous binary counter ..................................... 4 - 52
listing 4.25 : HDL description of N-bit magnitude comparator using generate statement ........4 - 56
Listing 4.26 : HDL description of on N-bit asynchronous down counter using generate statement
.... ............ 4. 58

listing 4.27 :.HDl description of N-bit memory word using generote .... ..................... ........... 4 · 60
listing 4.28 : HDl descrip""n of N-bit register using · VHDl ond Verilog. ............................ 4 · 61
listing 4.29 : HDl description of N-bit left shift register ........................................... ............ 4 · 62
listing 5.1 : HDl description of o full odder using procedure ond tosk-VHDl ond Verilog ...... 5 - 4
listing 5.2 : HDl description of on N-bit ripple corry odder using procedure ond tosk-
VHDl ond Verilog ........................................................................................... 5 - 6
listing 5.3 : HDl code for converting on unsigned binary to on integer using procedure ond tosk
....................................................................................................... 5 - 8
listing 5.4 : HDl code for converting o fraction binary to reol using procedure ond tosk ........ 5 - 10
listing 5.5 : VHDl code for converting on unsigned integer to binary using procedure ........... 5 - 12
listing 5.6 : VHDL code for converting o signed binary to integer using procedure................ 5 - 14
listing 5.7 : VHDLcode for converting on integer to signed binory using procedure ............... 5 - 15
listing 5.8 : HDl code for signed vector multiplication using procedure ond tosk.................. 5 - 17
listing 5.9 : HDL function to find the greater of two signed numbers .................................... 5 · 24
listing 5.10: VHDLfunction to describe the edge trigger D flip-flop .......... ........................... 5 · 26
listing 5.11 : Verilog function thot calcula tes loctoriol of o number.......................... ............ 5 · 27
l isting 5.12 : VHDLcode for reading ond processing a text file containing integer numbers. .. 5 · 33
listing 5.13 : VHDL code for reading ond processing o text file containing reol numbers........ 5 · 35
listing 5.14 : VHDL code for reading o string of chorocters into on orroy .............................. 5 - 36
listing 5.15 : HDl code for writing integer numbers too file ........... .................................... . 5 - 37
listing 5.16 : VHDl code for finding the percentage morks for o porticulor student................ 5 . 38
listing 5.17: Verilog code for storing y = x + 10 in lodd.txt .......................... ....... ............... 5 · 40
listing 6.1 : Pockoge declorotion ....................................................................................... . 6 · 2
listing 6.2 : Package body ........................................... ...................................................... 6 - 3
listing 6.3 : HDl code for finding the largest element of on orray ..................... ... .................. 6 · 5
listing 6.4 : Multiplication of two signed N-element vectors-VHDL and Verilog .................. 6 - 7
listing 6.5: VHDLDescription for addition of two (5x5] matrices. ................................... 6 · 11
listing 6.6 : HDL description of on AlU-VHDL ond Verilog................................................ 6 . 13
listing 6.7: HDL description of 32x8 SRAM-VHDl ond Verilog. ..................................... 6. 17
listing 6.8 : HDL code for the sta te machine in figure - VHDL ond Verilag ..................... 6 . 20

Listing 7.1 : Mixed-language description of o full odder ................................. ...................... 7 . 2
listing 7.2 : Mixed-language description of on or gate........................................ ................. 7. 3
listing 7.3: Mixed-language description of o 12-bit odder... .......... .......... ............................ 7 - 4
Listing 7.4 : Mixed-language description of o 4-bit odder with o zero flog.............................. 7. 6
Listing 7.5 : Mixed-language description of o master-slave D flip-flop ................................... 7 . 8
Listing 7.6 : Mixed-language description of o 4x4 comparator.............................................. 7. 9
Listing 7. 7 : Mixed-language description of o JK flip-flop ........................................ ........... 7 · 11
Listing 7.8 : Mixed-language description of 3-bit counter with clear .................................... 7 • 12
Listing 7.9 : Mixed-language description of on N-bit asynchronous counter ......... ............. ... 7 • 15
Listing 8. 1 : VHDL code for entily system 1............................................................................ 8 • 3
Listing 8 .2 : VHDL code for entily system2 .. ............................................................ ........ ...... 8 · 3
Listing 8.3 : VHDL code for entity system3 .................................................... ..... ................... 8 • 3
Listing 8.4 : VHDL code for entity system4 .................................................... ..... ................... 8 • 4
Listing 8 .5 : VHDL code for entily systems ............................................... ..... ............. ........... 8 . 4
listing 8.6 : VHDL code for entily system6 ..... ...... ........................................ .......... ........... ... 8 • 4
Listing 8.7 : VHDL code for entity system? .......... ........ ......................................... ................. 8 · 5
Listing 8.8 : VHDL code for entity ALU .......... ..................................................... ................. 8 · 5
listing 8.9 : VHDL code for entity orroy1....... ................... ................................................... 8 · 6
listing 8. 10 : VHDL code for entity weekly activity ............................................................ .... 8 · 7
Listing 8. 11 : VHDL code for entity seguentiol circuit .............. ... .............................. ............. 8 · 9
Listing 8 .12 : Verilog code for module system 1 ......................... ........................ ........ ... ....... 8 · 9
Listing 8 .13 : Verilog code for module system2 ......................... ..... .............. ...................... 8 • l 0
Listing 8 .14 : Verilog code for module system3 .............................. .................................... 8 • 10
Listing 8.15 : Verilog code for module orroy1 ........ ........................ ....... ............................. 8 · 11
listing 8. 16 : VHDL code for o signal-assignment statement, 6 = A ..................................... 8 · 11
Listing 8 .17 : VHDL code for o signal-assignment statement, 6 = 3 • A + 4 ......................... 8 · 13
Listing 8 .1 8 : Struclurol Verilog code for the logic diagram in Fig. 8 .1 5 (b). ..... .................... 8 · 14
Listing 8 .19 : VHDL voriobie-ossignment statement........................ .................... ................. 8 · 15
Listing 8 .20 : Mopping logical operators In HDL ............................................... ......,.......... 8 • 17
Listing 8.21 : Example of if-else statement......................................................................... 8 • 19
Listing 8 .22 : Example of if-else statement........................................................ ................. 8 • 19
Listing 8 .23 : Example of comparison using if-else statement ...................................... ........ 8 • 20

Listing 8.24 : Example of elseil and else-ii.......................................................................... 8 · 22
Listing 8.25 : Example al ii statement with storage .......................... .................................... 8 • 24
Listing 8.26 : Else-ii statement with gate-level logic ....................................................... ..... 8 · 26
Listing 8.27 : Example of case mopping ............................................................................ 8 • 31
Listing 8.28 : Example of case mopping .............................. ............................................. . 8 · 32
Listing 8.29 : Verila"g cosex............................................................................................... 8 • 32
listing 8.30 : Example of case with storage ................................. ..................................... .. 8 • 34
Listing 8.31 : A for-loop statement. ................................................................................. 8 · 37
Listing 8.32 : A Verilog example of task ............................................................ ................. 8 • 38
Listing 8.33 : Verilog example of a lundion ....... ................. ...................... ............. ............ 8 • 40
Listing 8.34 : Example of function synthesis.............................................................. ... ....... 8 · 40

Introduction
1.1 Why HDL?
We are familiar with the design of a digital system. The basic steps involved in
this process are,
a. Specify the desired behaviour of the circuit.
b. Synthesize the circuit.
c. Implement the circuit.
d. Test the circuit to check whether the desired specifications meet.
But as the size and complexity of digital systems increase, they can not be
designed manually; their design becomes highly complex. At their most detailed level,
they may consists of millions of elements, i.e. transistors or logic gates. So Computer
Aided Design (CAD) tools are used in the design of such systems. One such a tool is
a Hardware Description Language (HDL).
HDL describes the hardware of digital systems. This description is in textual form.
The Boolean expressions, logic diagrams and digital circuits (simple and complex) can
be represented using HDL.
• The HDL provides the digital designer with a means of describing a digital
system at a wide range of levels of abstraction and at the same time,
provides access to computer-aided design tools to aid in the design process
at these levels.
• The HDL, represents digital systems in the form of documentation which can
be understood by human as well as computers.
• It allows hardware designers to express their design with behavioral
constructs. An abstract representation helps the designer explore architectural
alternatives through simulations and to detect design bottlenecks before
detailed design begins.
• The HDL makes it easy to exchange the ideas between the designers.
(1 - 1)

Fundamentals of HDL 1 - 2 Introduction
• It resembles a programming language, but the orientation of the HDL is
specifically towards describing hardware structures and behavior. The
storage, retrieval and processing of programs written using HDL can be
performed easily and efficiently.
• HDLs are used to describe hardware for the purpose of simuJation,
modelling, testing, design and documentation.
1.2 A Brief History of HDL
The most prominent modern HDLs in industry are Verilog and VHDL. Verilog is
one of the two major Hardware Description Languages (HDLs) used by hardware
designers in industry and academia. Of course, VHDL is the other one. The industry
is currently split on which is better. Many feel that Verilog is easier to learn and use
than VHDL. Verilog is very C-like and liked by electrical and computer engineers as
most learn the C language in college. VHDL is very Ada-like and most engineers have
no experience with Ada. Let us take an overview of the brief history of both the
languages.
1.2.1 A Brief History of VHDL
VHDL is an acronym for "VHSIC Hardware Description Language" while VHSIC
is an acronym for "Very High Speed Integrated Circuits". VHDL is a hardware
description language that can be used to model a digital system at many levels of
abstraction, ranging from the algorithmic level to the gate level.
In 1981, in United States many companies were involved in designing the VHSIC
chips for Department of Defence. At that time, most of the companies were using
different hardware description languages to describe and develop their integrated
circuits. As a result, different vendors could not effectively exchange designs with one
another. Thus a need for standardized hardware description language for the designs,
documentation, and verification of the digital systems was generated. A team of three
companies, IBM, Texas instruments, and Intermetrics developed first version of VHDL.
To make this language an industry wide standard, the language transferred to IEEE
for standardization in 1986.
The standardization of VHDL began in February 1986 with adaptation of the
VHDL version 7.2. In 1987, the IEEE completed their mission and added several
enhancements to the language. These efforts introduced the IEEE Standard 1076-1987
version of VHDL, which was also recognized by American National Standards
Institute (ANSI). In 1993, some more features are added to VHDL to give the updated
version IEEE Standard 1076-1993. Later on many packages, for example, std_logic_l164
are added with the addition of several logic levels to the existing two logic levels.

Fundamentals of HDL 1 . 3 Introduction
1.2.2 A Brief History of Verilog HDL
Verilog was introduced in 1985 by Gateway Design System Corporation, now a
part of Cadence Design Systems, Inc's Systems Division. Until May, 1990, with the
formation of Open Verilog International (OVI), Verilog HDL was a proprietary
language of Cadence. It is the top HDL used by over 10,000 designers at such
hardware vendors as Sun Microsystems, Apple Computer and Motorola. Industrial
designers like Verilog. It provides the digital designer with a means of describing a
digital system at a wide range of levels of abstraction, and at the same time, provides
access to computer-aided design tools to aid in the design process at these levels. Jt
allows hardware designers to express their design with behavioral constructs,
deterring the details of implementation to a latter stage of design in the design. An
abstract representation helps the designer to explore architectural alternatives through
simulations and to detect design bottlenecks before detailed design begins.
Verilog HDL allows a hardware designer to describe designs at a high level of
abstraction such as at the architectural or behavioral level as well as the lower
implementation levels (i.e. gate and switch levels) leading to Very Large Scale
Integration (VLSI) Integrated Circuits (IC) layouts and chip fabrication. A primary use
of HDLs is the simulation of designs before the designer must commit to fabrication.
1.3 Structure of the HDL Module
HDL contains the features of conventional programming languages such as Pascal
or C, logic description languages such as ABEL-HDL, an~. netlist languages such as
EDlF. The HDL module follows the general structure of software languages such as C
It has a source code that is written in high-level language style using text editors
provided by the HDL package, or it can be written using external text editors and
imported to the HDL package by copy and paste.
Verilog HDL, simply referred to as Verilog has different structure than the VHDL.
Let us discuss the structure of both the HDLs.
1.3.1 Structure of the VHDL Module
The main components of a VHDL description consists of following kinds of
declarations :
• Package (optional)
• Entity
• Architecture
• Configuration (optional)
The Fig. 1.1 shows the relationship of these basic blocks of VHDL program. A
design may include any number of package, entity, architecture and configuration

Fundamentals of HDL 1 • 4 Introduction
declarations. It is important to note that the entity and archit~ture blocks are
compulsorily required; however, the package and configuration blocks are optional.
Package
Configuration
Fig. 1.1 Relationship of VHDL design units
1.3.1.1 Package
There are some declarations which are common across many design units. A
package is a convenient mechanism to store and share such declarations. It is an
optional design unit. A set of declarations contained in apackage declaration may be
shared by many design units. It defines items that can be made visible to other design
units. A package is represented by :
• Package declaration
• Package body (optional)
Package declaration
It defines the interface to the package. The syntax of a package declaration is given
below.
PACKAGE package_name IS
type declarations
subtype declarations
constant declarations
signal declarations
variable declarations
subprogram declarations
file declarations
alise declarations
component declarations
attribute declarations

Fundamentals of HDL
attribute specifications
disconnection specifications
use clauses
END package_name;
1 • 5 Introduction
The items declared in a package declaration can be accessed by other design units
by. using the 'library' and 'use' clauses. This is explained in the further section. The
example of package declaration is given below.
package MUX 4-to-l_package is
component MUX 4-to-1
pon (MO, Ml, M2, M3
s
f
and component;
and MUX 4-to-l_package;
IN STD_LOGIC;
IN STD_LOGIC_VECTOR (1downto 0)
OUT STD_LOGIC;
Fig. 1.2 Package declaration for 4-to-1 multiplexer
Package body
It contains the details of a package, that is the behavior of the subprograms and
the values of the deferred constants which are declared in a package declaration. The
package body may contain other declarations. The syntax of it is as given below.
package body package_name is
subprogram bodies
complete constant declarations
subprogram declarations
type and subtype declarations
file and alias declarations
use clauses
and package_name;
The name of the package must be same as the name of its corresponding package
declaration. If the package declaration does not have any subprogram or deferred
constant declarations, a package body is not necessary.
1.3.1.2 Entity
It gives the specification of input/output signals to external circuitry. An entity is
modelled using an entity de<;laration and atleast one architecture body. An entity X,
when used in another entity Y, becomes a component for the entity Y. Entity gives
interfacing between device and the other peripherals. An entity usually has one or
more ports, which are analogous to the pins on a schematic symbol. All information

must flow into and out of the entity through the ports. Each port must contain name,
data flow direction and type.
The syntax of a VHDL entity declaration is as shown below.
entity entity_name is
port ( signal_names : mode signal_type;
signal_names: mode signal_type;
signal_names : mode signal_type);
end entity_name ;
The following section describes the different elements of entity declaration.
entity_name
signal_names
mode
in
out
inout
buffer
It is an identifier selected by the user to name the entity.
It is a List of user selected identifiers to name external interface
signals.
The ports can be declared in four types which specify the signal
direction.
This mode is used for a signal that is an input to an entity (value is
read not written).
It is used for a signal that is an output from an entity. The value of
such a signal can not be read inside the entity's architecture. But it
can be read by other entities those use it.
It is used for a signal that is both, an input to an entity and an
output from the entity.
The signal is an output from the entity and its value can also be
read inside the entity's architecture.
slgnal_type : It is a built-in or user defined signal type.
For example, there is a system having its inputs and outputs like rd, wr, ADD,
x, y, z, ad, al. The entity for this can be written as shown below.
entity gate_logic is
port (
wr : in std_logic;
rd : In std_logic;
ad : inout std_logic_vector (7 downto 0);
ADD : in std_logic_vector (0 to 3);
x,y,z : out std_logic;

al : buffer std_logic_vector (7 downto 0)
);
end gate_logic ;
Here rd, wr are inputs to the system so they are input ports. The ad is also input
signal but it is 8 bit so it is defined as vector (7 downto 0). It means 7 is assigned to
MSB of your signal and 0 is assigned to LSB of your signal. Similarly x, y, z are
output signals so they are defined as output ports. The al is coming out and is
defined as buffer signal, so that you can also read this signal.
1.3.1.3 Architecture
Architecture specifies behavior, functionality, interconnections or relationship
between inputs and outputs. It is the actual description of the design. An architecture
consists of two portions : architecture declaration and architecture body. An
architecture body specifies the internal details of an entity.
• As a set of concurrent assignment statements (to represent dataflow)
• As a set of interconnected components (to represent structure)
• As a set of sequential assignment statement (to represent behavior)
• As any combination of above three.
The syntax for architecture is given below
architecture architecture_name of entity_name is
Declarations
begin
concurrent statements;
sequential statements;
end architecture_name;
To design any system, first we have to write the entity. In the architecture, we
write architecture_name for that entity. In declaration part, types, signals, constants,
function definitions, procedure definitions, component definitions etc. can be declared.
The variables can also be declared here. VHDL variables are similar to signals, except
that they usually do not have physical significance in a circuit. A variable declaration
is similar to a signal declaration, except that the 'variable' keyword is used as shown
below.
variable variable_names : variables_type;

Fundamentals of HDL
Example:
1. 8
architecture gate of or_gate Is
begin
Architecture process (a,b)
begin
1.3.1.4 Configuration
Process
statement if a ='O' and b ='O' then
c< =·o·:
else
Sequential --+--+---t
statements
c < ='1';
end if:
end process;
end gate;
Introduction
Configuration declarations may be used to associate particular design entities to
component instances (unique references to lower-level components) in a hierarchical
design, or to associate a particular architecture to an entity. As their name implies,
configuration declarations are used to provide configuration management and project
organization for a large design.
Important points to remember while representing any module us!ng VHDL
1. Each statement in VHDL is terminated with a semicolon (;).
2. The language is case insensitive. Le. the uppercase and lowercase letters are
considered as same.
3. The name should start with an alphabet letter and can include the special
char::.crer underscore LJ.
4. The name of the ports must be followed by a colon (:).
5. The architecture body starts with the predefined word begin, followed by
statements that detail the relationship between the outputs and inputs.
6. The comment should begin with two hyphens (--).
7. Leaving the blank spaces between two words or at the beginning of the line
are allowed.
8. Leaving the blank line(s) is allowed in the module.

1.3.2 Structure of the Verilog Module
The Verilog HDL describes a digital system as a set of modules. Each of these
modules has an interface to other modules to describe how they are interconnected.
Each module consists of a declaration and a body. In the declaration, name, inputs
and outputs of the module are listed. The body shows the relationship between the
inputs and the outputs. Usually, we place one module per file but that is not a
requirement. The modules may run concurrently, but usually we have one top level
module which specifies a closed system containing both test data . and hardware
models.
A module is a basic building block of Verilog HDL. Modules can represent pieces
of hardware ranging from simple gate to complete systems. e.g. a microprocessor. The
struture of module is,
module <module name> <port list>;
< declares>
< module items>
endmodule
The <module name> is an identifier that uniquely names the module. The module
name is user selected. It should start with alphabetical letter and it can include the
special character underscore (j. In contrast to VHDL, Verilog is a case sensitive. The
<port list> is a list of input, inout and output ports which are used to connect to other
modules. The <declares> section specifies data objects as registers, memories and wires
as wells as procedural constructs such as functions and tasks.
The Listing. 1.1 shows the example Verilog code. This code is the description for
the logic circuit shown in the Fig. 1.3.
.... Listing 1.1: Description of circuit using basic gates
module BG_circuit (P, Q , R, Y);
input P, Q, R;
output Y;
wires, t;
assign s = -P;
assign t = s & O;
assign Y = t I R;
endmodule
Fig. 1.3 Circuit using basic gates

Fundamentals of HDL 1 -10 Introduction
1n contrast to VHDL, in Verilog, input and output port signal types are implicitly
declared. We can declare more than one input or output on the same line using a
comma (,) to separate each input as shown in the Listing 1.1.
Important points to remember while representing any module using Verilog HDL.
1. Each statement in Verilog HDL except comment and last statement
(endmodule) is terminated with a semicolon (;).
2. The blank lines are allowed in the module and also spaces between the words
or at the begi1ming of the line are allowed.
3. The language is case sensitive. i.!?. the uppercase and lowercase letters are
considered as different.
4. The function of a circuit is indicated by the text between two slashes (I/) and
the end of the line which is interpreted as a comment.
5. Verilog uses about 100 keywords. All must be given in lowercase.
6. Identifiers are the names given to variables. With these names, they can be
referred in the design. They consist of alphanumeric characters and underscore
(-). They can not start with a number.
7. The input and output keywords are used for declaring inputs and outputs.
The keyword inout is used for a signal that is both, an input and an output.
8. Internal connections within the circuit are declared with the keyword wire.
Note : The ke}"vords are highlighted by printing them in bold. But it is not the
requirement of Verilog HDL.
1.4 Operators
HDL has an extensive list of operators to perform a wide variety of functions. Let
U $ :.ee the operators in VHDL and Verilog HDL.
1.4.1 Operators in VHDL
VHDL includes the following kinds of operators :
• Logical
• Relational
• Arithmetic
• Shift and Rotate

1.4.1.1 Logical Operators
Logical operators, when combined with signals and/or variables, are used to
create combinational logic. VHDL provides the logical operators as shown in the
Table 1.1.
Operator Equivalent Logic Operand Type Result Type
AND
=V- Bit Bit
OR
=C>- Bit Bit
NANO
=D- Bit Bit
NOR
=D- Bit Bit
XOR
=lD-- Bit Bit
XNOR =)[>-- Bit Bit
NOT -I>-- Bit Bit
Table 1.1 VHDL logical operators
These operators are defined for the types bit:' std_logic and Boolean, and for
one-dimensi011al arrays of these types (for example, an array of type bit_vector or
std_logic_vector).
The effects of the logical operators are defined in the following tables. The symbol
T represents TRUE for type BOOLEAN, '1' for type BIT; the symbol F represents
FALSE for type BOOLEAN, 'O' for type BIT.

A B A and B A B A or B A B A xor B
T T T T T T T T F
T F F T F T T F T
F T F F T T F T T
F F F F F F F F F
A B Anand B A B A nor B A not A
T T F T T F T F
T F T T F F F T
F T T F T F
F F T F F T
1.4.1.2 Relational Operators
Relational operators are used to create equality or magnitude comparison
functions. VHDL provides the relational operators as shown in the Table 1.2.
Operator Description Operand Type Result Type
= Equality Any type Boolean
I= Inequality Any type Boolean
< Less than Scalar or discrete array type Boolean
<= Less than or equal Scalar or discrete array type Boolean
> Greater than Scalar or discrete array type Boolean
>= Greater than or equal Scalar or discrete array type Boolean
Table 1.2
The following statement demonstrates the use of some of the above relational
operators :
if (A/= B) then ...
A is compared to B. If A is equal to B, then the value of the expression (A/= B) is
false (O}; otherwise it is true (1).
if (A> B) then ...
If A is greater than B, the value of the expression (A > B) is true (1); otherwise it
is false (0).
Note : The operands of each relational operator must be of the same type. The
result type of each relational operator is the predefined type Boolean.

1.4.1.3 Arithmetic Operators
Arithmetic operators are used to create arithmetic functions. Arithmetic operators
provided by VHDL are listed in Table 1.3.
Operator Operation Operands (A or Result Type
B) Type
Addition A numeric
numeric+
A+B B numeric
Subtraction A numeric
numeric-
A-B B numeric
. Multiplication A integer or real
Same as A
AxB B integer or real
. Multiplication A physical
Same as A
A x B B integer or real
. Multiplication A integer or real
Same as B
A x B B physical
I
Division A integer or real
Same as A
A + B B integer or real
Division A integer or real
Same as BI
A + B B physical
I
Division A physical
Same as A
A + B B integer or real
Modulus A only integer
integermod
A mod B B only integer
Remainder A only integer
integerrem
A rem B B only integer
Absolute A numeric
positive numericabs
abs (A)
Concatenation A numeric or
& (A & B) array
Same as A
B numeric or
array
.. Exponent A real or integer
Same as A
A•• B B only integer
Table 1.3 Arithmetic operators in VHDL

1.4.1.4 Shift and Rotate Operators
These operators shift or rotate the bits of the operand right or left by some
specified number of bit positions. There are two types of shift operators : Logic shift
operator and arithmetic shift operator. When logical shift operator is used, the vacant
positions created due to shift operation are filled with zeros. On the other hand, when
arithmetic right shift operator is used the vacant positions created due to shift
operation are filled with MSB (sign bit). The arithmetic left shift is same as the logical
left shift.
The Table 1.4 shows the shift and rotate operators supported in VHDL. To
understand the function of these operators, assume that operand A is the 4-bit vector
with value 1101.
Operator Operation Description Operand A Operand A after
before operation operation
sll A sll 1 Shift A one position left 1 1 0 1 1 0 1 0
logical
Sil A sll 2 Shift A two positions left 1 1 0 1 0 1 0 0
logical
srl A Sri 1 Shift A one position 1 1 0 1 0 1 1 0
right logical
srl A Sri 2 Shift A two positions 1 1 0 1 0 0 1 1
right logical
sla A sla 1 Shift A one position left 1 1 0 1 1 0 1 0
arithmetic
sra A sra 1 Shift A one position 1 1 0 1 1 1 1 0
right arithmetic
rol A rol 1 Rotate A one posttion 1 1 0 1 1 0 1 1
left
ror A ror 1 Rotate A one position 1 1 0 1 1 1 1 0
right
Table 1.4 Shift and rotate operators in VHDL
Note:
• Shift left by 1 bit performs multiplication by two while shift right by 1 bit
performs division by two.
• With rotate operation we can restore the original contents after one complete
cyclic rotation. This is not the case with shift operation.
1.4.1.5 Operator Precedence
The precedence of operators is shown in Table 1.5. The operators belongs to same
row have the same precedence level. Operators are listed in order of decreasing
precedence.

Type Operators
Miscellaneous operators -. abs not (Highest precedence)
Multiplying operators . I mod rem
Sign + -
Adding operators + - &
Relational operators = I= < <= > >=
Logical operators and or nand nor xor xnor (Lowest precedence)
Table 1.5
Operators of higher precedence are associated with their operands before operators
of lower precedence. For a sequence of operators wi~ the same precedence level, the
operators are associated with their operands in textual order, from left to right. The
precedence of an operator is fixed and may not be changed by the user, but
parentheses can be used to control the association of operators and operands.
1.4.2 Operators in Verilog HDL
Verilog HDL includes following kinds of operators :
• Boolean Logical
• Unary Reduction Logical
• Bitwise logical
• Relational
• Binary Arithmetic
• Unary Arithmetic
• Other
1.4.2.1 Boolean Logical Operators
Logical operators operate on logical operands and return a logical value, i.e.,
TRUE(!) or FALSE(O). Used typically in if and while statements. Do not confuse
logical operators with the bitwise Boolean operators. For example, 1 is a logical NOT
and - is a bitwise NOT. The first negates, e.g. !(5 == 6) is TRUE. The second
complements the bits, e.g. -{l,0,1,1) is 0100.
Operator Name
! Logical negation
&& Logical AND
11 Logical OR

Fundamentals of HDL. 1 -16 Introduction
1.4.2.2 Unary Reduction Logical Operators
Unary reduction operators operate on a single operand. They produce a single bit
result from applying the operator to all of the bits of the operand. For example, in
statement B =&A, if A. = 1101, then B = (1 & 1 & 0 & 1) = 0.
Operator Name
& ANO reduction
I OR reduction
• XOR reduction
-& NANO reduction
-1 NOR reduction
-· XNOR reduction
1.4.2.3 Bitwise Logical Operators
Bitwise operators operate on the bits of the operand or operands. The result of A
& B is the AND of each corresponding bit of A with B. For example, if A = 1011 and
B = 0101, then C= A & B gives C = 0001. Except for bitwise .negation, these operators
operate on a two operands.
Operator Operation
- Bitwise negation
& Bitwise ANO
I Bitwise OR
• Bitwise XOR
-& Bitwise NANO
- 1 Bitwise NOR
_11. or"'- Equivalence bitwise NOT XOR
1.4.2.4 Relational Operators
Relational operators compare two operands and return a logical value, i.e. TRUE(l)
or FALSE(O). For example, if A = 0100 and B = 0100, then statement if (A== B) results
True(l). If any bit is unknown, the relation is ambiguous and the result is
unknown(X).

Operator Operation
> Greater than
>= Greater than or equal
< Less than
<= Less than or equal
-- Logical equality
!= Logical inequality
1.4.2.5 Binary Arithmetic Operators
Binary arithmetic operators operate on two operands. Register and net, i.e. wire,
operands are treated as unsigned. However, real and integer operands may be signed.
U any bit of an operand is unknown ('x') then the result is unknown.
Operator Operation Comments
+ Addition
- Subtraction
. Multiplication
I Division Divide by zero produces an x. i.e. unknown.
% Modulus
1.4.2.6 Unary Arithmetic Operators
Operator Operation Comments
- Unary minus Changes sign of its operand.
1.4.2.7 Other Operators
The conditional operator operates much like in the language C.
Operator Operatio n Comments
--- Case equality The bitwise comparison includes comparison of x and z values. All
bits must match for equality. Returns TRUE or FALSE.
!== Case inequality The bitwise comparison includes comparison of x and z values.
Ally bit difference produces inequality. Returns TRUE or FALSE.
{ ' } Concatenation joins bits together with 2 or more comma-separated
expressions. e.g. (A{O], 0(1:7]} concatenates the zero bit of A to
bits 1 to 7 of B.

•
<< Shift left Vacated bit positions are filled with zeros, e.g. A =A < 2; //shifts A
two bits to left with zero fill.
» Shift right Vacated bit positions are filled with zeros.
?: Conditional Assigns one of two values depending on the conditional expression
e.g. A =C>D ? B+3 : B-2 means
if C greater than D, the value of A is B+3 otherwise B - 2.
1.4.2.8 Operator Precedence
The precedence of operators is shown in Table 1.6. The top of the table is the
highest precedence and the bottom is the lowest. Operators on the same line have the
same precedence and associate left to right in an expression. Parentheses can be used
to change the precedence or clarify the situation. We strongly urge you to use
parentheses to improve readability.
Type Operators
Unary operators ! & -& I - I '
_, + - (Highest precedence)
Multiplying operators .. I o/o
Sign operators + -
Relational operators << >>
< <= > >=
== != === -==
Logical operators & -& • -·
I - I
&&
II
Conditional operators ?: (Lowest precedence)
Table 1.6 Operator precedence in Verilog HDL
1.5 Data Types
To match the need for the hardware, the HDL supports variety of data types. For
example, if we are describing a signal, we need to specify its type (i.e. the values that
the signal can take), such as type bit, which means that the signal can have values
either 0 or 1; or type std_logic, in which the signal can have eight values that include
0, 1 and high impedance.
In this section, we discuss the data types supported by VHDL and Verilog HDL.

1.5.1 VHDL Data Types
VHDL supports a variety of data types. The type of a variable, signal, or constant
determines the operators that are predefined for that object as well as the range of
values that it can take on. The VHDL data types can be broadly classified into
following five data types :
• Scalar types : The scalar types include numeric data types and enumerated
data types. The numeric types consist of integer, floating point (real) and
physical types. Bit, Boolean and character are all enumerated types.
• Composite types : Array and record types are composite data types. The
values of these types are collection of their elements.
• Access types : They are pointers; they provide access to objects of a given
data type.
• File type : They provide access to object that contain a sequence of values of
a given type.
• Other types : They include the data types provided by the several external
libraries.
1.5.1 .1 Scalar Types
We have seen that, the scalar types consist of enumeration types, integer types,
physical types, and floating point types. Enumeration, data types and integer types are
called discrete types. On the other hand, integer types, floating point types and
physical types are called numeric types.
Integer type
As the name indicates, it covers all integer values, the values can be positive or
negative. The default range of Integer is -2147483647 to +2147483647. However, user
can specify a shorter range by using the pre-defined word range. The shorter range
may require less bits to represent the number when binary encoded. We can define
the subtype of base type whose range must be wholly contained within the bounds of
the range of base type.
Examples:
type num is integer;
type long is range -32768 to 32768; -- 16 bit binary encoding.
type short is range 0 to 255; -- 8 bit binary encoding.
sub type shorter is short range 0 to 31; -- 5 bit binary encoding.
sub type shortest is short range 0 to 15; -- 4 bit binary encoding.

Note : The encoding of integers in a binary format means that all ranges are rounded
up to the nearest power of two. This means that if shorter had been declared
as:
subtype shorter is short range 0 to 15;
Then the object is synthesized into 4 wires. Objects declared type of type integer
without a range constraint will be synthesized into 32 wires.
Real (floating point) type
Floating point type definition defines both a type and subtype of that types. The
default range of floating point is -1E38 to + IE38. Like integer type, here also we can
specify the shorter range by using the predefined word range.
Examples :
type Real_data is real;
type Voltage is range to -12.0 to +12.0;
Subtype min voltage is range - 5.0 to +5.0;
Enumerated types
Bit, Boolean, Character and severity_level are the enumerated types. These are
defined in a library such as std or ieee.
Bit data type allows only two values 0 or 1. It is used to describe a signal that
takes only l(High) or O(Low). The type Boolean has two values, True(l) or False(O).
Both True and False are predefined words.
The type character constitutes the 128 characters of the ASCII character set. These
character values are called character literals and are always written between two
single quotes (' '). For example, 'A', '_', ' 3 ' and so on.
An object with type severity can take one of four values : note, warning, error or
failure. This type is typically used in assertion statements.
Copynqhted material

Examples :
type Bit is ('O', '1');
type Switch_level is ('O', '1', 'x');
Physical type
Values of a physical type represent measurements of some quantity. Any value of
a physical type is an integral multiple of the base unit of measurement for that type.
For example, time (e.g. second, millisecond, microsecond, etc.) and voltage (e.g., volt,
millivolt, microvolt, etc.)
A physical type definition defines both a type and a subtype of that type. Each
unit declaration (either the base unit declaration or a secondary unit declaration)
defines a unit name. Unit name declared in secondary unit declaration must be
directly or indirectly defined in terms of integral multiples of the base unit of the type
declaration in which they appear.
Examples :
type time is range -1E18 to 1E18
units
fs; -- femtosecond
ps = 1000 fs; •• picosecond
ns = 1000 ps; ·· nanosecond
us = 1000 ns; -- microsecond
ms= 1000 us; -- millisecond
sec 1000 ms; -- second
min = 60 sec; -- minute
end units;
type distance is range 0 to 1E16
units
-- base unit :
A''
-- angstrom
-- metric lengths;
nm 10A; ··nanometer
um = 1000 run; •• micrometer (or micron)
mm = 1000 um; -- millimeter
cm= 10 mm; -- centimeter
Copynqhted material

Fundamentals of HDL
m = 1000 mm;
km= 1000 m;
-- English lengths :
mil= 254000 A;
inch = 1000 mil;
ft = 12 inch;
yd= 3 ft;
fin = 6 ft;
mi= 5280 ft;
lg = 3 mi;
end units;
1 - 22
-·meter
··kilometer
.. mil
-- inch
··foot
·· yard
··fathom
-- mile
·· league
x : distance; y : time; z : integer:
x := SA + 13 ft - 27 inch; ··arithmetic operations
y := 3ns + 5 min;
z := ns/ps;
x := z* mi;
y := y/10;
·· on physical data type
Introduction
The arithmetic operations are predefined for all physical types. It is an error if the
execution of such an operation cannot deliver the correct result (that is, if the value
corresponding to the mathematical result is not a value of the physical type).
User-defined types
The user can define a type by using the predefined word type.
Example :
type Multi_leveUogic is (low, high, rising, falling);
type arith_op is (add, sub, mul, div);
Here, multi_level_logic and arith_op are the user defined types. The variables
declared using such data types can take values mentioned in the data type definition.
For example,
Variable operation : arith_op := sub;
Variable level : Multi_level_logic := high;
1.5.1.2 Composite Types
Composite types are used to define collection of values. These include both arrays
of values (collection of values of a single type) and records of values (collection of
values of the same or different types).

An object of a composite type represents a collection of objects, one for each
element of the composite object. A composite type may only contain elements that are
of scalar, composite, or access types; elements of file types are not allowed in a
composite type. Thus, an object of a composite type ultimately represents a collection
of objects of scalar or access types, one for each non-composite subelement of the
composite object.
Array types
An array object is a composite object consisting of elements that have the same
subtype. The name for an element of an array uses one or more index values
belonging to specified discrete types. The value of an array object is a composite value
consisting of the values of its elements.
An array object is characterized by the number of indices (the dimensionality of
the array), the type, position and range of each index and the type and possible
constraints of the elements. The order of the indices is significant.
A one-dimensional array has a distinct element for each possible index value. A
multidimensional array has a distinct element for each possible sequence of index
values that can be formed by selecting one value for each index (in the given order).
The possible values for a given index are all the values that belong to the
corresponding range; this range of values is called the index range.
Example:
type num is integer ;
type numarr is array (7 downto 0) of num;
-- numarr is an array of 8 integer numbers
type my_word is array (0 to 31) of BIT;
-- a memory word type with an ascending range
type data_in is array (7 downto 0) of five_level_logic;
-- an input port type with a descending range
-- Example of unconstrained array declarations
type memory is array (integer range <>) of my_word;
-- a memory array type

string and bit_vector are the predefined array types, which are defined in
package std.
The values of the predefined type string are one-dimensional arrays of the
predefined type character, indexed by values of the predefined subtype positive;
subtype pos!tive is integer range 1 to integerhigh;
type string is array (positive range <>) of character;
The values of the predefined type bit_vector are one-dimensional arrays of the
predefined type BIT, indexed by values of the predefined subtype natural:
subtype natural is integer range 0 to integerhigh;
type bit_vector is array (natural range <>) of bit;
Record type
A reco•d type is a composite type, objects of which consist of named elements.
The value of a record object is a composite value consisting of the values of its
~iements. The record type is analogous to the record datatype in pascal and the struct
decl:uation in C.
A record type definition creates a record types; it consists of the element
declarations, in the order in which they appear in the type definition.
Example :
type DATE is
record
DAY : INTEGER range 1 to 31
MONTH : MONTH_NAME;
YEAR : INTEGER range 0 to 4000;
end record;
Copynght8d maten:il

1.5.1.3 Access Types
Values belonging to an access type are pointers to a dynamically allocated object
of some other type. These are similar to pointers in pascal or C languages.
Example:
type ptr is access date;
ptr is an access type whose values are
-- addresses that point to object of type date.
1.5.1.4 File Type
File types are used to define objects representing files in the host system
environment. The value of a file object is the sequence of values contained in the host
system file.
type_file_type_name Is file of type_name;
The type mark in a file type definition defines the subtype of the values contained
in the file. The type mark may denote either a constrained or an unconstrained
subtype. The base type of this subtype must not be a file type or an access type. If the
base type is a composite type, it must not contain a subelement of an access type. If
the base type is an array type, it must be a one-dimensional array type.
Examples :
file of string -- Defines a file type that can contain
-- an indefinite number of strings
file of natural ·• Defines a file type that can contain
-· only non-negative integer values
Three operations are provided for objects of a file type. Given the following file
type declaration :
type FT is file of TM :
Where type mark TM denotes a scalar type, a record type, or a constrained array
subtype, the following operations are implicitly declared immediately following the
file type declaration :
procedure read (F : in FT; value : out TM);
procedure write (F : out FT; value: in TM);
function endfile (F: in FT) return boolean;
Procedure read retrieves the next value from a file. Procedure write appends a
value to a file. Function endfile returns False if a subsequent read operation on an
input file can retrieve another value from the file; otherwise it returns true. Function
endfile always returns true for an output file.

1.5.1.5 Other Types
There are several other types provided by external library, IEEE. This library
contains a std_logic_l164 package which supports more types. Let us discuss them.
std_Logic type
std_logic is a data type defined by IEEE standard 1164, and defined in the file
ieee.vhd.std_logic is an enumerated type. This logic has nine v'llues as listed in
Table. 1.7.
Value Definition
u - Uninitialized
x - Forcing unknown
0 -· Forcing 0
1 - Forcing 1
z - High impedance
w - Weak unknown
L - Weak 0
H - Weak 1
. - Don't care
Table 1.7
The std_logic data type is very important for both simulation and synthesis.
Std_logic includes values that allow us to accurately simulate such circuit conditions
as unknowns and high-impedance stages. For synthesis purposes, the high-impedance
and don't-care values provide a convenient and easily recognizable way to represent
three-state enables and don't-care logic. For synthesis, only the values 0, 1, z and -
have meaning and are supported.
std_lugic_vector type
The type std_logic_vector represents an array of bits whose type is std_logic.
Example:
Port (I : in std_logic_vector (7 downto O);
0: out bit);
In the above example, port I is declared as type std_logic_vector which has 8 bits.
Signed
The type signed is a numeric type. It is declared in the external package
numeric_std and represents signed integer data in the form of an array. The left most

bit of objects of signed type represents sign and such objects are represented in 2's
complement form. let us see the object definition.
In the above definition, the variable difference is declared as signed type and has
5 bits with initial value 10011, or - 13.
Unsigned
The type unsigned represents integer data in the form of an array of std_logic and
it is declared in the external package numeric_std. Let us see the object definition
variable num : unsigned (4 downto 0) := 10011; In the above definition, the variable
num is declared as unsigned type and has 5 bits with initial value 10011, or 19.
1.5.2 Verilog Data Type
The set of Verilog HDL data types is designed to represent the data storage and
transmission elements found in digital hardware. Since the purpose of Verilog HDL is
to model digital hardware, the primary data types are for modeling registers (reg)
and nets (wire). The reg variables store the last value that was procedurally assigned
to them whereas the wire variables represent physical connections between structural
entities such as gates. A wire does not store a value; its value changes continuously
by the circuit that are driving it.
The Verilog HDL also supports several other data types including integers, real,
parameters and arrays.
1.5.2.1 Nets (Wire) and Registers
The reg and wire data objects may have the following possible values :
Value Definition
0 logical zero or false
1 logical one or true
x unknown logical value
z high impedance of tristate gate
The reg variables are initialized to x (unknown logic value) at the start of the
simulation. Any wire variable not connected to something has the x value. We may
specify the size of a register or wire in the declaration. For example, the declarations
wire Dl;
wire DO = t 'bO;
reg flag;

Fundamentals of HDL 1. 28 Introduction
Specify wires 0 1 and DO to be single bit wide. The initial value of DO is l'bO,
which represents 1 bit with value 0.
When the size of the reg or wire is more than 1 bit then registers and wires are
declared as vectors. Vectors are declared by brackets. The bits in vectors can be
referenced by the notation (<start-bit>:<end-bit>]. For example, the declarations
reg (0:7( A, B;
wire 10:3) Dataout;
reg (7:0) C = 8'b10001010;
reg (7:0) D ~ 3'd138;
A = 8'b01011010
B ={A(0:3) I A(4:7(, 4'b0000};
Specify registers A and B to be 8-bit wide with the most significant bit the zeroth
bit, whereas the most significant bit of register C and register D is bit seven. The wire
Dataout is 4 bits wide. C holds a value of 10001010 (b stands for binary). D holds the
same value as C (10001010); however it is specified in decimal 138 (d stands for
decimal).
B is set to the first four bits of A bitwise or-ed with the last four bits of A and
then concatenated with 0000. B now holds a value of 11110000. The II brackets means
the bits of the two or more arguments separated by commas are concatenated
together.
An argument may be replicated by specifying a repetition number of the form :
Here are some examples :
c = {2{4'b1011}};
C = {{4{A(41}}, A[4:71};
Memories are specified as
each 32-bits.
reg [31:0) Mem (0:1023);
II C assigned the bit vector 8'b10111011
11 first 4 bits are sign extension
vectors of registers. For example, Mem is 1 K words
The notation Mem(O) references the zeroth word of memory. The array index for
memory (register vector) may be a register. Notice that one can not refer a memory at
the bit-level in Verilog HDL. If we want a specific range of bits in a word of memory,
we must first transfer the data in the word to a temporary register.
1.5.2.2 Abstract Data Types : integer, real time
In addition to modeling hardware, there are other uses for variables in a hardware
model. For example, the designer might want to use an integer variable to count the
number of times an event occurs. For the convenience of the designer, Verilog HDL

has several data types which do not have a corresponding hardware realization. These
data types include integer, real and time. The data types integer and real behave
pretty much as in other languages, e.g. C. Be warned that a rag variable is unsigned
and that an integer variable is a signed 32-bit integer. This has important
consequences when we subtract.
time variables hold 64-bit quantities and are used in conjunction with the $time
system function. Arrays of integer and time variables (but not reals) are allowed.
Multiple dimensional arrays are not allowed in Verilog HDL.
Examples:
integer Count; //simple signed 32-bit integer
integer K(1:64J; //an array of 64 integers
real cost; // declares cost as real
time Start, Stop; // Two 64-bit time variables
1.5.2.3 Parameter
Parameter type is used to define global constants. We can declare global constants
by predefined word parameter.
Examples:
parameter N = 0;
parameter M = 7;
reg (M:NJ C =8'b10001010; //use of constants to define register width
1.6 Styles or Types of Descriptions
In a VHDL or Verilog program, architecture body (VHDL) or the module (Verilog)
contains a series of concurrent statements. All concurrent statements execute
simultaneously. HDL has several different concurrent statements. Also, it has a
mechanism which bundles a set of sequential statements which operate as a single
concurrent statement. The way in which these statements are used is called the
modeling style or types of descriptions". Thus these statements give rise to six
different modeling styles or types of descriptions a~,
• Behavioral
• Data flow
• Structural
• Switch-level
• Mixed-Type
• Mixed-Language

Fundamentals of HDL 1 • 30
Let us see the HDL uescription of full adder shown in the Fig. 1.4
Fig. 1.4 Implementation of full-adder
1.6.1 Behavioral Descriptions
Introduction
It is sometimes possible to directly describe the behavior or the functionality of a
circuit. Such a modeling style is called behavioral modeling which is very similar in
syntax and semantics to that of a high-level programming language (For example : C,
Pascal). A behavioral description models the system as to how the outputs behave
with the inputs.
In VHDL, the behavior of the entity is expressed using sequentially executed,
procedural code. The key mechanism used to model the behavior of the entity is, a
process statement.
)II- Listing 1.2 : Example of VHDL behavioral description
entity full_add is
port (A, B, Cin : in bit;
Sum, Cout : out bit);
end full_add;
architecture adder of full add is
begin
process (A, B, Cin)
begin
Sum < = A xor B xor Cin;
Cout < = (A and B) or (Cin and A) or (Cin and B);
end process;
end adder;
In Verilog, the key mechanism used to model the behavior is predefined words
always or initial.

Fundamentals of HDL 1 - 31
.... Listing 1.3 : Example of Verilog behavioral description
module full_add (A, B, Cin, Cout, Sum);
input A, B, Cin;
output Sum, Cout;
reg Sum, Cout;
always @(A, B, Cin)
begin
Sum = (A A B) A Cin;
Cout = (A & B) I (Cin & A) I (Cin & B);
end
endmodule
1.6.2 Dataflow Design Elements
lntrQduction
Data flow describes how the circuit signals flow from the inputs to the outputs.
There are some concurrent statements which allow to describe the circuit in terms of
operations on signals and flow of signals in the circuit. When such concurrent
statements are used in a program, the style is called a 'dataflow design'. Concurrent
signal assignment statements are used in.this type of modeling style.
.... Listing 1.4 : Example of VHDL data-flow description
entity full_add is
end full_add;
begin
Cout < =(A and B) or (Cin and A) or (Cin and B);
end adder;
In Verilog, predefined word assign is used to assign a value to the left-hand side
of a signal-assignment statement.
.... Listing 1.5 : Example of Verilog data-flow description
input A, B, Cin;
output Sum, Cout;
assign Sum =(A A B) A Cin;
assign Cout = (A & B) I (Cin & A) I (Cin & B);
endmodule

The built in operators of VHDL (for example : AND, OR,"NOT) and Verilog (for
example & I ") are used in the expression.
Here, the data flow model for the full_add is described using a two concurrent
signal assignment. In a signal assignment statement, the symbol <= implies an
assignment of a value to a signal ·in VHDL. The value of the expression on the
right-hand-side of the statement is computed and is assigned to the signal on the
left-hand-side, called a target signal. In Verilog, predefined word assign is used to
assign a value to a signal. A concurrent signal assignment is executed only when any
signal in the expression on the right-hand-side has an event on it, that is, the value of
the signal changes.
1.6.3 Structural Design Elements
In structural design, a VHDL and Verilog uses components or gates to model the
system. The important features of VHDL structural type of architecture body are :
• Design hierarchy
• Components are used
• Each component is simulated separately
In the structural modeling, an entity is described as a set of components connected
by signals, that is, as a netlist. The components used in an architecture may be from a
library or may be ones that were previously defined as part of a design.
entity full_add is
end full_add;
component xor3
port (11, 12, 13 : in bit;
01 : out bit );
end component;
component and2
port (11, 12 : in bit;
01 : out bit );
end component;
component or3
port ( I1. 12, 13 : in bit;
01 : out bit );
end component;
signal S1, S2, SJ : bit;

Fundamentals of HDL 1 - 33
begin
Y1 : xor3 port map (A, B, Cin, Sum);
Xl : and2 port map (A, B, S1);
X2 : and2 port map (A, Cin, S2);
X3 : and2 port map (B, Cin, S3);
Y2 : or3 port map (Sl, S2, SJ, Cout);
end adder;
Introduction
The name of the architecture body is adder. The entity declaration for full_add
specifies the interface ports for this architecture body. The architecture body is
composed of two parts : the declarative part (before the keyword begin) and the
statement parts (after the keyword begin). The components may either be predefined
components in a library or they may later be bound to other components in a. library.
The declared components are instantiated in the statement part of the architecture
body using component instantiation statement. Yl, Xl, X2, X3, Y2 are component
labels for this component instantiations. I1 is connected to signal A, 12 is connected to
signal B, 13 is connected to signal Cin, and 01 is connected to Sum in portmap xor3
gate. Similarly, port maps for and2 and or3 are defined. Note that in this case, the
signals in the port map of a component instantiation and the port signals in the
component declaration are associated by position. A component instantiation statement
is a concurrent statement.
1.6.4 Switch-Level Descriptions
In switch-level description the system is described using transistors which are
operated as switches. They are usually used to describe relatively small-scale digital
systems. The verilog uses keywords nmos,.pmos, cmos, tranifo, tran and tranifl to
describe the system. The VHDL does not have built-in .switch-level primitives;
however we can construct packages to include such primitives and attach them to the
VHDL module.
.... Listing 1.6 : VHDL switch-level description
library ieee ;
use ieee.std_logic_1164.all;
entity Inv la
port (X : in std_logic;
Y : out std_logic);
end Inv;
architecture Inverter of Inv la
component nmos
port (01 : out std_logic;
11, 12 : in std_logic);

Fundamentals of HDL
end component;
Component pmos
port (01 : out std_logic;
11, 12 : in std_logic);
end component;
1 . 34
·- pmos and nmos are keywords for switch level
for all : pmos use entity work.mos (pmos_behavioral);
for all: nmos use entity work.mos (nmos_behavioral);
-- above two statements refer the mos package.
constant vdd : std_logic := '1';
constant gnd: std_logic := 'O';
begin
p : pmos port map (Y, vdd, X);
n : nmos port map (Y, gnd, X);
end inverter;
.... Listing 1.7 : Verilog switch-level description
module Inv (Y, X);
inputX;
output Y;
supply 1 vdd;
supply 0 gnd;
pmos p(Y, vdd, X);
nmos n(Y, gnd, X);
endmodule
1.6.5 Mixed-Type Descriptions
Introduction
Mixed type or mixed-style descriptions use more than one type or style of the
basic styles discussed above. The listing 1.8 and 1.9 show an example of mixed type
description which uses data-flow and behavioral descriptions.
..,. Listing 1.8 : Example of VHDL mixed-type description
entity full_add is
end full_add;
architecture adder of full_add is
begin
-- data-flow description

Fundamentals of HDL
process (A, B, Cin)
begin
1 . 35
-- behavioral description
Cout < = (A and B) or (Cin and A) or (Cin and B);
end process;
end adder;
... Listing 1.9 : Example of Verilog mixed-type description
input A, B, Cin;
output Sum, Cout;
reg Sum, Cout;
assign Sum = (A " B) " Cin;
always @(A, B, Cin)
begin
11 data-flow description
11 behavioral description
Cout = (A & B) I (Cin & A) I (Cin & B);
end
endmodule
1.6.6 Mixed Language Descriptions
Introduction
Mixed language descriptions is the latest tool for HDL description in which we
can write a module or entity in one language and invoke or import a modul~ or entity
written in the other language. The listing 1.10 shows verilog module for full-adder in
which we instantiate (import) the VHDL entity HA (Half-adder).
... Listing 1.10 : Example of mixed language type description
input A, B, Cin;
output Sum, Cout;
wire CO, Cl, SO;
Half_adder Hl (A, B, SO, CO);
Half_adder H2(SO, Cin, Sum, Cl);
assign Cout =CO I Cl ;
endmodule
II Description of Half-Adder (HA) is written in VHDL
···-...

Fundamentals of HDL 1 . 36 Introduction
library ieee;
use ieee.std_logic_1164.all;
-- For correct mixing of two codes the entity name should be same, i.e., Half_adder
entity Half_adder is
port ( X, Y : in std_logic;
S, C : out std_logic);
end Half_adder;
architecture adder of Half adder is
begin
S <= A xor B;
C <=A and B;
end adder;
1.7 Simulation and Synthesis
This section explains two main applications of hardware description languages,
namely synthesis and simulation. These two are complementary design processes.
1.7.1 Synthesis
The task of designing a digital system that implements a desired functional
behaviour is referred to as the "synthesis'. Simply we can say, synthesis is the process
of generating a logic circuit from a truth table. For performing this process
automatically, synthesis CAD tools are available.
Let us see, how HDL is useful for the synthesis of a digital circuit. A HDL
program is the input to a synthesis cotnpiler. When this HDL code is passed throngh
initial synthesis tool, a lower-level description of the circuit is generated as an output.
With this process, a set of logic expressions which describes the logic functions
required to realize the circuit is produced. After this, these expressions are
manipulated further by the synthesis tools. The design entry may be in the form of
schematic capture or truth table. The logic expressions produced by the synthesis tool
are not likely to be in an optimal form. It is the task of the synthesis tool to
manipulate the user's design to produce an equivalent but better circuit automatically.
This step of synthesis process is called 'logic synthesis' or 'logic optimization'. Still the
optimized circuit is in the form of logic equations. In the last step of synthesis, it is
determined exactly, how the circuit will be realized in a specific hardware technology.
For executing this task, according to the physical resources available, it is decided how
to implement each logic function given by an expression. In this process a list of
components and their interconnections is derived from the model of a digital system
described in HDL. This list is called a 'netlist'. An integrated circuit or a layout of a
printed circuit board can be obtained by using a gate-level netlist. Thus a logic
synthesis produces a database with instructions on how to fabricate a physical piece of

Fundamentals of HDL 1. 37 Introduction
digital hardware. Logic synthesis consists of that part of a digital system design that
can be automated with computer software.
1.7.2 Simulation
In any design process, there are the basic tasks which should be performed in a
sequence. The flow-chart shown in Fig. 1.5 gives this basic sequence of tasks.
START
Initial design
Simulation
Successful design
Fig. 1.5 Basic design steps
First, the initial design is generated manually by the designer according to his
views, skills and knowledge. After this, the simulation of the design is carried out
mostly with the help of CAD tools. For the successful simulation, it is necessary to
apply adequate input conditions to the design as well as to the final product which
has to be tested. The simulator checks the designed product under the original
product specifications. This is known that what should be achieved. So if there are
errors, then those are removed and redesigned product is again simulated. This loop is
repeated until the simulation gives problem-free/error-free product. Once the designed
product performs correctly all of its functions, we call it the 'successful design'.
The operation of a digital circuit can be verified fastly and accurately using logic
simulation. There are two types of verification techniques, functional and timing.
The simulation is referred to as 'functional simulation' when all the functions of
the circuit are verified. After completion of successful functional simulation, the

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