MP_MC.pdf

B19ECT601
Microprocessors & Microcontrollers
Dr.K.Ramasamy
Dean (Academics & Research)
1

UNIT- I: 8- BIT and 16 - BIT MICROPROCESSOR
• Introduction to 8085
• 8086 Architecture
• Instruction set and programming
• Addressing modes
• Minimum and Maximum mode Configurations
• Coprocessor
• Multiprocessor.
2

Microprocessors
• A microprocessor is a controlling unit of a micro-computer,
fabricated on a small chip capable of performing Arithmetic
Logical Unit (ALU) operations and communicating with the other
devices connected to it.
• Microprocessor consists of an ALU, register array, and a control
unit. ALU performs arithmetical and logical operations on the data
received from the memory or an input device. Register array
consists of registers identified by letters like B, C, D, E, H, L and
accumulator. The control unit controls the flow of data and
instructions within the computer.
• How does a Microprocessor Work?
The microprocessor follows a sequence: Fetch, Decode, and then
Execute.
3

Architecture of 8085 Microprocessor
4

• 8085 is an 8-bit microprocessor designed by Intel in 1977
using NMOS technology.
• It has the following configuration:
• 8-bit data bus
• 16-bit address bus, which can address up to 64KB
• A 16-bit program counter
• A 16-bit stack pointer
• Six 8-bit registers arranged in pairs: BC, DE, HL
• Requires +5V supply to operate at 3.2 MHZ single phase
clock
• It is used in washing machines, microwave ovens, mobile
phones, etc. 5

8085 Microprocessor – Functional Units
Accumulator
• It is an 8-bit register used to perform arithmetic, logical, I/O &
LOAD/STORE operations. It is connected to internal data bus & ALU.
Arithmetic and logic unit
• As the name suggests, it performs arithmetic and logical operations like
Addition, Subtraction, AND, OR, etc. on 8-bit data.
General purpose register
• There are 6 general purpose registers in 8085 processor, i.e. B, C, D, E, H &
L. Each register can hold 8-bit data.
• These registers can work in pair to hold 16-bit data and their pairing
combination is like B-C, D-E & H-L.
Program counter
• It is a 16-bit register used to store the memory address location of the
next instruction to be executed. Microprocessor increments the program
counter whenever an instruction is being executed, so that the program
counter points to the memory address of the next instruction that is going
to be executed. 6

Stack pointer
• It is also a 16-bit register works like stack, which is always
incremented/decremented during push & pop operations.
Temporary register
• It is an 8-bit register, which holds the temporary data of arithmetic and logical
operations.
Flag register
• It is an 8-bit register having five 1-bit flip-flops, which holds either 0 or 1
depending upon the result stored in the accumulator.
• These are the set of 5 flip-flops −
• Sign (S)
• Zero (Z)
• Auxiliary Carry (AC)
• Parity (P)
• Carry (C)
7

Instruction register and decoder
• It is an 8-bit register. When an instruction is fetched from memory then it is stored
in the Instruction register. Instruction decoder decodes the information present in
the Instruction register.
Timing and control unit
• It provides timing and control signal to the microprocessor to perform operations.
Following are the timing and control signals, which control external and internal
circuits .
• Control Signals: READY, RD’, WR’, ALE
• Status Signals: S0, S1, IO/M’
• DMA Signals: HOLD, HLDA
• RESET Signals: RESET IN, RESET OUT
Interrupt control
• As the name suggests it controls the interrupts during a process. When a
microprocessor is executing a main program and whenever an interrupt occurs,
the microprocessor shifts the control from the main program to process the
incoming request. After the request is completed, the control goes back to the
main program. 8

Serial Input/output control
• It controls the serial data communication by using these two instructions:
SID (Serial input data) and SOD (Serial output data).
Address buffer and address-data buffer
• The content stored in the stack pointer and program counter is loaded into
the address buffer and address-data buffer to communicate with the CPU.
The memory and I/O chips are connected to these buses; the CPU can
exchange the desired data with the memory and I/O chips.
Address bus and data bus
• Data bus carries the data to be stored. It is bidirectional, whereas address
bus carries the location to where it should be stored and it is
unidirectional. It is used to transfer the data & Address I/O devices
9

Microprocessor - 8085 Pin
Configuration
10

Addressing Modes in 8085
Immediate addressing mode
• In this mode, the 8/16-bit data is specified in the instruction itself as one of its
operand. For example: MVI A, 20H: means 20H is copied into register A.
Register addressing mode
• In this mode, the data is copied from one register to another.
For example: MOV A, B: means data in register B is copied to register A.
Direct addressing mode
• In this mode, the data is directly copied from the given address to the register. For
example: LDB 5000H: means the data at address 5000H is copied to register B.
Indirect addressing mode
• In this mode, the data is transferred from one register to another by using the
address pointed by the register. For example: MOV A, M: means data is transferred
from the memory address pointed by the register pair (HL) to the register A.
Implied addressing mode
• This mode doesn’t require any operand; the data is specified by the opcode itself.
For example: CLA.
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Interrupts in 8085
• Interrupts are the signals generated by the external devices to request the microprocessor to
perform a task. There are 5 interrupt signals, i.e. TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR.
• Interrupt are classified into following groups based on their parameter −
• Vector interrupt − In this type of interrupt, the interrupt address is known to the processor.
For example: RST7.5, RST6.5, RST5.5, TRAP.
• Non-Vector interrupt − In this type of interrupt, the interrupt address is not known to the
processor so, the interrupt address needs to be sent externally by the device to perform
interrupts. For example: INTR.
• Maskable interrupt − In this type of interrupt, we can disable the interrupt by writing some
instructions into the program. For example: RST7.5, RST6.5, RST5.5.
• Non-Maskable interrupt − In this type of interrupt, we cannot disable the interrupt by
writing some instructions into the program. For example: TRAP.
• Software interrupt − In this type of interrupt, the programmer has to add the instructions
into the program to execute the interrupt. There are 8 software interrupts in 8085, i.e. RST0,
RST1, RST2, RST3, RST4, RST5, RST6, and RST7.
• Hardware interrupt − There are 5 interrupt pins in 8085 used as hardware interrupts, i.e.
TRAP, RST7.5, RST6.5, RST5.5, INTA.
• Note − INTA is not an interrupt, it is used by the microprocessor for sending
acknowledgement. TRAP has the highest priority, then RST7.5 and so on.
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Interrupt Service Routine (ISR)
• A small program or a routine that when executed, services the corresponding
interrupting source is called an ISR.
TRAP
• It is a non-maskable interrupt, having the highest priority among all interrupts.
Bydefault, it is enabled until it gets acknowledged. In case of failure, it executes as
ISR and sends the data to backup memory. This interrupt transfers the control to
the location 0024H.
RST7.5
• It is a maskable interrupt, having the second highest priority among all interrupts.
When this interrupt is executed, the processor saves the content of the PC register
into the stack and branches to 003CH address.
RST 6.5
• It is a maskable interrupt, having the third highest priority among all interrupts.
When this interrupt is executed, the processor saves the content of the PC register
into the stack and branches to 0034H address.
RST 5.5
• It is a maskable interrupt. When this interrupt is executed, the processor saves the
content of the PC register into the stack and branches to 002CH address. 13

Features of 8086 Microprocessor
• 1) The 8086 is a 16-bit microprocessor. The term “16-bit” means
that its arithmetic logic unit, internal registers and most of its
instructions are designed to work with 16-bit binary words.
• 2) The 8086 has a 16-bit data bus, so it can read data from or write
data to memory and ports either 16 bits or 8 bits at a time.
• 3) The 8086 has a 20-bit address bus, so it can directly access 220 or
10,48,576 (1Mb) memory locations. A sixteen-bit words are stored
in two consecutive memory locations.
• 4) The Features of 8086 Microprocessor can generate 16-bit I/O
address, hence it can access 216 = 65536 I/O ports.
• 5) The 8086 provides fourteen 16-bit registers.
• 6) The 8086 has multiplexed address and data bus which reduces
the number of pins needed, but does slow down the transfer of
data (drawback).
• 7) The 8086 requires one phase clock with a 33% duty cycle to
provide optimized internal timing. Range of clock rates are :- 5 MHz
for 8086; 8 MHz for 8086-2; 10 MHz for 8086-1
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• 8) The Features of 8086 Microprocessor is possible to perform bit, byte,
word and block operations in 8086. It performs the arithmetic and logical
operations on bit, byte, word and decimal numbers including multiply and
divide.
• 9) The Intel 8086 is designed to operate in two modes, namely the
minimum mode and the maximum mode. When only one 8086 CPU is to
be used in a microcomputer system, the 8086 is used in the minimum
mode of operation. In this mode the CPU issues the control signals
required by memory and I/O In multiprocessor (more than one processor
in the system) system 8086 operates in maximum mode. In maximum
mode, control signals are generated with the help of external bus
controller (8288).
• 10) The Intel 8086 supports multiprogramming. In multiprogramming,
the code for two or more processes is in memory at the same time and is
executed in a time-multiplexed fashion.
• 11) An interesting feature of the 8086 is that it fetches up to six
instruction bytes (4 instruction bytes for 8088) from memory and queue
stores them in order to speed up instruction execution.
• 12) The Features of 8086 Microprocessor provides powerful instruction
set with the following addressing modes: Register, immediate, direct,
indirect through an index or base, indirect through the sum of a base and
an index register, relative and implied.
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• The 8086 CPU is divided into two independent functional parts, the Bus interface
unit (BIU) and execution unit (EU).
• The Bus Interface Unit: contains Bus Interface Logic, Segment registers, Memory
addressing logic and a Six byte instruction object code queue. The BIU sends out
address, fetches the instructions from memory, read data from ports and memory,
and writes the data to ports and memory.
• The execution unit: contains the Data and Address registers, the Arithmetic and
Logic Unit, the Control Unit and flags. tells the BIU where to fetch instructions or
data from, decodes instructions and executes instruction. The EU contains control
circuitry which directs internal operations. A decoder in the EU translates
instructions fetched from memory into a series of actions which the EU carries out.
The EU is has a 16-bit ALU which can add, subtract, AND, OR, XOR, increment,
decrement, complement or shift binary numbers. The EU is decoding an instruction
or executing an instruction which does not require use of the buses.
• In other words the BIU handles all transfers of data and addresses on the buses for
the execution unit.
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• The Queue: The BIU fetches up to 6 instruction bytes for the following
instructions. The BIU stores these prefetched bytes in first-in-first-out
register set called a queue. When the EU is ready for its next instruction it
simply reads the instruction byte(s) for the instruction from the queue in the
BIU. This is much faster than sending out an address to the system memory
and waiting for memory to send back the next instruction byte or bytes.
• Physical address formation: The 8086 addresses a segmented memory. The
complete physical address which is 20- bits long is generated using segment
and offset registers each of the size 16-bit.The content of a segment register
also called as segment address, and content of an offset register also called as
offset address. To get total physical address, put the lower nibble 0H to
segment address and add offset address. The fig shows formation of 20-bit
physical address.
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20
Register organization of 8086:
Physical address formation
41000H
0100H
PA=41100H
--------------

Conditional Flags/Status Flags
• Carry Flag (CY): This flag indicates an overflow condition for unsigned
integer arithmetic. It is also used in multiple-precision arithmetic.
• Auxiliary Flag (AC): If an operation performed in ALU generates a
carry/barrow from lower nibble (i.e. D0 – D3) to upper nibble (i.e. D4 –
D7), the AC flag is set i.e. carry given by D3 bit to D4 is AC flag. This is
not a general-purpose flag, it is used internally by the Processor to
perform Binary to BCD conversion.
• Parity Flag (PF): This flag is used to indicate the parity of result. If
lower order 8-bits of the result contains even number of 1’s, the Parity
Flag is set and for odd number of 1’s, the Parity flag is reset.
• Zero Flag (ZF): It is set; if the result of arithmetic or logical operation is
zero else it is reset.
• Sign Flag (SF): In sign magnitude format the sign of number is indicated
by MSB bit. If the result of operation is negative, sign flag is set
• Overflow Flag: If the result exceeds 16 bit, OV is set.
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Control Flags
• Control flags are set or reset deliberately to control the operations of
the execution unit. Control flags are as follows:
• Trap Flag (TF): It is used for single step control. It allows user to
execute one instruction of a program at a time for debugging. When
trap flag is set, program can be run in single step mode.
• Interrupt Flag (IF): It is an interrupt enable/disable flag. If it is set, the
maskable interrupt of 8086 is enabled and if it is reset, the interrupt is
disabled. It can be set by executing instruction sit and can be cleared
by executing CLI instruction.
• Direction Flag (DF): It is used in string operation. If it is set, string bytes
are accessed from higher memory address to lower memory address.
When it is reset, the string bytes are accessed from lower memory
address to higher memory address.
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Microprocessor - 8086 Pin
Configuration
25

Addressing Modes
The 8086 has 12 addressing modes can be classified
into five groups.
• Addressing modes for accessing immediate and
register data (register and immediate modes).
• Addressing modes for accessing data in memory
(memory modes)
•Addressing modes for accessing I/O ports (I/O
modes)
• Relative addressing mode
• Implied addressing mode
27

1. Immediate addressing mode:
In this mode, 8 or 16 bit data can be specified as part of the instruction –
OP Code Immediate Operand
Example 1: MOV CL, 03 H:Moves the 8 bit data 03 H into CL
Example 2: MOV DX, 0525 H: Moves the 16 bit data 0525 H into DX
In the above two examples, the source operand is in immediate mode and the
destination operand is in register mode.
2. Register addressing mode:
The operand to be accessed is specified as residing in an internal register of 8086.
Example 1: MOV DX (Destination Register) , CX (Source Register) Which moves 16
bit content of CS into DX.
Example 2: MOV CL, DL
Moves 8 bit contents of DL into CL
MOV BX, CH is an illegal instruction.
The register sizes must be the same
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3.Direct addressing mode:
• The instruction Opcode is followed by an effective
address, this effective address is directly used as
the 16 bit offset of the storage location of the
operand from the location specified by the
current value in the selected segment register.
• The default segment is always DS.
• The 20 bit physical address of the operand in
memory is normally obtained as PA = DS: EA
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30
•In the direct addressing mode, the 16 bit effective address (EA)
is taken directly from the displacement field of the instruction.
Example 1: MOV CX, START
•If the 16 bit value assigned to the offset START by the
programmer using an assembler pseudo instruction such as DW
is 0040 and [DS] = 3050. Then BIU generates the 20 bit physical
address 30540 H.
The content of 30540 is moved to CL The content of 30541 is
moved to CH
Example 2: MOV CH, START
If [DS] = 3050 and START = 0040
8 bit content of memory location 30540 is moved to CH.
30500H
0040H
--------------
30540H=PA

4. Register indirect addressing mode:
• The EA is specified in either pointer (BX) register or an index (SI or
DI) register. The 20 bit physical address is computed using DS and
EA.
• Example: MOV [DI], BX
If [DS] = 5004, [DI] = 0020, [Bx] = 2456 PA=50060.
The content of BX (2456) is moved to memory locations 50060 H and
50061 H.
31

5. Based addressing mode:
• When memory is accessed PA is computed from BX and DS
when the stack is accessed PA is computed from BP and SS.
• Example: MOV AL, START [BX] or
MOV AL, [START + BX]
In based mode
• EA: [START] + [BX]
• PA: [DS] + [EA]
• The 8 bit content of this memory location is moved to AL.
32

6. String addressing mode:
• The string instructions automatically assume SI to point to
the first byte or word of the source operand and DI to point
to the first byte or word of the destination operand. The
contents of SI and DI are automatically incremented (by
clearing DF to 0 by CLD instruction) to point to the next
byte or word.
• Example: MOV S BYTE
• If [DF] = 0, [DS] = 2000 H, [SI] = 0500, [ES] = 4000,
[DI] = 0300
• Source address: PA= [DS] + [SI]=20500
• Destination address: PA=[ES] + [DI] = 40300
33

9. I/O mode (direct):
• Port number is an 8 bit immediate operand. Example: OUT 05 H, AL
• Outputs [AL] to 8 bit port 05 H
10. I/O mode (indirect):
• The port number is taken from DX. Example 1: IN AL, DX
• If [DX] = 5040
• 8 bit content from port 5040 is moved into AL.
• Example 2: IN AX, DX
• Inputs 8 bit content of ports 5040 and 5041 into AL and AH respectively.
11. Relative addressing mode:
• Example: JNC START
• If CY=O, then PC is loaded with current PC contents plus 8 bit signed value
of START, otherwise the next instruction is executed.
12. Implied addressing mode:
• Instruction using this mode has no operands.
• Example: CLC which clears carry flag to zero.
35

INSTRUCTION SET OF 8086
The 8086 instructions are categorized into the
following main types.
1.Data Copy / Transfer Instructions
2.Arithmetic and Logical Instructions
3.Shift and Rotate Instructions
4.Loop Instructions
5.Branch Instructions
6.String Instructions
7.Flag Manipulation Instructions
8.Machine Control Instructions
36

• Data Copy / Transfer Instructions:
• MOV:This instruction copies a word or a byte of data from some source to
a destination. The destination can be a register or a memory location. The
source can be a register, a memory location, or an immediate number.
• MOV AX, BX
• MOV AX, 5000H
• MOV AX, [SI]
• MOV AX, [2000H]
• MOV AX, 50H[BX]
• MOV [734AH], BX
• MOV DS, CX
• MOV CL, [357AH]
PUSH: Push to Stack
• This instruction pushes the contents of the specified register/memory
location on to the stack. The stack pointer is decremented by 2, after each
execution of the instruction.
E.g. PUSH AX
PUSH DS
PUSH [5000H]
37

POP: Pop from Stack
• This instruction when executed, loads the specified
register/memory location with the
• contents of the memory location of which the address is formed
using the current stack
• segment and stack pointer.
• The stack pointer is incremented by 2 Eg. POP AX
• POP DS
• POP [5000H]
XCHG: Exchange byte or word
• This instruction exchange the contents of the specified source and
destination operands
• Eg. XCHG [5000H], AX
38

• XCHG BX, AX
• Input and output port transfer instructions: IN:Copy a byte
or word from specified port to accumulator.
• Eg. IN AL,03H
• IN AX,DX
• OUT:Copy a byte or word from accumulator specified port.
• Eg. OUT 03H, AL
• OUT DX, AX
• LEA:Load effective address of operand in specified register.
[reg] offset portion of address in DS
• Eg. LEA reg, offset
• LDS: Load DS register and other specified register from
memory.
• [reg] [mem]
• [DS] [mem + 2]
• Eg. LDS reg, mem
39

Flag transfer instructions: LAHF:
• Load (copy to) AH with the low byte the flag register
• Eg. LAHF
• SAHF:
• Store (copy) AH register to low byte of flag register.
• Eg. SAHF
• PUSHF:
• Copy flag register to top of stack. [SP]= [SP] – 2
• [[SP]] [Flags]
• Eg. PUSHF
• POPF:
• Copy word at top of stack to flag register. [Flags] [[SP]]
• [SP]= [SP] + 2
40

Arithmetic operations:
• Addition, subtraction, negation, multiplication and comparing two
values.
ADD:
• The add instruction adds the contents of the source operand to the
destination operand.
• Eg. ADD AX, 0100H
• ADD AX, BX
• ADD AX, [SI]
• ADD AX, [5000H]
• ADD [5000H], 0100H
ADC: Add with Carry
• This instruction performs the same operation as ADD instruction,
but adds the carry flag to the result.
• Eg.
• ADC AX, BX
• ADC AX, [SI]
• ADC AX, [5000]
• ADC [5000], 0100H
41

• SUB: Subtract
• The subtract instruction subtracts the source operand from
the destination operand and the result is left in the
destination operand.
• Eg. SUB AX, 0100H
• SUB AX, BX
• SUB AX, [5000H]
• SUB [5000H], 0100H
• SBB: Subtract with Borrow
• The subtract with borrow instruction subtracts the source
operand and the borrow flag (CF) which may reflect the
result of the previous calculations, from the destination
operand
• Eg. SBB AX, 0100H
• SBB AX, BX
• SBB AX, [5000H]
• SBB [5000H], 0100H
42

• INC: Increment
• This instruction increases the contents of the specified Register or
memory location by
• Eg. INC AX
• INC [BX]
• INC [5000H]
• DEC: Decrement
• The decrement instruction subtracts 1 from the contents of the
specified register or memory location.
• Eg. DEC AX
• DEC [5000H]
• NEG: Negate
• The negate instruction forms 2’s complement of the specified
destination in the instruction. The destination can be a register or a
memory location. This instruction can be implemented by inverting
each bit and adding 1 to it.
• Eg. NEG AL
• AL = 0011 0101 =35H Replace number in AL with its 2’s complement
AL = 1100 1011 = CBH
43

• CMP: Compare
• This instruction compares the source operand, which
may be a register or an immediate data or a memory
location, with a destination operand that may be a
register or a memory location
• Eg. CMP BX, 0100H
• CMP AX, 0100H
• CMP [5000H], 0100H
• CMP BX, [SI]
• CMP BX, CX
• MUL:Unsigned Multiplication Byte or Word
• This instruction multiplies an unsigned byte or word by
the contents of AL.
• Eg. MUL BH; (AX)= (AL) x (BH)
• MUL CX; (DX)(AX) =(AX) x (CX) 44

• IMUL: Signed Multiplication
• This instruction multiplies a signed byte in source operand by a signed
byte in AL or a signed word in source operand by a signed word in AX.
• Eg. IMUL BH
• IMUL CX
• CBW: Convert Signed Byte to Word
• This instruction copies the sign of a byte in AL to all the bits in AH. AH is
then said to be sign extension of AL.
• Eg. CBW
• AX= 0000 0000 1001 1000 Convert signed byte in AL signed word in AX.
Result in AX = 1111 1111 1001 1000
• CWD: Convert Signed Word to Double Word
• This instruction copies the sign of a byte in AL to all the bits in AH. AH is
then said to be sign extension of AL.
• Eg. CWD
45

• DIV: Unsigned division
• This instruction is used to divide an unsigned word by a byte or to
divide an unsigned double word by a word.
• Eg. DIV CL; Word in AX / byte in CL; Quotient in AL, remainder in AH
• DIV CX; Double word in DX and AX / word; in CX, and Quotient in
AX; remainder in DX
• AAA: ASCII Adjust After Addition
• The AAA instruction is executed after an ADD instruction that adds
two ASCII coded operand to give a byte of result in AL. The AAA
instruction converts the resulting contents of AL to a unpacked
decimal digits.
• Example1: ADD CL, DL; [CL] = 32H = ASCII for 2; [DL] = 35H = ASCII
for 5; Result [CL]= 67H
MOV AL, CL; Move ASCII result into AL since AAA adjust only [AL]
AAA; [AL]=07, unpacked BCD for 7
46

• Example2:
• Addition of two one digit ASCII coded number
will not be ASCII. To convert the result to
ASCII, we use AAA after ADD instruction.
47

• AAS: ASCII Adjust AL after Subtraction
• This instruction corrects the result in AL
register after subtracting two unpacked ASCII
operands. The result is in unpacked decimal
format. The procedure is similar to AAA
instruction except for the subtraction of 06
from AL.
48

• AAM: ASCII Adjust after Multiplication
• This instruction, after execution, converts the product available In AL into
unpacked BCD format.
• Eg. MOV AL, 04; AL = 04
• MOV BL ,09; BL = 09
• MUL BL; AX = AL*BL; AX=24H
• AAM; AH = 03, AL=06
• AAD: ASCII Adjust before Division
• This instruction converts two unpacked BCD digits in AH and AL to the equivalent
binary number in AL. This adjustment must be made before dividing the two
unpacked BCD digits in AX by an unpacked BCD byte.
• In the instruction sequence, this instruction appears Before DIV instruction.
• Eg. AX 05 08
• AAD result in AL 00 3A 58D = 3A H in AL
• The result of AAD execution will give the hexadecimal number 3A in AL and 00 in
AH where 3A is the hexadecimal Equivalent of 58 (decimal).
• DAA: Decimal Adjust Accumulator
• This instruction is used to convert the result of the addition of two packed BCD
numbers to a valid BCD number. The result has to be only in AL.
• Eg. AL = 53; CL = 29
• ADD AL, CL; AL= (AL) + (CL); AL =53 + 29; AL =7C
• DAA; AL =7C + 06 (as C>9); AL=82
49

• DAS: Decimal Adjust after Subtraction
• This instruction converts the result of the
subtraction of two packed BCD numbers to a
valid BCD number. The subtraction has to be
in AL only.
• Eg. AL = 75, BH = 46
• SUB AL, BH; AL =2F = (AL) - (BH)
• DAS; AL =29 (as F>9, F - 6 = 9)
50

Logical instructions
• Eg. AND AX, 0008H
• AND AX, BX
• OR: Logical OR
• Eg. OR AX, 0008H
• OR AX, BX
• NOT: Logical Invert
• This instruction complements the contents of an operand register or a
memory location, bit by bit.
• Eg. NOT AX
• Eg. XOR AX, 0098H
• XOR AX, BX
• TEST: Logical Compare Instruction
• The TEST instruction performs a bit by bit logical AND operation on the
two operands.
• The result of this ANDing operation is not available for further use, but
flags are affected.
• Eg. TEST AX, BX
• TEST [0500], 06H
51

52
Shift and Rotate Instructions
SHL/SHR destination, count: Logical Shit
SHL:This instruction shifts each bit in the specified destination to the left and 0 is stored at
LSB position. The MSB is shifted into the carry flag. The number of shifts is indicated by
count.
Eg. SHL CL, 1
SHL AX, CL
SHR: SHR destination, count
This instruction shifts each bit in the specified destination to the right and 0 is stored at
MSB position. The LSB is shifted into the carry flag. The number of shifts is indicated by
count.
Eg. SHR CX, 1
MOV CL, 05H
SHR AX, CL
SAR: SAR destination, count: Arithmetic Shift
This instruction shifts each bit in the specified destination some number of bit positions to
the right. As a bit is shifted out of the MSB position, a copy of the old MSB is put in the
MSB position. The LSB will be shifted into CF.
Eg. SAR BL, 1
MOV CL, 04H
SAR DX, CL
ROL Instruction: ROL destination, count
This instruction rotates all bits in a specified byte or word to the left some number of bit
positions. MSB is placed as a new LSB and a new CF.
Eg. ROL CL, 1 MOV CL, 03H ROL BL, CL
CY CL7 CL6 CL5 CL4 CL3 CL2 CL1 CL0
CL7 CL6 CL5 CL4 CL3 CL2 CL1 CL0 CY

• ROR Instruction: ROR destination, count
• This instruction rotates all bits in a specified byte or word to the right
some number of bit positions. LSB is placed as a new MSB and a new CF.
• Eg. ROR CL, 1
• MOV CL, 03H
• ROR BL, CL
• RCL Instruction: RCL destination, count
• This instruction rotates all bits in a specified byte or word some number of
bit positions to the left along with the carry flag. MSB is placed as a new
carry and previous carry is place as new LSB.
• Eg. RCL CL, 1
• MOV CL, 04H
• RCL AL, CL
• RCR Instruction: RCR destination, count
• This instruction rotates all bits in a specified byte or word some number of
bit positions to the right along with the carry flag. LSB is placed as a new
carry and previous carry is place as new MSB.
• Eg. RCR CL, 1
• MOV CL, 04H
• RCR AL, CL
53

Loop Instructions:
• Unconditional LOOP Instructions LOOP: LOOP
Unconditionally
• This instruction executes the part of the program from
the Label or address specified in the instruction upto
the LOOP instruction CX number of times. At each
iteration, CX is decremented automatically and JUMP IF
NOT ZERO structure.
• Example: MOV CX, 0004H
• Conditional LOOP Instructions LOOPZ / LOOPE Label
• Loop through a sequence of instructions from label
while ZF=1 and CX=0.
• LOOPNZ / LOOPNE Label
• Loop through a sequence of instructions from label
while ZF=1 and CX=0.
54

Branch Instructions:
• Branch Instructions transfers the flow of execution of the program
to a new address specified in the instruction directly or indirectly.
When this type of instruction is executed, the CS and IP registers
get loaded with new Values of CS and IP corresponding to the
location to be transferred.
• The Branch Instructions are classified into two types
1. Unconditional Branch Instructions.
2. Conditional Branch Instructions.
Unconditional Branch Instructions:
• CALL: Unconditional Call
1. Near CALL i.e., ±32K displacement.
2. For CALL i.e., anywhere outside the segment.
55

• RET: Return from the Procedure.
• INT N: Interrupt Type N.
• In the interrupt structure of 8086, 256 interrupts are
defined corresponding to the types from 00H to FFH. When
INT N instruction is executed, the type byte N is multiplied
by 4 and the contents of IP and CS of the interrupt service
routine will be taken from memory block in 0000 segment.
• INTO: Interrupt on Overflow
• This instruction is executed, when the overflow flag OF is
set. This is equivalent to a Type 4 Interrupt instruction.
• JMP: Unconditional Jump
• IRET: Return from ISR
56

Conditional Branch Instructions
JZ/JE Label
Transfer execution control to address ‘Label’, if ZF=1.
JNZ/JNE Label
Transfer execution control to address ‘Label’, if ZF=0
JS Label
Transfer execution control to address ‘Label’, if SF=1.
JNS Label
Transfer execution control to address ‘Label’, if SF=0.
JO Label
Transfer execution control to address ‘Label’, if OF=1
JNO Label
Transfer execution control to address ‘Label’, if OF=0.
JNP Label
Transfer execution control to address ‘Label’, if PF=0.
JP Label
Transfer execution control to address ‘Label’, if PF=1.
JB Label
Transfer execution control to address ‘Label’, if CF=1.
JNB Label
Transfer execution control to address ‘Label’, if CF=0.
JCXZ Label
Transfer execution control to address ‘Label’, if CX=0
57

String Manipulation Instructions
• The 8086 supports a set of more powerful instructions
for string manipulations for referring to a string, two
parameters are required.
I. Starting and End Address of the String.
II. Length of the String.
• The length of the string is usually stored as count in the
CX register. The incrementing or decrementing of the
pointer, in string instructions, depends upon the
Direction Flag (DF) Status. If it is a Byte string
operation, the index registers are updated by one. On
the other hand, if it is a word string operation, the
index registers are updated by two.
58

• REP: Repeat Instruction Prefix
• This instruction is used as a prefix to other instructions, the instruction to
which the REP prefix is provided, is executed repeatedly until the CX
register becomes zero (at each iteration CX is automatically decremented
by one).
• i. REPE / REPZ - repeat operation while equal / zero.
• ii. REPNE / REPNZ - repeat operation while not equal / not zero. These
are used for CMPS, SCAS instructions only, as instruction prefixes.
• MOVSB / MOVSW: Move String Byte or String Word
• CMPS: Compare String Byte or String Word
• SCAN: Scan String Byte or String Word
• LODS: Load String Byte or String Word
• STOS: Store String Byte or String Word
• The STOS instruction Stores the AL / AX register contents to a location in
the string pointer by ES: DI register pair. The DI is modified accordingly, No
Flags are affected by this instruction.
• The direction Flag controls the String instruction execution, The source
index SI and Destination Index DI are modified after each iteration
automatically. If DF=1, then the execution follows auto decrement mode,
SI and DI are decremented automatically after each iteration. If DF=0, then
the execution follows auto increment mode. In this mode, SI and DI are
incremented automatically after each iteration.
59

Flag Manipulation and a Processor
Control Instructions
The Flag manipulation instructions directly modify some of the Flags of 8086.
i. CLC – Clear Carry Flag.
ii. CMC – Complement Carry Flag.
iii. STC – Set Carry Flag.
iv. CLD – Clear Direction Flag.
v. STD – Set Direction Flag.
vi. CLI – Clear Interrupt Flag.
vii. STI – Set Interrupt Flag.
Machine Control instructions
• The Machine control instructions control the bus usage and execution
i. WAIT – Wait for Test input pin to go low.
ii. HLT – Halt the process.
iii. NOP – No operation.
iv. ESC – Escape to external device like NDP
v. LOCK – Bus lock instruction prefix.
60

• Minimum mode: Single processor mode where 8086 generates all necessary
control signals directly
• MN/MX!=1
• 8086, Latches, Transceivers, Clock generator, memory and I/O devices
• Minimum mode signals:
• INTA!: Recognition of interrupt request
• ALE: Enables latch to separate address & data bits
• DEN!: Informs transceiver that CPU is ready to send/receive data
• DT/R!: Transmit/Receive data
• M/IO!: Data transfer is between CPU & memory or I/O
• WR!: Write operation
• HLDA!: Bus grant signal for DMA operation
• HOLD: Bus request signal for DMA operation
• Latch: 74LS373: Separates address from multiplexed address/data signals
• Controlled by ALE signal generated by 8086
• Address is latches & is available only during earlier part of cycle
63

• Transceiver: 74245
• Bidirectional buffers/data amplifiers
• Separates data from multiplexed address/data signals
• Controlled by DEN!, DT/R!
• DEN! Indicates that valid data is available on data lines
• DT/R! indicates the direction of data transfer
• Clock generator: 8284
• Generates clock signal from crystal oscillator
• Synchronizes external signals with system clock
• Provides Reset signal
• Wait state logic
• It provides clock, Ready & Reset to 8086
64

• Memory & I/O devices:
• M/IO!, RD! and WR!: Specify the type of data
transfer: Memory read, Memory write, IO
read & IO write
65

Maximum mode configuiration
66

• MN/MX!=0
• Multiprocessor mode: 8086, 8087/8089
• 8086 does not generate control signals directly.
Bus controller 8288 is used to generate control
signals
• 8288 uses S0, S1, S2 to indicate the current
machine cycle
• Maximum mode signals:
• QS1, QS0: indicates the status of instruction
Queue
67

S0!Si!S2!: Indicate type of current machine cycle
• 000 Interrupt acknowledge
• 001 IO read
• 010 IO write
• 011 Halt
• 100 Instruction fetch
• 101 Memory read
• 110 Memory write
• 111 Passive (Inactive)
68

• LOCK!: Bus is reserved by one processor & is not available
for other processor in multiprocessor mode
• RQ!/GT1!: Bus request/Grant Low priority
• RQ!/GT0!: Bus request/Grant High priority
• Bus controller: 8288
• Derives control signals (RD!, WR!) for memory and IO
devices, DEN!, DT/R!, ALE, INTA! etc.
• Input to 8288: S0!, S1!, S2!, CLK
• AIOWC, AMWC: Advanced IO write, Memory write: Similar
to IOWC! And MWTC except that they are activated one
clock cycle earlier. This gives slow interfaces an extra clock
cycle to prepare to input data.
69

Multiprocessor Systems
• Multiprocessor Systems refer to the use of multiple processors that
execute instructions simultaneously and communicate using
mailboxes.
• Maximum mode of 8086 is designed to implement 3 basic
multiprocessor configurations:
1. Coprocessor (8087)
2. Closely coupled (dedicated I/O processor: 8089)
3. Loosely coupled (Multi bus)
• Coprocessors and closely coupled configurations are similar - both
the CPU and the external processor share: Memory, I/O system, Bus
& bus control logic & Clock generator.
• In both configurations 8086 is the master or host & the supporting
processor is the slave.
70

Coprocessor Configuration:
• For complex applications, 8086 is not sufficient. It should be supplemented with
coprocessors. 8086 has no instructions for performing floating point arithmetic.
So by using 8087 as a coprocessor, an application that heavily involves floating
point calculations can be readily satisfied.
• Both 8086 and 8087 execute their instructions from the same program
• 8086 performs opcode fetch cycles and identify the instructions for 8087. Once
8086 identifies the instruction of 8087, it is allotted to 8087 for further execution.
• After the completion of 8087 execution cycle, the results will be referred back to
8086
• ESC instruction:
• ESC opcode, operand
• opcode: instruction opcode: determines the action to be taken by the coprocessor
• When the CPU executes the ESC instruction, the processor accesses the memory
operand by placing the address on the address bus.
• Possible to have 2 coprocessors.
• WAIT instruction: It allows the processor to synchronize itself with external
hardware, eg., waiting for 8087 math co-processor.
• BUSY pin of 8087 is connected to TEST! Pin of 8086. When 8087 is busy in
executing some instructions, it pulls BUSY high, so TEST! signal is also high and
now 8086 is made to WAIT until BUSY signal goes low. When 8087 completes
execution of its instruction, BUSY signal goes low & hence TEST! signal also goes
low and now only 8086 goes for execution of its program.
• WAIT instruction repeatedly checks TEST! pin until it becomes activated and then
executes the next instruction in sequence.
71

Synchronization between the 8086 and its
coprocesssor:
• If a coprocessor is configured to share the system
bus, it will recognize the ESC instruction and
therefore will get the opcode and the operand.
72

Closely (Tightly) Coupled Configuration
• Coprocessor cannot take control of the bus, it does everything through the
CPU
• Closely Coupled processor may take control of the bus independently -
8089 shares CPU’s clock and bus control logic.
• Independent processor: 8089: Executes its own instruction system
• Instead of using ESC and WAIT instructions, communication with host CPU
is by way of shared memory to minimize the cost.
• Host (8086) sets up a message (command) in memory
• Independent processor interrupts host on completion or setup status bit
in the shared memory space.
73

Interprocessor communication through shared memory
74

Loosely Coupled Configurations:
• Here number of modules of 8086 can be interfaced through a common
system bus to work as a multiprocessor system.
• A loosely coupled configuration provides the following advantages:
1. High system throughput can be achieved by having more than one
CPU.
2. The system can be expanded in a modular form. Each bus master
module is an independent unit and normally resides on a separate
PC board. Therefore, a bus master module can be added or removed
without affecting the other modules in the system.
3. A failure in one module normally does not cause a breakdown of the
entire system and the faulty module can be easily detected and
replaced.
4. Each bus master may have a local bus to access dedicated memory or
I/O devices so that a greater degree of parallel processing can be
achieved. More than one bus master module may have access to the
shared system bus
Extra bus control logic must be provided to resolve the bus arbitration
problem. The extra logic is called bus access logic and it is its responsibility to
make sure that only one bus master at a time has control of the bus.
Simultaneous bus requests are resolved on a priority basis: There are three
schemes for establishing priority:
75

Bus allocation schemes
• Simultaneous bus requests are resolved on a priority basis:
Daisy chaining:
• Simplest, cheapest scheme
• No priority resolving network is needed
• Singe bus request line for requesting for the bus
• Controller sends bus grant signal if bus busy signal is inactive. It
goes through all masters in sequence till it reaches a requesting
master
• The master then gains the control of bus, activates bus busy line &
starts using it
• Priority is decided by the position of the requesting master in the
sequence.
• Less HW; response time is high; failure of one module causes hole
system to fail.
78

Polling method:
• Controller uses address lines to address each master in
sequence
• When the BR is received by the controller from a
device, it generates the address on the address lines. If
the generated address matches that of the requesting
master, controller activates the BUSY line.
• Once BUSY line is activated, controller stops generating
further address.
• Priority can be dynamically changed by changing the
polling sequence stored in the controller.
79

Independent bus request scheme:
• It resolves priority in a parallel fashion
• Each module has a separate BR & BG lines & a priority
assigned to it
• Controller has a priority encoder, which selects the request
with highest priority & returns the corresponding BG signal.
• BUSY line is common to all the masters
• Arbitration is fast & independent of no of modules in the
system
• Fast because each master communicates with controller
independently
• It requires BR & BG lines (2n lines for n modules)
80

Chapter 2
Peripherals & Interfacing
• 8255-PPI
• 8279-KBDC
• ADC 0808, DAC 0808
• 8254-PIT
• 8259-PIC
• 8251-SCI
• 8257-DMAC
1

8255-Programmable Peripheral
Interface-PPI
• PPI 8255 is a general purpose programmable I/O
device designed to interface the CPU with its
outside world such as ADC, DAC, keyboard,
Display etc.
• We can program it according to the given
condition. It can be used with almost any
microprocessor.
• It consists of three 8-bit bidirectional I/O ports
i.e. PORT A, PORT B and PORT C grouped to
Group A & Group B.
2

• Data bus buffer: Tristate bidirectional buffer;It
is used to interface 8255 with the system bus
• Read/Write control logic: It accepts control
signals (RD, WR..) and issues commands to
Group A & Group B control blocks.
• Group A & Group B control blocks: Accept
control from CPU & issues command to the
ports
4

The common applications of 8255 are:
• Traffic light control
• Generating square wave
• Interfacing with KB, Display, DC motors and stepper motors
To communicate with peripherals through 8255 three steps are necessary:
• Determine the addresses of Port A, B, C and Control register according to
Chip Select Logic and the Address lines A0 and A1.
• Write a control word in control register.
• Write I/O instructions to communicate with peripherals through port A, B,
C.
Modes of operation of 8255:
Input/Output mode
• Mode 0: Simple I/O mode
• Mode 1: I/O mode with handshake
• Mode 2: Bidirectional data transfer mode
BSR mode (Bit Set/Reset mode)
5

I/O Modes of 8255
Mode 0: Simple Input or Output
• In this mode, Port A and Port B are used as two simple 8-bit I/O ports and
Port C as two 4- bit I/O ports. Each port (or half-port, in case of Port C) can
be programmed to function as simply an input port or an output port.
• The input/output features in mode 0 are: Outputs are latched, Inputs are
not latched. Ports do not have handshake or interrupt capability.
Mode 1: Input or Output with handshake
• In mode 1, handshake signals are exchanged between the microprocessor
and peripherals prior to data transfer.
• The ports (A and B) function as 8-bit I/O ports. They can be configured
either as input or output ports. Each port (Port A and Port B) uses 3 lines
from port C as handshake signals. The remaining two lines of port C can
be used for simple I/O functions. Input and output data are latched and
Interrupt logic/handshake facility is supported.
• Mode 2: Bidirectional Data Transfer
• This mode is used primarily in applications such as data transfer between
the two computers or floppy disk controller interface. Port A can be
configured as the bidirectional port and Port B either in mode 0 or mode
1.
• Port A uses five signals from Port C as handshake signals for data transfer.
The remaining three lines from Port C can either as simple I/O or as
handshake signals for Port B.
8

8251-USART (Universal Synchronous
Asynchronous Receiver Transmitter)
9

• Programmable chip designed for synchronous
& asynchronous serial data transmission
• Converts parallel data into serial stream of bits
suitable for serial transmission
• Receives serial stream of bits & convert into
parallel data bytes to be read by
microprocessor
10

Modem control:
• It handles the modem handshake signals to coordinate the
communication between the modem and USART.
• It establishes data communication through modem over telephone
lines
• DSR!: To check if the data set is ready when communicating with a
modem. Its status is checked by CPU using a status read operation
• DTR!: To indicate that the device is ready to accept data when the
8251 is communicating with a modem
• RTS!: To indicate the modem that the receiver is ready to receive a
data byte from the modem. This is used to communicate with a
modem.
• CTS!: If this is low, the 8251 is enabled to transmit the serial data.
16

Operating Modes of 8251
1. Asynchronous mode
2. Synchronous mode
Two types of control words:
• Mode Instruction control word: Mode instruction is used for setting the function
of the 8251.
• Command Instruction control word: Command is used for setting the operation of
the 8251. It is possible to write a command whenever necessary after writing a
mode instruction and sync characters.
17
Mode instruction format-Asynchronous.

18
Synchronous - mode Instruction format
1: External Synchronization
0: Internal Synchronization

20
Status information
It is possible to see the internal status of the 8251 by reading a status word.
The bit configuration of status word is shown in Fig.

8254-Programmable Interval Timer/Counter
21

• Generates accurate time delay
• Performs event counting, square wave generator
• Has 3 independent 16 bit presettable down counters (BCD or hexadecimal)
• It has 3 counters each with two inputs (Clock and Gate) and one output.
Gate is used to enable or disable counting. When any value of count is
loaded and value of gate is set (1), after every clock, value of count is
decremented by 1 until it becomes zero.
Depending upon the value of CS, A1 and A0 we can determine addresses
of selected counter.
• Data is transmitted or received by the buffer on executing IN or OUT
instructions
• The read/write logic controls the direction of the data buffer depending
upon whether it is a read or a write operation
• 8253can operate in any one of the six different modes. A control word
must be written in the respective control word register by the
microprocessor to initialize each of the counters of 8254 to decide its
operating mode. All the counters can operate in any one of the modes or
they may be even in different modes of operation, at a time.
22

• Mode 0 (Interrupt on terminal count)
• Mode 1 (Programmable one shot)
• Mode 2 (Rate generator)
• Mode 3 (Square wave generator)
• Mode 4 (Software triggered strobe)
• Mode 5 (Hardware triggered strobe)
25

• Mode 0: Interrupt on TC:
• The output is initially low after the mode is set. The output
remains low even the count is loaded into the counter.
• After the falling edge of the clock, counter starts
decrementing the count value, if the GATE input is high.
• The counting process continues till the TC is reached. When
the TC is reached, OUT goes high & remains HIGH till the
count register is reloaded with a new mode or a new count.
• The high OUT can be used to interrupt the processor.
• When the GATE goes low, counting is terminated & the
current count is latched till the GATE goes high again.
26

Mode 1: Programmable one shot:
• Used as monostable multivibrator
• The GATE input is used as trigger input
• Initially output remains high till the count is
loaded into the count register and a trigger is
applied. After the application of positive edge
trigger (GATE), output goes low and remains
low till the count becomes zero.
28

Mode 2: Rate generator:
• Rate generator or divide by N counter
• If N=4 is loaded into the counter, after 4
pulses, the output becomes low only for one
clock cycle. Count N is reloaded again and
again.
30

Mode 3: Square wave generator:
• Used as a Square wave generator
• If the count N is even, then for half of the
count (N/2 pulses) the output remains high
and for remaining N/2 pulses it remains low.
• If the count N is odd, then for (N+1)/2 pulses,
output remains high & for (N-1)/2 pulses,
output remains low. It is repeated to generate
square wave.
32

Mode 4: Software Triggered Strobe:
• After the mode is set, the output goes high.
When a count is loaded, counting down starts.
On TC, the output goes low for one clock cycle
& then goes high. This low pulse can be used
as a strobe, when peripherals are interfaced
with microprocessor.
• When the GATE goes low, count is inhibited &
the count value is latched.
34

Mode 5: Hardware Triggered Strobe:
• Initially the OUT is high. The counting is triggered
by the rising edge of the GATE. When initial count
is expired the OUT becomes low for one clock
pulse, then high again. After writing the control
word and the initial count, the counter will not be
loaded until clock pulse after one trigger.
In Software triggered strobe mode, the trigger is
given internally by the software whereas in
hardware triggered mode the trigger has to be
given externally by hardware.
36

8279 Programmable Keyboard/Display Controller
38

 It consists 4 main sections:
1. CPU interface and control section.
2. Scan section
3. Keyboard Section
4. Display section.
 CPU INTERFACE AND CONTROL SECTION:
It consists of
1. Data buffers
2. I/O control
3. Control and timing registers.
4. Timing and control logic. 39

Data Buffers:
 8-bit bidirectional buffer.
 Used to connect the internal data bus and external
data bus.
I/O control:
 I/O control section uses the A0,CS!,RD! and WR! signals
to controls the data flow.
 The data flow is enabled by CS!=0 otherwise it is the
high impedance state.
 A0=0 means the data is transferred.
 A0=1 means status or command word is transferred.
40

41
I/O control signals listed below
TIMING AND CONTROL REGISTERS:
Store the keyboard and display modes and others operating condition
programmed by the CPU.
The modes are programmed by sending proper command A0=1.
TIMING AND CONTROL:
It consists of timing counter
First counter is divided by N prescalar that can be programmed to give an
internal frequency of 100 KHz.

Scan Section
It has two modes:
1. Encoded mode
2. Decoded mode.
ENCODED MODE:
 It is externally decoded to provide 16 scan lines
 It provides binary count from 0000 to 1111 by
four scan lines(SC3-SC0) by active high inputs.
42

 Display section uses all 16 scan lines to interface 16 digit 7
segment display. These 16 scan lines are connected to the
digit drivers.
 But keyboard use only 8 scan lines out of 16 lines. These 8
scan lines are connected to 8 rows of the KB. So 8*8 KB can
be interfaced.
DECODED MODE:
 In this mode, the internal decoder decodes the least 2
significant bits & It provides four possible combination
from (SL0-SL3)
 This four active low outputs line is used to directly to
interface 4 –digit 7-segment display, 8*4 matrix keyboard
43

Keyboard section
This is consist of
 Return buffers.
 Keyboard debounce control.
 FIFO / sensor RAM.
 FIFO / sensor RAM status.
RETURN BUFFERS:
 8 return lines (RL7-RL0) are connected to the 8 columns of
the keyboard.
 In strobed mode ,the contents of return lines are
transferred to FIFO RAM.
44

KEYBOARD DEBOUNCE AND CONTROL:
 It is enabled only when keyboard mode is selected.
 In this mode , return lines are scanned whether any
keys are closed in the row.
 If debounce circuit detects any closed switch, it waits
about 10 msec.
 It is continued , the key code along with the status of
SHIFT and CONTROL keys are transferred into RAM.
FIFO/SENSOR RAM:
 This is a dual function of 8*8 RAM.
45

 The 8279 generates an interrupt signal when
there is an entry in FIFO.
 Each new entry is written into successive RAM
position and read in the order of entry.
FIFO/SENSOR RAM status:
 This is used to tell the status of FIFO/SENSOR
RAM.
 The status of logic also makes IRQ signal is High ,
When FIFO is empty.
46

Display section:
It consists of
1. Display RAM.
2. Display Address registers.
3. Display registers.
DISPLAY RAM:
 It is a 16*8 RAM.
 Which stores 16 digits display codes.
 It can be accessed by CPU directly.
47

DISPLAY ADDRESS REGISTERS:
 Used to hold address of the byte currently written or
read by the CPU and scan count value.
 In auto increment mode, address in the register is
automatically incremented for each write or read.
DISPLAY REGISTERS:
 Two 4-bit registers such as A and B.
 They hold the bit patterns of character to be displayed.
 The content of display registers A and B can be blanked
and inhibited individually during digit switching (BD!).
48

Operating modes
1. Input modes.
2. Display modes.
INPUT MODES:
 It is basically 3 types,
1. Scanned keyboard.
2. Scanned sensor matrix.
3. Strobed mode.
SCANNED KEYBOARD:
Key board can be scanned in two ways.
1.Encoded Scan
2.Decoded Scan.
49

ENCODED SCAN:
In this scan, scan lines (SL2-SL0) are decoded
externally to provide 8 scan lines.
Additionally it provides 8 return lines.
So the size of matrix keyboard is 8*8 (i.e Scan *
Return)=64.
When the key is pressed , it stores the status of
return lines, Scan lines, SHIFT and CNTL/STB keys
into FIFO RAM.
The Scanned keyboard structure is
50
DECODED SCAN:
In this mode, internal decoder decodes the two least significant bits of scan
lines (SL3-SL0).
So the maximum size of keyboard is 8*4=32.

2-KEY LOCKOUT:
In this mode, the two key depression is not
allowed.
When two keys are depressed almost at the
same time, the first key will be detected,
debounced & decoded. Then the status of key
code is entered into FIFO RAM along with the
status of CNTL and SHIFT lines.
Second key press will be missed.
51

N-KEY ROLLOVER:
Each key is recognized, debounced & detected
independently from all others.
All the pressed keys will be detected,
debounced & decoded independently.
52

Display modes:
It is basically two types
1. Left entry (Type writer mode).
2. Right entry (Calculator mode).
LEFT ENTRY:
 In this mode , 8279 display characters from left to
right.
 Like a typewriter.
AUTO INCREMENT IN LEFT ENTRY:
 In left entry mode , Auto increment flag is set; after
each operation, display RAM address is incremented.
53

RIGHT ENTRY:
 In this mode , 8279 display characters from
Right to left.
 Like a Calculator.
AUTO INCREMENT IN RIGHT ENTRY:
 In right entry mode, Auto increment flag is
set; after each operation display RAM
address is incremented.
54

8259-Programmable Interrupt Controller
55

The Interrupt Request Register (IRR):
An 8-bit register in which the active interrupt requests are stored. Whenever
activation of an interrupt request input is done, the bit corresponding in
IRR register is set to 1. For example, if we activate the IR4 and IR6 inputs,
bits no 4 and 6 of IRR are set to 1 by making the contents of IRR as
01010000. But the processor is designed only to read the contents of this
register but cannot write it to IRR.
The interrupt Mask Register (IMR):
• This register is used to disable (mask) or enable (unmask) individual
interrupt inputs. Each bit in this register corresponds to the interrupt
input with the same number. We can unmask an interrupt input by
sending a command word with a 0 in the bit position that corresponds to
that input.
The In Service Register (ISR):
• The ISR keeps track of which interrupt inputs are currently being
serviced. For each input that is currently being serviced, the
corresponding bit will be set in the ISR.
The Priority Resolver:
It examines all the three registers and set the priority of interrupts and
according to the priority of the interrupts, interrupt with highest priority is
selected for service. Hence it sets an appropriate bit in ISR register. Also, it
resets the interrupt level which is already been serviced in IRR.
56

Interrupt Sequence in 8086:
1. One or more of the INTERRUPT REQUEST lines are raised high, setting the
corresponding IRR bit(s).
2. The 8259A evaluates these requests, and sends an INT to the CPU, if
appropriate.
3. The CPU acknowledges the INT and responds with an INTA! pulse.
4. Upon receiving an INTA! from the CPU, the highest priority ISR bit is set,
and the corresponding IRR bit is reset. The 8259A will also release a CALL
instruction code onto the 8-bit Data Bus through its Data pins.
5. This CALL instruction will initiate two more INTA! pulses to be sent to the
8259A from the CPU.
6. These two INTA! pulses allow the 8259A to release its 16 bit subroutine
address onto the Data Bus. The lower 8-bit address is released at the first
INTA! pulse and the higher 8-bit address is released at the second INTA!
pulse.
7. This completes the 3-byte CALL instruction released by the 8259A. In the
AEOI mode, the ISR bit is reset at the end of the third INTA! pulse.
Otherwise, the ISR bit remains set until an appropriate EOI command is
issued at the end of the interrupt subroutine.
57

8259A Interrupt Operation:
• To implement interrupt, the interrupt enable flip-flop in
the microprocessor should be set by writing the EI
instruction and the 8259A should be initialized by writing
control words in the control register.
• The 8259A requires two types of control words:
(a) Initialization Command Words (ICWS)
(b) Operational Command Words (OCWs)
• ICWs are used to initialize & to set up the proper
conditions and specify RST vector address.
• The OCWs are used to perform functions such as masking
interrupts, setting up status-read operations etc.
58

Initialization Command Words (ICWs):
• There are four initialization command words (ICWs) for the 8259A
that are selected when A0 pin is logic one. If a single 8259A is used
in a system, ICW1, ICW2,
ICW3 and ICW4 must be programmed.
• If cascade mode is used in a system, then all four ICWs must be
programmed.
• ICW1: Programs the basic operation of 8259A. To program this ICW
for 8086-Pentium 4 operation, place a logic 1 in bit IC4. Bits ADI, A7,
A6, A5 are don’t care for microprocessor operation and only apply
to the 8259A when used with an 8-bit 8085 microprocessor.
• This ICW1 selects single or cascade operation by programming the
SNGL bit. The LTIM bit determines whether the interrupt request
inputs are positive edge-triggered or level-triggered.
59

Operation Command Words (OCWs):
• Once 8259 is initialized, it is ready for
processing interrupts. The operational
command words (OCWs) are used to direct
the operation of the 8259A in desired mode
once it is programmed with ICW.
• 3 OCWS: OCW1, OCW2 & OCW3 are needed
to operate 8259 in the initialized mode.
62

ADC interfacing
• ADC is an input device to microprocessor & is interfaced
with microprocessor using ports of 8255.
• 2 ADC techniques: Successive approximation
& dual slope integration techniques
Algorithm:
1. Apply stable analog input to ADC using Sample & Hold
circuit
2. Apply SOC (Start Of Conversion) pulse by microprocessor
to the ADC
3. Read EOC (End Of Conversion) pulse by microprocessor
4. Read digital data output of ADC by the microprocessor
63

Features:
• Internal circuits perform zero & full scale adjustment
• Conversion time: 100microsec
• 8 channels; one can be selected using address lines
(Select lines) A, B & C.
• Unipolar ADCs; able to convert only negative analog
voltage to their equivalent digital
• 8 bit successive approximation ADC
• Eliminates need for external zero & full scale
adjustment
65

• Clock input is given
• Port A of 8255 is used to transfer digital data of ADC to
8086 & Port C is used to transfer control signals
• Analog input is given to I/P2 of ADC
• Through Port B, 8086 sends select signals (ABC), to
select I/P2
• ABC=010 to select I/P2 of ADC
• OE & ALE pins are kept at +5V to select ADC & enable
the outputs
• PC lower acts as output port to send SOC to ADC;
PC upper receives EOC
67

Interfacing ADC0808 with 8086
68

• When DAC is enabled, it converts digital input
given through PA to analog
• The analog output from DAC is current
• It is converted to voltage using OP-AMP based
I to V converter
• The output of DAC is fed to OP-AMP to get the
final output.
70

Features of 8257
• It has four channels which can be exhibited over four
I/O devices.
• Each channel has 16-bit address and 14-bit counter
registers
• Data transfer of each channel can be taken up to 64kb.
• Each channel can be programmed independently.
• Each channel can perform certain specific actions i.e,
DMA read, DMA write and DMA verify operations.
• It requires a single phase clock.
• Its frequency ranges from 250Hz to 3MHz.
72

• The DMA controller in a sense is a second processor in the
system but is dedicated to an I/O function
• DMA Channels: 8257 has 4 independent DMA channels
(CH0 to CH3), hence four I/O devices can request for DMA
simultaneously.
• Each channel consists of two 16-bit registers:
(i) Address register (ii) Count Register.
• Address register holds the starting address of the memory
block to be accessed by I/O device.
• Count register holds the number of bytes to be transferred
during DMA action.
• The low order 14-bits of count register specify the number
of bytes; therefore each channel can support data transfer
of 214=16KB during DMA process.
• The high order 2-bits of count register specify the mode of
operation (read, write or verify)
73

• Data Bus Buffer: This 8-bit Bidirectional buffer is
used to interface the 8257 to the system Data
Bus. It allows the transfer of data and information
between 8257 and microprocessor.
• Read/Write Control Logic: 8257 operates in two
basic modes, master mode and slave mode. In
the slave mode, read/write logic accepts the or
signal. In the master mode, read/write logic
generates and for DMA write cycle or and for
DMA read cycle.
74

• Priority Resolver: This logic block determines the priorities
of the channels when more than one I/O device request for
DMA. By default CH0 has the highest priority while the CH3
has lowest. In rotating priority, the priority of the channels
has a circular sequence. The channel which has being just
serviced move to the lowest priority and channel next to it
move to the highest priority, hence each channel achieves
the highest priority in rotation.
• Control Logic: In the master mode, Control logic controls
the sequence of operation during DMA cycles (DMA read,
DMA write & DMA verify). It also generates required
control signals and memory address to be accessed.
• It increments 16-bit address register and decrement count
register of corresponding channel during DMA action.
75

Sequence of operations performed by a DMA :
• Primarily, when any device requires to send data between
the device and the memory, the device need to send DMA
request (DRQ) to DMA controller.
• The DMA controller sends Hold request (HRQ) to the CPU
and waits for the CPU to assert the HLDA signal.
• Then the microprocessor tri-states all the data bus, address
bus, and control bus. The CPU leaves the control over bus
and acknowledges the HOLD request through HLDA signal.
• when the CPU is in HOLD state with the HOLD request, the
DMA controller has to control the operations over buses
between the CPU, memory, and I/O devices.
76

8051 MICROCONTROLLER
1. 8051 – Architecture
2. Special Function Registers (SFRs)
3. Instruction set
4. Addressing modes
5. Assembly language programming
6. I/O Ports
7. Timers/counters
8. Interrupts and
9. Serial communication
1

Features of 8051
• 8 bit Microcontroller
• 8 bit CPU
• 128 bytes on-chip data memory (RAM)
• 4KB bytes on-chip program memory (ROM)
• Four register banks (Bank 0,1,2 & 3)
• 32 general purpose registers each of 8-bit.
• 21 SFRs
• 128 user defined software flags (1 bit register).
• 8-bit bidirectional data bus.
• 16-bit unidirectional address bus.
• 16 bit Timers (usually 2, but may have more or less)
• Clock frequency: 11.0592MH
3

Special Function Registers
7
•PCON (Power Control Register)
•TMOD (Timer Mode Register)

8051 Addressing modes
1. Immediate Addressing:
• Data is immediately available in the instruction.
For example-
• ADD A,#77H; Adds 77(decimal) to A and stores in A
• ADD A,#4DH; Adds 4D(hexadecimal) to A and stores in A
MOV DPTR,#1000H; Moves1000(hexadecimal) to data pointer
2. Register Addressing:
• Data is available in the register specified in the instruction. The
register bank is decided by 2 bits of Processor Status Word.
For example-
• ADD A,R0; Adds content of R0 to A and stores in A
9

3. Direct Addressing:
• The address of the data is available in the instruction. For example-
MOV A,88H;Moves content of SFR TCON (address is 88H) to A
4. Register Indirect Addressing:
• The address of data is available in the R0 or R1 registers as specified in the
instruction.
• For example-MOV A, @R0; moves content of memory location whose
address is pointed by R0 to A.
5. External Data Addressing:
• Pointer used for external data addressing can be either R0/R1 (256 byte
access) or DPTR (64kbyte access). For example-
• MOVX A,@R0;Moves content of external RAM memory location whose
address in R0 to A
• MOVX A,@DPTR; Moves content of external RAM memory location whose
address is pointed by DPTR to A 10

6. External Code Addressing:
• Sometimes we may want to store non-volatile data in
to the ROM e.g.look-uptables. Such data may require
reading the code memory. This may be done as
follows:
• MOVC A,@A+DPTR; Moves content of External ROM
memory location whose address is pointed by A+DPTR
to A
• MOVC A,@A+PC; Moves content of External ROM
memory location whose address pointed by A+PC to A
11

Instruction Set of 8051
8051 Instructions are grouped into:
• Arithmetic Instructions
• Logical Instructions
• Data Transfer instructions
• Boolean Variable (Bit manipulation)Instructions
• Program Branching Instructions
14

Assembly language programming
Program to add 79, F5, E2 & store the result in R0 & R5
MOV A, #00
MOV R5,A
ADD A, #79H
JNC LOOP1
INC R5
LOOP1: ADD A, #F5H
JNC LOOP2
INC R5
LOOP2: ADD A, #E2H
JNC OVER
INC R5
OVER: MOV R0, A
15

• Program to add 2 numbers:
MOV DPTR, #4500
MOVX A, @DPTR
MOV R0,A
MOV R1, #00
INC DPTR
MOVX A, @DPTR
ADD A, R0
JNC LOOP1
INC R1
LOOP1: INC DPTR
MOVX @DPTR,A
INC DPTR
MOV A,R1
MOVX@DPTR,A
16

• Program to subtract 2 numbers:
MOV A, #Data1
SUBB A, #Data2
MOV DPTR, #4500
MOVX @DPTR, A
17

• Program to MULTIPLY 2 numbers:
MOV A, #Data1
MOV B, #Data2
MUL AB
MOV DPTR, #4500
MOVX @DPTR,A
INC DPTR
MOV A,B
MOVX @DPTR,A
18

• Program to DIVIDE 2 numbers:
MOV A, #Data1
MOV B, #Data2
DIV AB
MOV DPTR, #4500
MOVX @DPTR,A
INC DPTR
MOV A,B
MOVX @DPTR,A
19

• The four 8-bit I/O ports P0, P1, P2 and P3 each uses 8
pins. All the ports upon RESET are configured as output,
ready to be used as input ports.
• Port 0 is also designated as AD0-AD7, allowing it to be
used for both address and data. When connecting an
8051 to an external memory, port 0 provides both
address and data. The 8051 multiplexes address and
data through port 0 to save pins.
• ALE indicates if P0 has address or data.
When ALE=0, it provides data D0-D7
When ALE=1, it has address A0-A7
21

• In 8051-based systems with no external memory
connection. Both P1 and P2 are used as simple I/O.
• In 8051-based systems with external memory
connections, Port 2 must be used along with P0 to
provide the 16-bit address for the external memory.
• P0 provides the lower 8 bits via A0 – A7 & P2 is used
for the upper 8 bits of the 16-bit address, designated as
A8 – A15, and it cannot be used for I/O
• Port 3 can be used as input or output.
• Port 3 does not need any pull-up resistors. Port 3 has
the additional function of providing some extremely
important signals.
22

8051 Timer/Counter
• In 8051, there are two 16-bit timer registers.
These registers are known as Timer0 and Timer1.
• The timer registers can be used as Timer or
Counter.
TMOD (Timer Mode) Register
• Both Timer 0 and Timer 1 use the same register
to set the various timer operation modes. It is an
8-bit register in which the lower 4 bits are set
aside for Timer 0 and the upper four bits for
Timer 1. In each case, the lower 2 bits are used to
set the timer mode.
24

25
•GATE: Every timer has a means of starting and stopping. 8051 timers have both
software and hardware controls. The SETB instruction is used to start it and it is
stopped by the CLR instruction. These instructions start and stop the timers as long
as GATE = 0 in the TMOD register.
•Timers can be started and stopped by an external source by making GATE = 1 in
the TMOD register.
•C/T!: This bit in the TMOD register is used to decide whether a timer is used as
a delay generator or an event manager/counter.
M1 M2 Mode
0 0 13-bit timer mode.
0 1 16-bit timer mode.
1 0 8-bit auto reload
mode.
1 1 Spilt timer mode.

Mode 0 (13-Bit Timer Mode)
• Timer register is configured as a 13-bit register consisting of all the 8 bits
of TH1 and the lower 5 bits of TL1. The upper 3 bits of TL1 should be
ignored. The timer interrupt flag TF1 is set when the count rolls over from
all 1s to all 0s.
Mode 1 (16-Bit Timer Mode)
• Timer mode "1" is a 16-bit timer and is a commonly used mode. It
functions in the same way as 13-bit mode except that all 16 bits are used.
Mode 2 (8 Bit Auto Reload)
• Both the timer registers are configured as 8-bit counters (TL1 and TL0)
with automatic reload. Overflow from TL1 (TL0) sets TF1 (TF0) and also
reloads TL1 (TL0) with the contents of TH1 (TH0), which is preset by
software. The reload leaves TH1 (TH0) unchanged.
Mode 3 (Split Timer Mode)
• When Timer 0 is placed in mode 3, it becomes two separate 8-bit timers.
Timer 0 is TL0 and TH0. Both the timers count from 0 to 255 and in case of
overflow, reset back to 0.
• When Timer 1 is in split mode, TH1 and TL1 can be set in modes 0, 1 or 2,
but it cannot be started/stopped as the bits that do that are now linked to
TH0. The real timer 1 will be incremented with every machine cycle.
26

27
Mode 0
Mode 1
Mode 2
Mode 3

28
Set/Cleared by HW
Set/Cleared by HW
Set/Cleared by SW
Set/Cleared by SW
TCON Register:

8051 Serial Port
• Serial port in 8051 transfers/receives bits serially at different baud
rate (9600, 4800, 2400 & 1200) & is programmable using T1.
• T1 is programmed in mode2 (8bit auto reload mode) to generate
different baud rate
• TxD, RxD: Transmits/Receives data serially
• XTAL OSCR frequency=11.0592MH
• Timer clock=XTAL OSCR frequency/12
• Registers related to Serial port communication
• SBUF Register: 8 bit register used in serial communication; When a
byte is written in SBUF, framing is done & transmitted serially over
TxD. When serial bits are received over RxD line, deframing is done
& stores the byte in SBUF.
• SCON Register
• PCON Register
30

Writing to the Serial port:
• MOV SBUF, #A: 8051 transmits character A through TxD;
After transmitting A, TI is set. After that next character will
be transmitted.
CLR TI
MOV SBUF, #A
$:JNB TI, $; wait until TI is set
The above 3 instructions will successfully transmit a character
A & wait for TI bit to be set to continue.
Reading the Serial port:
$:JNB RI, $; wait for 8051 to set RI
MOV A, SBUF; Read the character from the serial port
36

PCON Register:
• When 8051 is powered, SMOD bit =0.
• By setting SMOD, the baud rate can be doubled.
MOV A, PCON
SETB ACC.7
MOV PCON,A
• Idle mode (IDL): Clock to CPU is disabled; peripheral clock is active,
CPU status is protected & the power drawn in this mode is 15% of
full power.
• Power down mode (PD): Onchip oscillator is stopped (both CPU &
peripheral clocks), device draws only 10microA current, reduces
power consumption
• GF0, GF1: General purpose flags
37

Examples for Serial port programming
1. Write a program for the 8051 to transfer letter “A” serially at 4800
baud rate continuously.
MOV TMOD, #20H Timer 1, mode 2 (auto reload); 0010 0000
MOV TH1, #-06 4800 baud rate; FAH
MOV SCON, #50H 8 bit, 1 start, 1 stop, REN enabled; 0101 0000
SETB TR1 start timet 1
AGAIN: MOV SBUF, #”A” letter “A” to be transmitted
HERE: JNB TI, HERE wait for last bit
CLR TI clear TI for next character
SJMP AGAIN keep sending “A”
38

2. Write a program for the 8051 to receive bytes of data serially, and put
them in P1. Set the baud rate at 4800, 8 bit data and 1 start and 1 stop
bit.
MOV TMOD, #20H Timer 1, mode 2 (auto reload); 0010 0000
MOV TH1, #-6 4800 baud rate
MOV SCON, #50H 8 bit, 1 start, 1 stop, REN enabled; 0101 0000
SETB TR1 start timet 1
HERE: JNB RI, HERE wait for character to come in
MOV A, SBUF save incoming byte in A
MOV P1, A sent to port 1
CLR RI get ready to receive next byte
SJMP HERE keep getting data
39

MICROCONTROLLER BASED
SYSTEM DESIGN
•Interfacing to: matrix display, (16x2) LCD
•High power devices
•Optical motor shaft encoder
•Stepper Motor, DC Motor speed Control using PWM
•RTC and EEPROM interface using I2C protocol.
1

Interfacing dot matrix LED display to
8051 microcontroller.
LED dot matrix display.
• An LED dot matrix display consists of a matrix of LED’s arranged in a
rectangular configuration. The desired character or graphics can be
displayed by switching ON /OFF a desired configuration of LED’s.
• Common display configurations available are 7×5, 8×8, 7×15, etc.
LED dot matrix can be used in simple display applications where the
resolution is not a big concern.
• The figure below shows the arrangement of LEDs in a typical 7×5
dot matrix display.
• Any individual LED or a group of LEDs in the matrix can be activated
by switching the required number of rows and columns. For
example, in the above figure, if Row1 is made high and Column1 is
made low, the top left LED (address R1C1) will glow.
• As a demonstration, lets see how we can display letter “A” using the
display. The table given below shows the logic levels at each pin for
displaying A.
2

3
Typical 7×5 dot matrix display.
The logic levels at each pin
for displaying A.

Interfacing dot matrix LED display and 8051
• The circuit diagram for interfacing dot matrix display and
8051 microcontroller is shown above. In the above circuit
diagram you can see that only one LED in a row will be ON
at a time but any number of LEDs in a column can be ON at
a time. That means the microcontroller’s port pin can
directly drive a row but it requires additional circuit for
driving the column lines.
• The purpose of ULN2003A here is to drive the column lines
of the display. ULN2003A is a high voltage (50V), high
current (500mA per channel) Darlington transistor array.
Each IC has 7 channels with individual output clamp diodes.
ULN2003A an active high device, which means a logic high
must be applied to the input to make the corresponding
output high.
5

LCD interfacing
Advantages:
• Declining prices of LCDs
• Ability to display numbers, characters &
graphics, where as in LEDs only numbers &
few characters can be displayed.
• Refreshing controller is there into the LCD,
hence CPU is relieved.
• Ease of programming for characters & graphics
6

Interfacing LCD display and 8051
7

• D0-D7: Data pins used to send information to LCD or read the
contents of LCD’s internal registers.
• RS :Register Select
• 0: Selects Instruction command register
User can send a command such as clear display, cursor at home,
decrement/increment cursor. Shift display/cursor right/left, display
off/on, cursor on/off etc.
• 1: Selects Data register
Data can be transferred to LCD display
• R/W!: 1: Read data from LCD display
0: Write data to LCD display
• EN: Enable the Latch to latch the information presented to its
data pins
• VCC/VEE : Controls LCD contrast
9

• A relay is a switch that enables a microcontroller to control
high power external devices. It is a gateway that takes a
control signal from microcontroller, but sources the power
signal from a high power source. It makes the two signals
work in tandem to allow the controller to control high
powered appliances.
• Relay helps to provide electrical isolation between two
circuits (power circuit & control circuit) which is very
important in the case of microcontrollers.
• Due to the electrical isolation properties and high load-
carrying capacity of the relays, they are used to control high
power external devices like fans, lights and motors.
• There are two types of relays:
Electromechanical relays
Solid-state relays
10
Interfacing to high power devices

• An electromechanical relay consists of an electromagnet,
which, when energized, moves the metal armature. The
armature is connected to the normally closed contact
when the electromagnet is not energized. Once energized
the electromagnet pulls the armature to the normally open
contact which completes the circuit driving an external
device.
• A solid-state relay, in contrast to the electromechanical
relay, does not have any movable parts. Due to this reason,
solid-state relays have a faster switching time and higher
life cycles when compared to electromagnetic relays.
• Solid-state relays use optocouplers instead of
electromagnets to provide electrical isolation and control.
In the case of DC output devices, solid-state relays use
silicon-controlled rectifiers with the optocouplers whereas,
in the case of AC loads, they use a TRIAC or thyristors
11

8051 Interfacing to high power devices
12

• The Figure shows the solution specific to the
8051 microcontroller. A darlington transistor is
used to activate relays because of its high current
gain. It is necessary that logic one activation is
applied since the output current is then very low
(pin acts as an input).
• In order to prevent the self-induction of high
voltage, caused by a sudden stop of current flow
through the coil, an inverted polarized diode is
connected in parallel to the coil. The purpose of
this diode is to “cut off” the voltage peak.
13

Interfacing optical motor shaft encoder
• Encoder is a circular device in the form of disk that provides a digital
output in response of a movement.
• Optical Encoders are mainly used to measure the angular or linear
displacement, position, velocity, acceleration and direction of movement
of rotors, shafts particularly in machine tools, robots, rotary machines,
and translational systems etc.,
• Principle: An optical encoder is a device, that converts motion or any
movement into a sequence of encoded pulsed digital signals by
modulating (coding) the continuous optical signals from a light source.
• The light source is received by a photo detector through a slotted disk
containing coded patterns called track. By counting or decoding these bits
and the pulses can be converted into relative or absolute position
measurements. The number of pulses is being proportional to the position
of the disk. The number of the pulses per second determines the velocity
of the disk.
• Classification of Optical Encoders may be classified as follows:
1. Linear Encoder
2. Rotary Encoder:
a) Incremental Encoder b) Absolute Encoder
14

• Incremental Encoder: An incremental encoder provides a
simple pulse by which each time the object to be measured
has moved a certain distance. This encoder comparatively
produces digital pulses as the shaft rotates, for the
measurement of relative displacement of the shaft.
• Incremental encoder is also called as relative Encoder that
detects changes in rotation from some reference position.
• Principle of operation: When a beam of light passes
through slots in a disc, it is detected by a suitable light
sensor placed opposite to the light source. When the disk is
rotated, a pulsed output is produced by the sensor with the
number of pulses being proportional to the position of the
disk and the number of pulses per second determines the
velocity of the disk.
15

• It consists of primarily three components: a light source, a coded disk and
a photo detector. A coded wheel is a specially designed rotating disk made
of plastic or glass containing code patterns called track.
• The pattern or track on the disk consists of alternate appearance of
opaque and transparent segment and the pattern is circular. The coded
wheel is mounted between the light source and a photo detector. The light
source used here is light emitting diode (LED) to provide continuous light
signal. A photo diode or photo transistor is commonly used as a photo-
detector. The position of these three components should be such that
their line of action must be same. The disk is rigidly fixed with the rotor or
shaft. When the opaque section of the coded disk passes in front of the
light, the detector does not receives any signal and hence no output.
Conversely, when the transparent section of the coded disk passes in front
of the light, the detector receives light signal from the light source and
hence there is an output.
• Under these design criteria, if the disc is made to rotate, the photo
detector will receive pulsed light signal for every time it sees the light
source i.e. the LED. The photo detector converts the light signal into
electrical signal.
• The result is a series of signals corresponding to the rotation of the wheel.
By using a counter to count these signals, it is possible to find out how far
the wheel has rotated. Velocity information can be obtained by
differencing the pulses.
17

DC Motor speed Control using PWM
• DC motor converts electrical energy in the form of Direct Current
into mechanical energy.
• In the case of the motor, the mechanical energy produced is in the
form of a rotational movement of the motor shaft.
• The direction of rotation of the shaft of the motor can be reversed
by reversing the direction of Direct Current through the motor.
• The motor can be rotated at a certain speed by applying a fixed
voltage to it. If the voltage varies, the speed of the motor varies.
• Thus, the DC motor speed can be controlled by applying varying DC
voltage; whereas the direction of rotation of the motor can be
changed by reversing the direction of current through it.
• For applying varying voltage, we can make use of the PWM
technique.
• For reversing the current, we can make use of H-Bridge circuit or
motor driver ICs that employ the H-Bridge technique or any other
mechanisms.
18

19
• For construction and interfacing of DC motor,
refer the class notes.

Stepper Motor Interfacing
• Used in control area, position control system (dot matrix
printer, disk driver & Robotics etc.)
• PM rotor: shaft which is surrounded by a stator
• Rotor moves in steps
• Common stepper motor has 4 stator windings (4 phase
stepper motor)
• Step angle: Minimum degree of rotation with a single step
• No. of steps/revolution= 360deg/step angle
• If step angle=2deg; No. of steps/revolution=180
• No. of applied pulses determine the no. of rotations
• To change the direction of rotation, change the pulse
sequence
• To change RPM (Speed), change pulse repetition frequency
20

22
When 8051 outputs 0, a coil is energized, current is stored in the coil. When 8051
outputs 1, the coil is deenergized & we need to provide a path for the stored
current to flow through. Hence a diode is connected in reverse bias for the current
to flow through. The diode is called as free wheeling/flyback diode.

Program to rotate stepper motor
continuously in clock wise direction:
START: MOV R0, #04 ; Initialize count for No. of step sequence
MOV DPTR, #TABLE ; Initialize the memory pointer
RPT: MOVX A, @DPTR ; Get the 1st step from A register
MOV P1, A ; Send it to port1 to which SM is interfaced
ACALL DELAY ; Call delay
INC DPTR
DJNZ R0, RPT
SJMP START
TABLE: DB 09 05 06 0A
DELAY: MOV R2, #64H
L1: MOV R3, #FFH
L2: DJNZ R3, L2 ; Repeat the procedure
DJNZ R2, L1
RET
23

RTC interface using I2C protocol
• RTC (Real Time Clock) is an electronic device
which plays an essential role in real time embedded
system design. It provides a precise time and date in
various applications such as system clock, student
attendance system and alarm etc, that keep track on
current time and provides consistent result to the
respective task.
• RTC interfacing with 8051 microcontroller is similar to
all other kinds of “Real Time Clocks” interfaced to it.
So let us look on simple RTC interfacing with 8051
microcontroller and programming procedure involving
in it.
24

Step1: Select RTC Device
Let us look on simple RTC interfacing with 8051
microcontroller and programming procedure involving
in it.
Step2: Internal Register and Address of the RTC Device
• RTC provides years, months, weeks, days, hours,
minutes and seconds based on crystal frequency.
• RTC consists of inbuilt RAM memory for data storage.
• A battery backup will be provided in case of failure of
main power supply by connecting a battery to RTC
device.
26

Step3: Interfacing RTC DS1307 with 8051
• RTC can be interfaced to by using different serial bus
protocols such as I2C protocols that provide
communication link between them.
• The figure shows real time clock interfacing with 8051
microcontroller using I2C bus protocol.
• I2C is a bi-directional serial protocol, which consist of
two wires such as SCL and SDA to transfer data
between devices connected to bus.
• 8051 microcontroller has no inbuilt RTC device
therefore we connect externally through a serial
communication for ensuring the consisting data.
• I2C devices have open drain outputs therefore, a pull-
up resistors must be connected to the I2C bus line with
a voltage source. If the resistors are not connected to
the SCL and SDL lines, the bus will not work.
27

Step4: RTC Data Framing Format
• Since RTC interfacing with 8051
microcontroller uses I2C bus, the data transfer
is in the form of bytes or packets and each
byte is followed by an acknowledgement.
Step5: RTC Programming
28

31
• For interfacing of RTC using I2C refer the class
notes.

EEPROM interface using I2C protocol
• The following figure shows interfacing I2C-EEPROM with 8051
microcontroller. Here, I2C is a master- slave protocol, that includes the data
along with clock pulse. Typically, the master device switched the clock
line, SCL. This line orders the data timing which transfers on the I2C bus.
Unless the clock is operated, no data will be transferred. All slaves are
controlled by the same clock, SCL.
32

• I2C bus supports the various devices where each device is
identified by a unique address whether it is an LCD driver,
memory card, microcontroller or interfacing of
keyboard which can operate as Tx or Rx depends on the
functioning of the device.
• The controller is designed to control the EEPROM device via
I2C protocol. Here, the I2C protocol works as a master
device and regulates EEPROM which works as a slave.
• The R/W operations are proficient by transferring a set of
control signals comprising the address AND/ OR data bus.
These signals should be attended with suitable clock signals
33

Interface I2C Bus-EEPROM with 8051 Microcontroller
• If you want to read, Write and Erase EEPROM by using I2C bus in
8051 striker board. Interfacing of I2C Bus-EEPROM with 8051
microcontroller is very simple. The operation of this interfacing is to
send a signal like WRITE, followed by data and address bus. In this
operation, the EEPROM is used to store the data. In 8051 kit, two
numbers of EEPROM lines are regulated by I2C supported drivers.
The SCL and SDA are connected to the I2C based serial EEPROM IC.
• By using SDA and SCL, I2C lines, the read and write operations of
EEPROM are done in 8051 Slicker Kit
• The interfacing of I2C is so simple and in every single data
Read/Write in EEPROM. The delay depends on compiler how it
enhances the loops as soon as you make changes in the choices the
delay varies.
34

35
• For interfacing of EEPROM refer the class
notes.

32- BIT ARM PROCESSOR
•RISC Vs CISC Architecture
•ARM Processor Architecture
•ARM Core data flow model
•Barrel Shifter
•ARM processor modes and families
•Pipelining
•ARM instruction Set and its Programming.
1

RISC (Reduced Instruction Set Computer) CISC (Complex Instruction Set Computer)
Very fewer instructions are present. The
number of instructions are generally less
than 100.
A large number of instructions are
present in the architecture.
No instruction with a long execution time
due to very simple instruction set. Some
early RISC machines did not even have an
integer multiply instruction, requiring
compilers to implement multiplication as
a sequence of additions.
Some instructions with long execution
times. These include instructions that
copy an entire block from one part of
memory to another and others that copy
multiple registers to and from memory.
Fixed-length encodings of the instructions
are used.
Example: In IA32, generally all
instructions are encoded as 4 bytes.
Variable-length encodings of the
instructions.
Example: IA32 instruction size can range
from 1 to 15 bytes.
Simple addressing formats are supported.
Only base and displacement addressing is
allowed.
Multiple addressing formats are
supported for specifying operands. A
memory operand specifier can have many
different combinations of displacement,
base and index registers.
2
RISC Vs CISC Architecture

RISC CISC
RISC does not supports array. CISC supports array.
Arithmetic and logical operations only use
register operands. Memory referencing is
only allowed by load and store
instructions, i.e. reading from memory
into a register and writing from a register
to memory respectively.
Arithmetic and logical operations can be
applied to both memory and register
operands.
Implementation programs exposed to
machine level programs. Few RISC
machines do not allow specific instruction
sequences.
Implementation programs are hidden
from machine level programs. The ISA
provides a clean abstraction between
programs and how they get executed.
No condition codes are used. Condition codes are used.
Registers are being used for procedure
arguments and return addresses.
Memory references can be avoided by
some procedures.
The stack is being used for procedure
arguments and return addresses.
3

Applications ARM processors :
• ARM processors are specifically used in High end
portable devices like digital cameras, mobile
phones, home networking modules and wireless
communication technologies and other
embedded systems due to the benefits, such as
high code density, low power consumption,
smaller silicon area, reasonable performance
MIPS (several million instructions per second)
etc.
4

• ARM processor is Based on RISC architecture
• High code density, low power consumption as well as low and smaller
silicon footprint. Silicon footprint is the amount of space a particular
unit of hardware or software occupies.
RISC Architecture has got a large uniform register file and it is basically
a load-store architecture where data processing operations are only
with registers and does not really involve memory locations.
• It is basically 32 bit processor, but we will find the variants of that as
well. In fact we have got ARM processors which can support both 32
bit as well as 16 bit operations.
• Bit processor. Thumb extensions of ARM architecture.
• ARM Processors have got a barrel shifter in the data path which can
maximize the usage of hardware available on chip.
• Then there is an auto increment and auto decrement addressing
modes to optimize program loops. This is not very common with RISC
processors.
• Also it supports load and store of multiple data elements through a
single instruction and subsequently we will find that there is an
interesting set of branch instructions. In these branch instructions,
they are not just individual branch instructions but this branching can
be used in conjunction with other operations. So, we have got a large
variety of branching possibilities and these has also been used to
maximize the execution throughput.
5

• There are various variations of this architecture, in
fact the whole idea is that this architecture has
undergone a number of versions and these versions
have been implemented into number of processors
having distinct identities and numbers.
• Four such versions, version 1, version 2, version 3,
version 4
• Initially version 1 the processor was a 26 bit
addressing processor, it had no multiply or provision
for core processors.
• The version 2 really made a 32 bit addressing mode.
• Version 3 really made it into a 32 bit addressing
register capable and included multiply as an option.
• PIC, like other simple micro-controllers simply support
add and subtract operations. Here, in this instructions
set itself we have got multiply. In fact we shall see also
variations of multiply in the instruction set of all.
6
Variants of ARM Architecture

• In fact version 4 was characterized by enhanced set of instruction
and in version 4 itself they introduced what is called the thump
mode and this version is called version 4T which included a 16 bit
mode. Now, this 16 bit mode obviously implies that given the cell
memory if we can use 16 bit instructions we can pack additional
instructions.
• So, we can use this effectively same memory for more instructions
and thereby we can increase code density. And this is particularly
useful when we really do not require 32 bit operations. And this
embedding of a 16 bit variant inside the 32 bit architecture came
in version 4T is for thumb.
• ARM instructions are 32 bits wide, and Thumb instructions are 16
wide. Thumb mode allows for code to be smaller, and can
potentially be faster if the target has slow memory.
• Then we have got version 5T which is superset of 4T adding new
instructions
• The version 5TE add its signal processing instructions. In fact the
instruction which are targeted for signal processing applications
into the basic set. In fact this is again are departure from classical
RISC concept.
7

• Now, these architectures have been implemented into a variety of
chips. So, there are some examples, ARM6 actually implements
version 3.
• ARM7 which is a very popular ARM version implements version 3
but another variant of this ARM7 which is ARM7TDMI, this actually
implements version 4T, that means it has got a thump embedded
into the basic processor.
• The Strong ARM is version 4 implementation, but this
implementation is from Intel and not from ARM implemented. In
fact it has been the point I was making that ARM core that has been
licensed to a number of manufactures and they have taken the
basic core, done the appropriate modifications and designed
processors for various targeted applications. The example is Strong
ARM here, which Intel head made around the ARM core targeted
for again embedded applications. ARM 9E-S this example is an
implementation of the version 5TE that is extension architecture
which implements digital signal processing instructions set and it
is thought primarily targeted for embedded system which need to
process lots of digital signals like speech, video etc.
8

Barrel shifter
• First thing is any architecture is characterized by its data
path as well as by the control path. Our current focus will
be on data path and we shall try to understand the
instruction set of ARM with reference to this core data
path.
• This data path is organized in such a way that the operands
are not directly fetched from memory because that is the
basic feature of a RISC. So the operands are typically stored
in the register file and instruction typically use 2 source
registers and single result or destination registers wherever
required in the operations involving 3 registers. If the
operation involves just 2 registers then obviously the third
register will not be there.
• There is a barrel shifter on the data path which can
preprocess data before it enters ALU.
9

• Barrel shifter is basically a combinational circuit which
can shift the data bits to the left or to the right by
arbitrary number of positions in the same cycle itself.
• In a classical shift registers involving flip flops the
number of shifts require the equivalent number of
clock cycles because a shifting takes place on the basis
of clock. But here it is a combinational circuit so that
the shift takes place in one clock cycle itself. In fact
the shift takes place in the same instruction cycle.
This is very basic enhancement in the ARM data path.
• The other interesting feature is the increment and
decrement logic which can operate on the registers
independent of the ALU. So, we have got a facility for
implementation of what we call auto increment and
auto decrement addressing modes. In fact this is not
uncommon with CISC processors but this has been
brought in ARM to facilitate certain operations that is
particularly block move kind of operations and that
way it is an enhancement on the key RISC model. 10

ARM Core Data path:
• There is a register bank which is connected to the ALU
where two data parts one is A bus, another data part is B
bus and this B bus goes via the Barrel shifter.
• So, this Barrel shifter can actually preprocess the data
which can come from one of this source registers; and the
Barrel shifter can shift to the left, shift to the right or even
rotate the data before it is fed to the ALU.
• Basically, ALU & Barrel shifter are combinational circuits.
So, all the operations that is operation that ALU carries
out as well as operation that Barrel shifter carries out can
take place in one cycle itself and that actually splits up the
operation & improves execution speed/performance.
11

• We can use the register bank for generation of the address as well. In fact the PC
also is part of the register bank and that can generate the address. As well as the
other register banks can be made useful for generation & for manipulation of
address. Because registers are in a way symmetric they can have both address as
well as the data. The PC generates the address for the instruction. Now here, we
have not indicated whether it would be a Harvard or VanNeuman architecture
typically. So, what we are concentrating primarily here is the data path.
• The incremental block, this incremental block enables us to decrement or
increment the register values independent of the ALU. In fact the PC value can be
incremented and put back to the registers so on and so forth. Other operations
can also be done with the registers using the incremental block.
• There is an instruction decode & control to decode/translate the instruction and
generate the control signals for the operation.
• There is an address bus is 0 to 31 that means it is a 32 bit. Data buses are also 32
bits, so it is basically a 32 bit processor. It can operate on 32 bit operands and the
addresses that it generates are also 32 bit.
• Since the registers can handle data and address in a symmetric fashion it is very
easy to handle same number of bits for address and data and use the similar kind
of operations for manipulating addresses and data in the registers.
• Now, let us look at the register bank because we are found that in the data path
this register bank has a very prominent role.
12

• Fixed length instruction
• Pipelined
• Load/Store architecture
• 32 bit architecture
• Most ARM implements 2 types of instruction
sets (32 bit & 16 bit (Thumb mode)
14

ARM Core Data flow model
15
The Von Neumann architecture:
Both data & instructions use
the same bus.

ARM core Processor
• RISC Architecture
• Use Load Store architecture
• Load instruction copy data from memory to
registers
• Store instruction copy data from registers to
memory
• No data processing instructions that directly
manipulate data in memory; hence data
processing is carried out in registers
16

Elements of ARM core Processor
• Instruction decoder: Translates instructions before they are executed
• Register file: for computation & manipulation purposes; storage bank of
32 bit registers; 16 registers r0 to r15
• Sign extend: Registers hold signed or unsigned 32 bit values. This unit
converts signed 8 bit and 16 bit numbers accessed from memory to 32 bit
numbers to place in registers
• Barrel shifter
• MAC: Multiply Accumulate unit: Take register values Rn and Rm from A &
B buses and compute the result. Data processing instruction will write
result in Rd to result file.
• ALU: Load & Store instruction use ALU to generate address to be held in
address register; the address is broadcast on address bus; Register Rm can
be preprocessed in barrel shifter before it enters ALU; Barrel shifter & ALU
can calculate a wide range of expressions and addresses.
• Address register
• Incrementer: Updates the address register before it reads or writes next
register value from/ to the next sequential instruction.
17

Processor Architectures
• Based on number of program and data buses
used there are 3 processors architecture:
• Von Neumann architecture
• Harvard architecture
• Super Harvard architecture
• Here Von Neumann architecture is shown as
same bus is used to access data & instructions
18

19
r14 is also called the Link Register (LR). This is used for
holding the return address when calling a function or
subroutine. At the end of the function or subroutine, the
program control can return to the main program and
resume by loading the value of LR into the Program
Counter (PC).
CPSR holds four status bits, negative (N), zero (Z), carry
(C), and overflow (O). These bits can be used for
conditional execution of subsequent instructions.
The SPSR is used to store the current value of the
CPSR when an exception is taken so that it can be
restored after handling the exception.

CPSR(Current Program Status Register)
20
The ARM core uses the CPSR to monitor and control internal operations. The CPSR
is dedicated 32-bit register and resides in register file.
The above figure shows basic layout of current program status register and it is
divided into four fields each 8-bit wide as shown above.
1. Flags 2. Status 3. Extension 4. Control
In the current design, Extension and status fields are reserved for future use.
The flag field contains the conditional flags such as negative flag, zero flag, carry flag and
overflow flag.
The control field contains processor mode bits, state bit and interrupts mask bits.

• Conditional Flags:
• Bit 31 – N – Negative flag: This flag bit indicates the result of arithmetic and logical
operation is negative.
• N = 0, Result is positive. N = 1, Result is negative.
• Bit 30 – Z – Zero flag: This flag bit indicates the result of arithmetic and logical
operation is ZERO.
• Z = 0, Result is positive (Unsigned). Z = 1, Result is negative (Signed).
• Bit 29 – C – Carry flag: This flag bit indicates the overflow occurred or not after the
addition.
• C = 0, Carry has not occurred after addition. C = 1, Carry occurred after addition.
• Bit 28 – V – Overflow flag: This flag bit indicates the signed overflow has occurred
or not ie result has exceed the limit or not.
• V = 0, Overflow not occurred. V = 1, Overflow occurred.
• Control Bits:
• Bit 7 – I – Interrupt Request (IRQ) I = 0, Enables the IRQ Interrupts. I = 1, Disables
the IRQ Interrupts.
• Bit 6 – F – Fast Interrupt Request (FIQ)
• F = 0, Enables the FIQ Interrupts. F = 1, Disables the FIQ Interrupts.
• Bit 5 – T – Thumb
• T = 0, Indicates the ARM state.
• T = 1, Indicates the THUMB state.
• Bit 4 to 0 – Processor mode bits.
• These bits are used for selection of operating modes is done as follows.
21

22
There are seven processor modes in total: six privileged modes (abort, fast
interrupt request, interrupt request, supervisor, system, and undefined) and
one nonprivileged mode (user).
The processor enters abort mode when there is a failed attempt to access
memory.

Processor Operating Modes
• The processor mode determines which
registers are active and the access rights to
the CPSR itself.
• Each processor mode is privileged or nonprivileged.
– A privileged mode allows full read-write access to CPSR and
Non- privileged mode allows only read access to CPSR but still
allows read-write access to conditional flags.
• ARM processor has seven processor modes. Out of this
six privileged modes and one Non- privileged mode.
They are
– Privileged modes: Abort, Fast interrupt request, Interrupt
request, Supervisor, System, Undefined.
– Non- Privileged mode: User.
23

• The processor enters abort mode when there is a failed
attempt to access memory.
• Fast interrupt request & Interrupt request modes correspond
to the two interrupt levels available on the ARM processor.
FIQs for fast, low latency interrupt handling and Interrupt
Requests (IRQs), for more general interrupts. An FIQ takes
priority over an IRQ in an ARM system.
• Supervisor mode is the mode that the processor is in after
reset and is generally the mode that an operating system
kernel operates in.
• System mode is a special version of user mode that allows full
read-write access to the CPSR.
• Undefined mode : When processor encounters an instruction
that is undefined or not supported by the implementation.
• User mode is used for programs and applications. 24

Banked Registers
26
•Main registers are 17.
•Banked registers (20) are a subset of the main 16 registers.
•Banked registers are identified by shading in the diagram

• The above figure shows all 37 registers in the register
file.
• Of those, 20 registers are hidden from a program at
different times. These registers are called banked
registers and are identified by the shading in the diagram.
• Banked registers are available only when the processor is
in a particular mode; for example, abort mode has
banked registers r13_abt, r14_abt and spsr_abt.
• Banked registers of a particular mode are denoted by an
underline character post-fixed to the mode mnemonic or
_mode.
• Every processor mode except user mode can change
mode by writing directly to the mode bits of the CPSR.
• All processor modes except system mode have a set of
associated banked registers that are a subset of the
main 16 registers. 27

• A banked register maps one-to-one onto a user mode
register. If you change processor mode, a banked
register from the new mode will replace an existing
register.
– For example, when the processor is in the interrupt
request mode, the instructions you execute still
access registers named r13 and r14. However, these
registers are the banked registers r13_irq and
r14_irq.
• The user mode registers r13_usr and r14_usr are not
affected by the instruction referencing these registers.
A program still has normal access to the other registers
r0 to r12.
• The processor mode can be changed by a program that writes
directly to the cpsr (the processor core has to be in privileged
mode) or by hardware when the core responds to an
exception or interrupt.
28

Pipelining
Pipelining:
• A pipeline is the mechanism, a RISC processor uses to
execute instructions. Using a pipeline speeds up
execution by fetching the next instruction while other
instructions are being decoded and executed.
• One way to view the pipeline is to think of it as an
automobile assembly line, with each stage carrying
out a particular task to manufacture the vehicle.
• Three-stage pipeline:
• Fetch: It loads an instruction from memory.
• Decode: It identifies the instruction to be executed.
• Execute: It processes the instruction and writes the result back to
a register.
29

• Example: ARM7 three-stage pipelining
30
The above figure shows a sequence of three instructions being fetched, decoded, and
executed by the processor. Each instruction takes a single cycle to complete after the
pipeline is filled.
The three instructions are placed into the pipeline sequentially.
First cycle: the core fetches the ADD instruction from memory.
Second cycle: the core fetches the SUB instruction and decodes the ADD instruction.

• Third cycle: both the SUB and ADD instructions are
moved along the pipeline. The ADD instruction is
executed, the SUB instruction is decoded, and the
CMP instruction is fetched. This procedure is called
filling the pipeline.
• The pipeline allows the core to execute an
instruction every cycle.
ARM 9 is using 5 stage pipeline:
• Stage 1 (Instruction Fetch)
• Stage 2 (Instruction Decode)
• Stage 3 (Instruction Execute)
• Stage 4 (Memory Access)
• Stage 5 (Write Back into Register)
31

ARM 10 is using 6 stage pipeline:
• Stage 1 (Instruction Fetch)
• Stage 2 (Issue to the next stage)
• Stage 3 (Instruction Decode)
• Stage 4 (Instruction Execute)
• Stage 5 (Memory Access)
• Stage 6 (Write Back into Register)
32

• As the pipeline length increases, the amount of work
done at each stage is reduced, which allows the
processor to attain a higher operating frequency. This
in turn increases the performance.
• The system latency also increases because it takes
more cycles to fill the pipeline before the core can
execute an instruction.
• The increased pipeline length also means there can be
data dependency between certain stages. You can
write code to reduce this dependency by using
instruction scheduling.
33

There are three other characteristics of the pipeline:
• First: The execution of a branch instruction or branching by
the direct modification of the PC causes the ARM core to
flush its pipeline.
• Second: ARM10 uses branch prediction, which reduces the
effect of a pipeline flush by predicting possible branches
and loading the new branch address prior to the execution
of the instruction.
• Third: An instruction in the execute stage will complete
even though an interrupt has been raised. Other
instructions in the pipeline will be abandoned, and the
processor will start filling the pipeline from the appropriate
entry in the vector table.
34

ARM instruction Set
3 Groups
• Data Processing instructions: Operate on values in
registers or on immediate values specified as part of
the instruction: Perform arithmetic, logical and
multiply operations.
• The result is also 32 bit & goes into a specified register.
• Long multiply results 64 bits & stored in 2 registers
• Data Transfer instructions: Move values between
registers & memory.
• Control flow instructions : Change the value of the PC;
Conditional & unconditional branch instructions.
35

Data Processing instructions
Arithmetic instructions:
• ADD r0, r1,r2: r0=r1+r2
• ADC r0, r1,r2: r0=r1+r2+C
• SUB r0, r1,r2: r0=r1-r2
• SBC r0, r1,r2
• RSB r0, r1,r2: Reverse subtraction;r0=r2-r1
• RSC r0, r1,r2
36

Bit-wise logical instructions
• AND ro, r1,r2: r0=r1 and r2
• ORR ro, r1,r2: r0=r1 or r2
• EOR ro, r1,r2: r0=r1 xor r2
• BIC ro, r1,r2:Logical bit clear; r0=r1 and (not r2)
Register-register move instructions:
• MOV r0, r2; Move r2 to r0
• MVN r0, r2; Move negate;r0= not r2
37

Comparison instructions
• CMP r1, r2; set cc on (r1-r2)
• CMN r1, r2; Compare negated; set cc on (r1+r2)
• TST r1, r2; set cc on (r1 and r2)
• TEQ r1, r2; set cc on (r1 xor r2)
All these above instructions affect the condition
codes (N,Z,C,V) in CPSR. These instructions do not
produce result in any register.
38

Specifying immediate operands: The 2nd source operand may
be shifted either by a constant number of bit positions or
by a register-specified number of bit positions.
• ADD r1,r2,#2: r1=r2+2
• SUB r3,r2,#1: r3=r2-1
Shifted register operands:
ADD r1,r2,r3,LSL #3; r1=r2+(r3<<3)
ADD r1,r2,r3,LSL r5; r1=r2+(r3<<r5)
Various shift & rotate options:
LSL: Logical shift left
LSR: Logical shift right
ROR: Rotate right
RRX: Rotate right extended by 1 bit; Carry is also rotated
ASL: Arithmetic shift left is similar to LSL; Protects the sign bit
ASR: Arithmetic shift right; Protects the sign bit
39

Multiplication instruction
• MUL r1,r2,r3; r1=(r2*r3) (31:0)
• Only the LS 32 bits are returned
• Immediate operands are not supported in
MUL instruction.
Multiply-accumulate instruction
• MLA r1,r2,r3,r4; r1=(r2*r3+r4) (31:0)
• It is required in DSP applications
40

3 types
• Single register loads & stores
• Multiple register loads & stores
• Single register-memory swap
• All ARM data transfer instructions use register indirect addressing
Single register loads & stores
Examples:
• LDR r0, [r1]; r0=mem[r1]: This instruction will take the address in r1, and
then load a 4 byte value from the memory pointed to by it into register r0
• STR r0, [r1]; mem[r1]=r0
Register indirect with offset:
• LDR r0, [r1, #4]; r0=mem[r1+4]
• STR r0, [r1, #12]; mem[r1+12]=r0
Register indirect with autoindexing:
• LDR r0, [r1, #4]!; r0=mem[r1+4], r1=r1+4
• STR r0, [r1, #12]!; mem[r1+12]=r0, r1=r1+4
Register indirect with postindexing:
• LDR r0, [r1], #4; r0=mem[r1], r1=r1+4
• STR r0, [r1], #12; mem[r1]=r0, r1=r1+12
41
Data Transfer instructions

We can specify a byte or half-word to be transferred
• LDRB r0, [r1]; r0=mem8[r1]
• STRB r0, [r1]; mem8[r1]=r0
• LDRSH r0, [r1]; r0=mem16[r1]; Load signed half word r0 from
memory
• STRSH r0, [r1]; mem16[r1]=r0
Multiple register loads & stores
ARM supports instructions that transfer data between several registers
& memory.
Load Multiple Increment After
• LDMIA r1, (r3,r5,r6); r3=mem[r1], r5=mem[r1+4], r6=mem[r1+8]
Load Multiple Increment Before
• For LDMIB, the addresses will be r1+4, r1+8 and r1+12
• LDMIB r1, (r3,r5,r6); r3=mem[r1+4], r5=mem[r1+8],
r6=mem[r1+12]
42

• Point to note: ARM does not support any HW
stack.
• SW stack can be implemented using the LDM
& STM family of instructions
• Memory mapped I/O in ARM: Both memory
locations & I/O devices will be treated as the
same.
• So no separate instructions for I/O ports. Both
use LDR & STR instructions only.
43

Control flow instructions
• These instructions change the order of instruction execution.
• Normal flow is sequential execution, where PC is incremented by 4
after executing every instruction.
Types of control flow instructions
Unconditional branch: B or BAL (Branch and Link)
B Target
conditional branch: BEQ, BNE, BPL, BMI, BCC, BCS, BVC, BVS, BGT, BGE,
BLT, BLE
BNE Loop
Branch & link instruction:
• Used for calling subroutine in ARM
• The return address is saved in register r14 (called Link register)
• To return from the subroutine, we have to jump back to the address
stored in r14.
Example: BL MYSUB
Note: Nested subroutine calls cannot be used in this way.
We can use SW stack to save/restore the return address & registers.
44

Conditional execution:
• A unique feature of the ARM instruction set: All instructions
can be made conditional, ie. will get executed only when a
specified condition is true.
• Helps in removing many short branch instructions
(improves performance & code density)
• Example1: if (r2 != 10) r5=r5+10-r3
CMP r2, #10
BEQ SKIP
ADD r5,r5,r2
SUB r5,r5,r3
SKIP:
CMP r2, #10
ADDNE r5,r5,r2
SUBNE r5,r5,r3
Here 1 branch instruction (BEQ SKIP) has been eliminated.
45

• Example2: if ((r1==r3) && (r5==r6)) r7=r7+10
CMP r1,r3
BNE SKIP
CMP r5,r6
BNE SKIP
ADD r7,r7,#10
SKIP:
CMP r1,r3
CMPEQ r5,r6
ADDEQ r7,r7,#10
Here 2 branch instructions have been eliminated.
46

ARM instruction Set and its
Programming
47

ARM Programming
49
Example1: 8bit data transfer
Example2: Find 1s complement of a number

Example3: Addition of 2 numbers
50

Example4: Shit left one bit
51

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