A typical programmable machine
1st Micro-processor: Intel 4004
Basics of Microprocessor
1.1 Evolution of Microprocessor and types
1.2 Salient features of 8085 Microprocessor,
Architecture of 8085 (block diagram), Register
organization, Limitations of 8-bit
Microprocessor
Intel 4004
•First commercially
available
microprocessor
produced in 1971.
•A 4 bit
microprocessor with
45 instructions and a
speed of 50K
instructions per
second (< ENIAC)
•Contained 2300
PMOS transistors.
•It was a 4 bit device
used with some other
devices to use it as a
calculator.
Intel 8008
•In 1972, Intel
designed 8008
microprocessor
working with 8 bit
words and
Motorola 6800.
•This required 20 or
more additional
devices to form a
functional CPU.
Intel 8080
•Designed in
1973, 8080 had a
larger instruction
set and required
only 2 additional
devices to form a
functional CPU.
•NMOS transistors
were used in this
for faster
operations.
Intel 8085
•In 1977, Intel
developed 8085
microprocessor
with internal clock
generator having
higher frequency
at reduced cost
and integration.
•It was a single
NMOS device
implemented with
6200 transistors
Intel 8086
•.
•This is the first
actual processor
designed in 1978
•Object code
programs created for
these processors still
can be executed on
the latest members of
Intel Architecture (IA)
family.
•8086 has 16 bit
registers and 16 bit
external data bus
with 20-bit
addressing giving
1MB address space.
Intel 8088
•8088 was identical to
8086, except for a smaller
external data bus of 8-bits.
•These processors
introduced IA
segmentation, but only in
real mode.
•16-bit registers could be
used as pointers to address
into segments of up to
64Kbytes in size
Intel 80186
•Was never used
Intel 80286
•In this processor,
Protected Mode was
introduced, in which
segment register
contents are selectors or
pointers to descriptor
tables.
•The descriptor provides
24 bit base addresses,
allowing a maximum
physical memory size of
up to 16 Mbytes,
support for virtual
memory management
on a segment swapping
basis, and various
protection mechanisms.
Intel 80386
•This introduced 32 bit registers (
for operands) into the architecture,
for both calculation & addressing
•The lower half of each 32 bit
register retained the properties of
one of the 16 bit registers of the
earlier two generations, to provide
complete upward compatibility.
•A new Virtual 8086 mode was
provided to yield greater efficiency
when executing programs created
for the 8086 and 8088 processors
on the new 32 bit machine.
•The 32 bit addressing was
supported with an external 32 bit
address bus giving a 4GBytes
address space and also allowed
each segment to be as large as 4
Gbytes
Intel 80486
•8 KB unified level 1 cache for code and data
was added to the CPU.
• In later versions of the 80486 the size of
level 1 cache was increased to 16 KB.
•Intel 486 featured much faster bus transfers -
1 CPU cycle as opposed to two or more CPU
cycles for the 80386 bus.
•Floating-point unit was integrated into
80486DX CPUs.
•This eliminated delay in communications
between the CPU and FPU.
•Clock-doubling and clock-tripling technology
was introduced in faster versions of Intel
80486 CPU.
•80486SX2 and 80486DX2 were clock-doubled
version, and 80486DX4 was a clock-tripled
version.
•Power management features and System
Management Mode (SMM) became a
standard feature of the processor.
Intel Pentium
•Introduced in Mar 1993( First
gen) and Mar 1994 .
•Maximum rated speeds :
60/66 MHz ( First gen)
;75/90/100/120/133/150/166
/200 MHz ( Second gen.)
•CPU Clock multiplier : 1x(1st
gen);1.5x -3x(2nd gen)
•Register size : 32 bit
•External Data bus : 64 bit
•Memory address bus : 32 bit
•Maximum memory : 4 GB
Intel Pentium II
•Bus speeds : 66 MHz; 100 MHz
•CPU clock multiplier: 3.5x, 4x,
4.5x, 5x
•CPU Speeds : 233 MHz, 266
MHz,300 MHz,333 MHz, 350 MHz,
400 MHz, 450 MHz
•Cache memory : 16K x 2( 32KB)
L1,512KB – ½ speed L2
•Internal registers: 32 bit
•External data bus: 64 bit system
bus
•Memory address bus : 36 bit
•Addressable memory : 64 GB
•Virtual memory : 64 TB
Intel Pentium III
•The first Pentium III core,
featured SSE instruction set,
which allowed SSE-enabled
applications to process up to
four single-precision floating
point numbers at once.
•Other Pentium 3 cores added
other features, like 256 and 512
KB on-die L2 cache memory and
smaller package size.
•During its lifetime, the core of
Pentium III microprocessors was
shrunk twice - from 0.25 micron
to 0.18 micron, and then to 0.13
micron.
Intel Pentium IV
•Speeds range from 1.3
GHz – 3.8 GHz
•FSB speed : 400 MHz,
533 MHz, 800 MHZ, 1066
MHz
•Hyper pipelined/ hyper
threading technology
•L2 cache can handle upto
4GB RAM
•Bus width is 64 bits
Block diagram/ Architecture of 8085
8085 Functional blocks
1. Arithmetic and Logic Unit
2. Register Array
3. Instruction Register and Decoder
4. Timing and Control Unit
5. Interrupt Control
6. Serial I/O Control
7. Address/Data Buffer
Register Organization
• Temporary registers
– Temporary data register
– W and Z register
• General purpose registers
• Special registers : PC, SP
• Accumulator(A)
• Instruction register and decoder
• Flag register D7 D6 D5 D4 D3 D2 D1 D0
S Z AC P CY
Features of 8085
• 8-bit microprocessor
• 16-bit address bus, so max. 64KB of memory
• 8-bit data bus
• Generates 8-bit I/O device address, so can access 256
I/O devices
• Requires +5V supply
• On-chip clock generator
• Has 5 h/w interrupts
• Has serial I/O lines
• Has accumulator, flag register, 6 GPR, 2 SPR, 3 TR
• Has 74 instructions, 4 addressing modes
8085 Pinout: 40 pin IC
1. Address Bus (A8-A15)
2. Data Bus (AD0-AD7)
3. Control and Status
signals (6)
4. Power Supply and clock
signals (5)
5. Externally initiated
signals (11)
6. Serial I/O port (2)
Interrupt Structure of 8085
Interrupt Priority Triggering Masking Vector Location
TRAP 1 Edge & Level Non-maskable 0024H
RST 7.5 2 Edge Maskable 003CH
RST 6.5 3 Level Maskable 0034H
RST 5.5 4 Level Maskable 002CH
INTR 5 Level Maskable Supplied by the
interrupting device
Hardware interrupts
Software interrupts
Limitations of 8085
• Can not process 16-bit data
• Limited instruction set
• No pipelining concept
• Processing speed is less
• Address bus is 16-bit, so can not access more than
64KB memory
• Can not process floating point data
• Not suitable for multiprocessor system
• Does not support memory segmentation
• Not suitable for workstation and server

8085

  • 2.
  • 3.
  • 4.
    Basics of Microprocessor 1.1Evolution of Microprocessor and types 1.2 Salient features of 8085 Microprocessor, Architecture of 8085 (block diagram), Register organization, Limitations of 8-bit Microprocessor
  • 5.
    Intel 4004 •First commercially available microprocessor producedin 1971. •A 4 bit microprocessor with 45 instructions and a speed of 50K instructions per second (< ENIAC) •Contained 2300 PMOS transistors. •It was a 4 bit device used with some other devices to use it as a calculator.
  • 6.
    Intel 8008 •In 1972,Intel designed 8008 microprocessor working with 8 bit words and Motorola 6800. •This required 20 or more additional devices to form a functional CPU.
  • 7.
    Intel 8080 •Designed in 1973,8080 had a larger instruction set and required only 2 additional devices to form a functional CPU. •NMOS transistors were used in this for faster operations.
  • 8.
    Intel 8085 •In 1977,Intel developed 8085 microprocessor with internal clock generator having higher frequency at reduced cost and integration. •It was a single NMOS device implemented with 6200 transistors
  • 9.
    Intel 8086 •. •This isthe first actual processor designed in 1978 •Object code programs created for these processors still can be executed on the latest members of Intel Architecture (IA) family. •8086 has 16 bit registers and 16 bit external data bus with 20-bit addressing giving 1MB address space.
  • 10.
    Intel 8088 •8088 wasidentical to 8086, except for a smaller external data bus of 8-bits. •These processors introduced IA segmentation, but only in real mode. •16-bit registers could be used as pointers to address into segments of up to 64Kbytes in size
  • 11.
  • 12.
    Intel 80286 •In thisprocessor, Protected Mode was introduced, in which segment register contents are selectors or pointers to descriptor tables. •The descriptor provides 24 bit base addresses, allowing a maximum physical memory size of up to 16 Mbytes, support for virtual memory management on a segment swapping basis, and various protection mechanisms.
  • 13.
    Intel 80386 •This introduced32 bit registers ( for operands) into the architecture, for both calculation & addressing •The lower half of each 32 bit register retained the properties of one of the 16 bit registers of the earlier two generations, to provide complete upward compatibility. •A new Virtual 8086 mode was provided to yield greater efficiency when executing programs created for the 8086 and 8088 processors on the new 32 bit machine. •The 32 bit addressing was supported with an external 32 bit address bus giving a 4GBytes address space and also allowed each segment to be as large as 4 Gbytes
  • 14.
    Intel 80486 •8 KBunified level 1 cache for code and data was added to the CPU. • In later versions of the 80486 the size of level 1 cache was increased to 16 KB. •Intel 486 featured much faster bus transfers - 1 CPU cycle as opposed to two or more CPU cycles for the 80386 bus. •Floating-point unit was integrated into 80486DX CPUs. •This eliminated delay in communications between the CPU and FPU. •Clock-doubling and clock-tripling technology was introduced in faster versions of Intel 80486 CPU. •80486SX2 and 80486DX2 were clock-doubled version, and 80486DX4 was a clock-tripled version. •Power management features and System Management Mode (SMM) became a standard feature of the processor.
  • 15.
    Intel Pentium •Introduced inMar 1993( First gen) and Mar 1994 . •Maximum rated speeds : 60/66 MHz ( First gen) ;75/90/100/120/133/150/166 /200 MHz ( Second gen.) •CPU Clock multiplier : 1x(1st gen);1.5x -3x(2nd gen) •Register size : 32 bit •External Data bus : 64 bit •Memory address bus : 32 bit •Maximum memory : 4 GB
  • 16.
    Intel Pentium II •Busspeeds : 66 MHz; 100 MHz •CPU clock multiplier: 3.5x, 4x, 4.5x, 5x •CPU Speeds : 233 MHz, 266 MHz,300 MHz,333 MHz, 350 MHz, 400 MHz, 450 MHz •Cache memory : 16K x 2( 32KB) L1,512KB – ½ speed L2 •Internal registers: 32 bit •External data bus: 64 bit system bus •Memory address bus : 36 bit •Addressable memory : 64 GB •Virtual memory : 64 TB
  • 17.
    Intel Pentium III •Thefirst Pentium III core, featured SSE instruction set, which allowed SSE-enabled applications to process up to four single-precision floating point numbers at once. •Other Pentium 3 cores added other features, like 256 and 512 KB on-die L2 cache memory and smaller package size. •During its lifetime, the core of Pentium III microprocessors was shrunk twice - from 0.25 micron to 0.18 micron, and then to 0.13 micron.
  • 18.
    Intel Pentium IV •Speedsrange from 1.3 GHz – 3.8 GHz •FSB speed : 400 MHz, 533 MHz, 800 MHZ, 1066 MHz •Hyper pipelined/ hyper threading technology •L2 cache can handle upto 4GB RAM •Bus width is 64 bits
  • 19.
  • 21.
    8085 Functional blocks 1.Arithmetic and Logic Unit 2. Register Array 3. Instruction Register and Decoder 4. Timing and Control Unit 5. Interrupt Control 6. Serial I/O Control 7. Address/Data Buffer
  • 22.
    Register Organization • Temporaryregisters – Temporary data register – W and Z register • General purpose registers • Special registers : PC, SP • Accumulator(A) • Instruction register and decoder • Flag register D7 D6 D5 D4 D3 D2 D1 D0 S Z AC P CY
  • 23.
    Features of 8085 •8-bit microprocessor • 16-bit address bus, so max. 64KB of memory • 8-bit data bus • Generates 8-bit I/O device address, so can access 256 I/O devices • Requires +5V supply • On-chip clock generator • Has 5 h/w interrupts • Has serial I/O lines • Has accumulator, flag register, 6 GPR, 2 SPR, 3 TR • Has 74 instructions, 4 addressing modes
  • 24.
    8085 Pinout: 40pin IC 1. Address Bus (A8-A15) 2. Data Bus (AD0-AD7) 3. Control and Status signals (6) 4. Power Supply and clock signals (5) 5. Externally initiated signals (11) 6. Serial I/O port (2)
  • 25.
    Interrupt Structure of8085 Interrupt Priority Triggering Masking Vector Location TRAP 1 Edge & Level Non-maskable 0024H RST 7.5 2 Edge Maskable 003CH RST 6.5 3 Level Maskable 0034H RST 5.5 4 Level Maskable 002CH INTR 5 Level Maskable Supplied by the interrupting device Hardware interrupts Software interrupts
  • 26.
    Limitations of 8085 •Can not process 16-bit data • Limited instruction set • No pipelining concept • Processing speed is less • Address bus is 16-bit, so can not access more than 64KB memory • Can not process floating point data • Not suitable for multiprocessor system • Does not support memory segmentation • Not suitable for workstation and server