This presentation discussed the Pentium Processor Family as requirement of the Micro-controller Course in Technological University of the Philippines. It covers the history of Pentium family of processors, list of Intel processors, features of the processors, architecture, modes, pipeline and trends.

1. PENTIUM PROCESSOR FAMILY
Presenters
Benjamin Nicomedes
For-Ian Sandoval

2. OVERVIEW: PENTIUM PROCESSOR
• a brand used for a series of x86-
compatible microprocessors
• produce by Intel
• a consumer-level product
• Greek and Latin words pente + ium
• used the fifth generation microarchitecture
• current Pentium processors only share the
name but are in fact based on the same
processor chips

3. HISTORY OF THE PENTIUM FAMILY OF
PROCESSORS
• 32-bit microprocessor introduced
by Intel in 1993
• contains more than 3
million transistors
• roots in the Intel486(TM) processor
• ''Pentium processor'' refers to a family of
microprocessors that share a common
architecture and instruction set

4. HISTORY OF THE PENTIUM FAMILY OF
PROCESSORS
• The 1st Pentium processors (P5
variety) was fabricated in 0.8
micron bipolar complementary
metal oxide semiconductor
(BiCMOS) technology
• Pentium Pro, Pentium II and Pentium III (P6)
• Pentium 4 & Pentium D (Netburst)
• Pentium M (P6-Based)
• Pentium Dual-Core (P6-Based & Core)

5. HISTORY OF THE PENTIUM FAMILY OF
PROCESSORS
• Pentium (Nehalem, Sandy
Bridge, Ivy Bridge Haswell and
Broadwell)

6. LIST OF INTEL PENTIUM PROCESSORS

7. EVOLUTION OF PENTIUM PROCESSORS
• significant processor evolution
facts, including introduction
date, ratings and number of
transistors

8. FEATURES OF THE PENTIUM FAMILY OF
PROCESSORS
P54C
• fully software compatible with the installed
base of over 100 million compatible Intel
architecture systems
• provides new levels of performance to new
and existing software
• reimplementation of the Intel
32-bit instruction set
architecture using the latest,
most advanced, design
techniques

9. ADVANCE FEATURES OF THE PENTIUM
FAMILY OF PROCESSORS
• Superscalar architecture or execution
• Pipeline architecture
• Branch prediction or Branch Target Buffer
• Dual 8-KB On-Chip Caches
• Write-Back Cache
• 64-Bit Bus
• Instruction Optimization
• Floating-Point Optimization
• Pentium Extensions

10. THE ARCHITECTURE OF PENTIUM MICROPROCESSOR

11. REGISTER SET
• is to hold temporary results and control the
execution of the program
• EAX, ECX, EDX, EBX, ESP, EBP, ESI, or
EDI
• The 32-bit registers are named with prefix E,
EAX, etc, and the least 16 bits 0-15 of these
registers can be accessed with names such
as AX, SI.
• Similarly the lower eight bits (0-7) can be
accessed with names such as AL & BL.

12. REGISTER SET
• The comparison of the available flags in 16-
bit and 32-bit microprocessor is may provide
some clues related to capabilities of these
processors.
• All of these flag registers include 6 flags
related to data conditions (sign, zero, carry,
auxiliary, carry , overflow, and parity) and
three flags related to machine operations,
interrupts, Single-step and Strings)

13. REGISTER SET
• The instruction pointer EAP known as
program counter (PC) in 8-bit
microprocessor, is a 32-bit register to handle
32-bit memory addresses, and the lower 16
bit segment IP is used for 16-bit memory
address.
• The flag register is a 32-bit register, however
14-bits are being used at present for 13
different tasks;

14. REGISTER SET
• The I/O Privilege uses two bits in protected
mode to determine which I/O instructions can
be used, and the nested task is used to show
a link between two tasks.
• The processor also includes control registers
and system address registers, debug and
test registers for system and debugging
operations.

15. PENTIUM PROCESSOR MODES
Protected mode
• the native state of the
microprocessor
• the recommended mode that all new
applications and operating systems should
target
• all instructions and
architectural features are
available
• capabilities of protected mode is the ability
to directly execute "real-address mode"

16. PENTIUM PROCESSOR MODES
Real-Address Mode or Real-
Mode
• programming environment of
the processor, with a few
extensions
• reset initialization places the processor in
real mode where, with a single instruction, it
can switch to protected mode

17. PENTIUM PROCESSOR MODES
System Management Mode
• a standard architectural
feature unique to all new Intel
microprocessors
• provides an operating-system and
application independent
• transparent mechanism to implement
system power management
• OEM differentiation features

18. INTEL PENTIUM MMX MICROARCHITECTURE

19. P6 MICROARCHITECTURE
19
Instruction Fetch nit
BTB/BAC
Instruction Fetch Unit
Bus interface unit
Instruction
Decoder
Instruction
Decoder
Register
Alias Table
AllocatorMicrocode
Sequencer
Reservation
Station
ROB &
Retire RF
AGU
MMX
IEU/JEUIEU/JEU
FEU
MIU
Memory
Order Buffer
Data Cache
Unit (L1)
External bus
Chip boundary
Control
Flow
(Restricted)
Data
FlowInstruction Fetch Cluster
Issue Cluster
Out-of-order
Cluster
Memory
Cluster
Bus Cluster

20. NETBURST MICROARCHITECTURE
20
BTB (4k entries) I-TLB/Prefetcher
IA32 Decoder
Execution Trace Cache
Trace Cache BTB
(512 entries)
Code ROM
op Queue
Allocator / Register Renamer
INT / FP op QueueMemory op Queue
Memory scheduler
INT Register File / Bypass Network FP RF / Bypass Ntwk
AGU AGU 2x ALU 2x ALU Slow ALU
Ld addr St addr
Simple
Inst.
Simple
Inst.
Complex
Inst.
FP
MMX
SSE/2
FP
Move
L1 Data Cache (8KB 4-way, 64-byte line, WT, 1 rd + 1 wr port)
Fast Slow/General FP scheduler Simple FP
Quad
Pumped
400M/533MHz
3.2/4.3 GB/sec
BIU
U-L2 Cache
256KB 8-way
128B line, WB
48 GB/s
@1.5Gz
256 bits
64 bits
64-bit
System
Bus

21. PIPELINE DEPTH EVOLUTION
PREF DEC DEC EXEC WB
P5 Microarchitecture
IFU1 IFU2 IFU3 DEC1 DEC2 RAT ROB DIS EX RET1 RET2
P6 Microarchitecture
TC NextIP TC Fetch Drive Alloc QueueRename Schedule Dispatch Reg File Exec Flags Br Ck Drive
NetBurst Microarchitecture

22. ADDRESSING MODE & TYPE OF INSTRUCTIONS
• instruction set is divided into 9 categories of
operations and has 11 addressing modes
• instruction may have 0-3 operands and the
operand can be 8, 16, or 32- bits long
• All Intel Architecture instruction encoding are
subsets of the general instruction format

23. ADDRESSING MODE & TYPE OF INSTRUCTIONS
• Instructions consist of optional instruction
prefixes (in any order)
• one or two primary opcode bytes
• an addressing-form specifier (if required)
consisting of the ModR/M byte

24. ADDRESSING MODE & TYPE OF INSTRUCTIONS
• sometimes the SIB (Scale-Index-Base) byte
• a displacement (if required)
• an immediate data field (if required)

25. TRENDS IN MICROPROCESSOR
• Microprocessor astounding range of chips
powering devices
• Embedded microprocessor
• Microprocessor packaging
• Microprocessor speed
• Microprocessor increasing power dissipation
• Microprocessor cost, compatibility and fit
• Microprocessor Architecture for Java
Computing or MAJC

26. MAJC
• microprocessor architecture designed to
meet the broadband demands of the 21st
century
• addressing the challenge of high bandwidth
• need for state-of-the-art computational
performance

27. MAJC ARCHITECTURE CHARACTERISTICS
• Scalability to take full advantage of advances
in semiconductor technology
• Broad scalability to systems with large
numbers of processors
• A new standard of performance for
applications with New Media computational
needs
• Focus on bandwidth throughput

28. 21st CENTURY MICROPROCESSOR TRENDS
• Convergence of communication media and
computers (audio, video, and data) require
processors to compute information at wire
speed
• Advancements in semiconductor technology will
provide rapidly-increasing resources on each
microprocessor chip
• As microprocessors are used in increasingly
disparate applications from smart cards to
supercomputers there is great value in the
ability to create a wide span of implementations
from a given processor architecture

29. 21st CENTURY MICROPROCESSOR TRENDS
• Software, over time, will become
independent of specific instruction sets
• Bandwidth between processors, memory,
and I/O devices needs to be available to
move information in real-time
• The content processed by computers is
becoming increasingly media-rich

30. FEATURES OF TODAY’S MICROPROCESSOR
• Modular Architecture
• Software Portability
• Multiple Levels of Parallelism
• Multiple Processor Units per Cluster
• Multiple Functional Units per Processor Unit
• Multiple Software
• SIMD Instructions

31. FEATURES OF TODAY’S MICROPROCESSOR
• Data and Address Size
• Context Switch Optimization
• Integral Support for Media-Rich Data
• Data Type-Independent Registers
• Instruction Grouping

32. THANK YOU!!!