The document explains two methods for interfacing memory or I/O devices with a microprocessor: I/O mapped I/O and memory mapped I/O. It details the addressing schemes, associated instruction sets, and connections required for implementing these interfacing methods. Additionally, it describes chip selection logic and considerations for memory size and address line requirements.

1. System Interfacing

2. Methods of Interfacing
• There are two methods of interfacing memory
or I/O devices with microprocessor
1. I/O mapped I/O
2. Memory mapped I/O
• In I/O mapped I/O, I/O device is treated as a
I/O device and memory as memory.
• In memory mapped I/O, I/O devices are also
treated as memory.

3. I/O mapped I/O
• I/O device is treated as I/O device & memory
as memory
• Each I/O device uses
– either 8 address lines (Fixed port)
– or 16 address lines ( Variable port)
• In fixed port 256 input and 256 output devices
can be connected
• Invariable port, 65,536 input & 65,536 output
devices can be used

4. Instructions used in Fixed type
addressing
• Any address line A0 - A7 or A8 – A15 can be
used.
• A16 - A19 are all 0’s.
• IN AL, 8 bit port address
• IN AX, 8 bit port address
• OUT 8 bit port address, AL
• OUT 8 bit port address, AX

5. Instructions used in Variable type
addressing
• Address lines A0 - A15 are be used.
• A16 - A19 are all 0’s.
• MOV DX, 16bit port address
• IN AL,DX
• IN AX,DX
• OUT DX,AL
• OUT DX,AX

6. Odd & even addressing concept
Actual physical
address
Even address
A3A2A1 A0
Odd address
A3A2A1 A0 BHE
0000 000 0 000 0 1
0001 1 1 0
0010 001 0 001 0 1
0011 1 1 0
0100 010 0 010 0 1
0101 1 1 0
0110 011 0 011 0 1
0111 1 1 0
1000 100 0 100 0 1
1001 1 1 0
1010 101 0 101 0 1
1011 1 1 0
1100 110 0 110 0 1
1101 1 1 0
1110 111 0 111 0 1

8. Logic levels of A0 and BHE for different types of
memory access
Address Data type BHE A0 Bus cycle Data lines
used
Even 00000 Byte 1 0 One D0-d7
odd 00001 Byte 0 1 One D8-d15
Even 00000 Word 0 0 One D0-d15
odd 00001 word 0 1 First cycle D8-d15
(lower byte)
1 0 Second
cycle
D0-d7
(higher byte)

9. 1. Find the required size of the memory
2. Find how many address lines are required. Always start with A1 of 8086,
A0 is commonly used for chip selection.
3. Find the address lines required to be connected to the memory chip.
Always connect A1 of 8086 to A0 of memory chip, A2 to A1 and so on.
so, if 13 lines are required, use A1 to A13 of 8086 & connect those to A0-
A12 of memory chip.
4. Use the remaining address lines of 8086 for chip selection, and connect
it to CS of chip*.
5. if memory used for even address only, use A0 for chip selection and use
data lines d0 to d7
6. If memory used for odd address only, use BHE for chip selection and use
data lines d8 to d15
7. Show the control signals as: MRDC/MEMR of 8086 connected to OE of
memory chip as i/p line
8. Name the memory devices properly as <size> RAM/ROM.
For RAM only: MWTC/MEMW OF 8086 connected to WR of memory chip as
i/p line.

10. Chip selection logic
1. Always use 3:8 decoder for chip selection, depending on CBA
combination any one of the O0 to O7 will be low.
C
B
A
O0
-
O7 Active low
outputs
E2 E1 E

19. • Full and partial decoding