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GOOD JOB……..

      4/23/2013   1
8085


4/23/2013   2
Evolution of Intel Microprocessor………..
                4004 8008 8080 8086 8086
  Introduced   15/11/      1/4/72 1/4/74 8/6/74 1/6/79
               71
  Clock        108         108       2 MHz    5,8,10           5,8
  speed
               kHz         kHz                MHz              MHz
  Bus Width    4 bits      8 bits    8 bits   16 bits          8 bits
  Number of    2300        3500      6000     29,000           29,000
  transistor
  (microns)
               (10)                  (6)      (3)              (3)
  Addressabl   640         16kbyt    64kbyte 1MB               1MB
  e
  Memory
               bytes       es        s
  Virtual              _         _       _           _               _
  Memory

                                                   4/23/2013             3
1980 Intel processor……………….
              80286        386 TM DX    386 TM SX     4867 H DX
                                                      CPU
Introduced    1/2/82       1/10/85      16/6/88        10/4/89

Clock speed   6,1.2,5MHz   16-33MHz     16-33MHz       25-50MHz

Bus width     16 bits      32bits       16bits         32bits

Number of     134,000(1.   275,000(1)   275,000(1)     1.2
Transistor    5)                                       Million(10.8-
(microns)                                              1)
Addressable   16MB         4GB          4GB            4GB
memory


Virtual       1GB          64TB         64TB           64TB
memory



                                                     4/23/2013         4
1990 Intel processor……………………….


                486 TM SX    Pentium       Pentium I      Pentium II
  Introduced    22/4/91      22/3/93       01/11/95       07/5/97
  Clock         16-133       60-           150-           200-
  Speed         MHz          166MHz        200MHz         300MHz
  Bus Width     32 bits      32bits        64 bits        64 bits
  Number of     1.185        3.1           5.5            7.5
  Transistor(   Million(1)   Million(.8)   Million(0.6)   Million(1.35
  microns)                                                )
  Addressabl    4GB          4GB           64GB           64GB
  e Memory
  Virtual       64TB         64TB          64TB           64TB
  Memory




                                                            4/23/2013    5
2000 Intel Processor………………




                        Pentium III   Pentium 4
       Introduced       26/2/99       25/11/2000
       Clock speed      450-660MHz    1.3-1.8GHz
       Bus Width        64 bits       64 bits
       Number of        95 Million    64 Million
       Transistor(micro
       ns)
       Addressable      64GB          64GB
       memory
       Virtual Memory   64 TB         64 TB




                                                   4/23/2013   6
1.It has an 8-bit MICROPROCESSOR, it provides 8-bitsdata.

2.It operate in a single +5V power supply at Vcc and
ground to Vss.

3.It operates on clock cycle with 50% duty cycle.

4. It has on chip clock generator, it contain like LC ,RS
or crystal .

5.It can operate with 3mhz clock frequency.

6.It contain 16 bits address line , 8 bits data line and
             64 Kbytes memory and 256 i/o ports.
                                              4/23/2013     7
7.It support 74 instructions with the following addressing
modes:
  a) Immediate b) Register c) Direct d) Indirect e)
Implied

8. The ALU of 8085 performs.
  a) 8 bits binary addition with or without carry

  b) 16 bits binary addition c) 2 digit BCD addition

  d) 8 bits binary subtraction with or without borrow .

  e)8 bits logical AND,OR EX-OR COMPLEMENT (NOT) and
             bit shift operation.
                                               4/23/2013     8
9. It has 8-bit accumulator ,flag register ,instructional register ,
   six 8-bit general register(B,C,D,E.H)AND 16 BITS register (SP and
PC)
10. It provides five hardware interrupts :TRAP,RST7.5,RST 6.5,
RST 5.5 and INTR.
11. IT has serial I/O control signal.
12. It provides control signals (IO/M, RD WR,) to control
the bus cycles and so external bus controller is not
required.
13. It can be used to implemented three chip
microcomputer with supporting I/O device like IC 8155
and 8355


                                                       4/23/2013       9
ARCHITECTURE OF 8085 :
It consist of various functional blocks as listed below :
•Registers
•Arithmetic and logic unit
•Instruction decoder and machine cycle encoder
•Address buffer
•Address/data buffer
•Incrementer/decrementer address latch
•Interrupt control
•Serial I/O control
•Timing and control circuitry.

                                           4/23/2013    10
INTR INTA RST5.5 RST6.5 RST7.5 TRAP   SID          SOD



                                   8 Bit internal data bus


     ACCUMULAT            TEMP              FLAG                         W Reg Z Reg
                                                         INST Reg.
        OR                Reg.              Reg.                         B Reg C Reg
                                                                         D Reg E Reg
                                                         INSTRUCTI       H Reg L Reg
                                                            ON           STACK
                                             ALU          DECODER        POINTER
                                                         &MACHINE
                                                           CYCLE
                                                                              PC
                                                                         INCREMENTER/DE
                                                          ENCODER
                                                                         CREMENTER
     POWER         +5V                                                   ADDRESS LATCH
     SUPPLY        GND
                 TIMING AND CONTROL
X1      CLK GEN CONTROL STATUS      DMA                               ADD          ADD/DATA
X2                    RESET                                          BUFFER         BUFFER


                                                                     A      A
               RD
     CLK OUT        WR ALE
                               SO S1IO/M                            15- 8
          READY
                                                   HLDA RESET OUT
                                               HOLD RESET IN      ADDRESS BUS
                                                                                    AD7-AD0
                                                                                    DATA/ADD BUS 11
           4/23/2013
The 8085 register are classified as……….

   1 . General purpose Registers( A,B,C,D,E,H and L 8
        OR 16 Bits reg.)
  2. Temporary Register
  a) Temporary data Register b) W and Z Register

   3. Special purpose Registers
   a) Accumulator b) Flag Register ( S,Z,AC,P,CY,-Sign flag)
   c) Instruction Register

  4) Sixteen Bit Register
   a) Program Counter b) Stack Pointer



                                            4/23/2013     12
1. 16 bit Registers…………

 a) Program Counter (PC): Program is a sequence of
                  instruction ,it store the address
                  of the next instruction at a given time.


 b) Stack Pointer(SP): It Reserved area of the memory in the
                      RAM where temporary information may
                      be stored.


2. Arithmetic Logic Unit(ALU): It perform bitwise
                     fundamental arithmetic operation such
                     as ADD,SUB… Also perform logic
                     operation AND,OR, EX-OR.
                                             4/23/2013    13
3. Instruction Decoder : It store opcode, then sent to inst
                            decoder.Inst decoder decodes it and
                            accordingly gives timing and control
                            signals which control the register,
                             the data buffer,ALU and External signal
                             depend on nature of the instruction.


4. Address Buffer : It is 8 bit unidirectional buffer .it is used to drive
                    external high order address bus     (A15-A 8).
5.Address/Data buffer : It is Bi- Directional buffer ,it is
used to drive multiplexed address/data bus, low order
(A7-A0) and data bus (D7-D0).




                                                           4/23/2013         14
6. Incrementer/decrementer Address Latch : The 16 bit register is used
                     to increment and decrement the content of program
                     counter or stack pointer as a part of execution of inst
                    related to them.

7. Interrupt Control : The processor fetch ,decodes and executes Instruction
                        in a sequence. Its having special routine Whenever
                        special condition exits within a program.

8. Serial I/O Control : it is used for long distance data transmission and
                       communication .it provides two lines SOD and SID for
                       serial communication. SOD(Serial output data) is used
                       for send data serially and SID(Serial Input data)
                        line used to receive data serially.

9. Timing and control circuitry: it is responsible for all the operations
                    such as control of fetching ,decoding operation,
                    generating appropriate signals for inst execution.

10.Power Supply and Frequency signals: It requires +5v .

                                                           4/23/2013        15
A6-A1(ADDRESS BUS)
AD0-AD7( I/0 3 STATE Multiplexed add/data bus)
ALE( output Address Latch Enable)
 S0-S1(output data bus Status)
 S1 So
 0   0 HALT
 0   1 WRITE    (S1 Used for advance R/W status)
 1   0 READ
 1    1 FETCH

                                      4/23/2013    16
RD (READ OUTPUT)
WR ( WRITE OUTPUT)
READY( INPUT)
 HOLD(INPUT)
HLDA (OUTPUT)

 INTR-INTERRUPT REQUEST ( INPUT)

INTR-INTERRUPT ACKNOWLEDGE (OUTPUT)
1) RST 7.5
2) RST 6.5(INPUT)
3) RST 5.5

 RESTART INTERRUPTS
1) RST 7.5(HIGHEST PRIORITY)
2) RST 6.5(INPUT)
3) RST 5.5(LOWEST PRIORITY)




                                       4/23/2013   17
TRAP (INPUT)

RESET IN (INPUT)

RESET OUT(OUTPUT)

X1,X2 ( INPUT)

CLK (OUTPUT)

IO/M (OUTPUT)

SID (OUTPUT)

SOD (OUTPUT)




                     4/23/2013   18
4/23/2013   19

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microprocessor

  • 1. GOOD JOB…….. 4/23/2013 1
  • 3. Evolution of Intel Microprocessor……….. 4004 8008 8080 8086 8086 Introduced 15/11/ 1/4/72 1/4/74 8/6/74 1/6/79 71 Clock 108 108 2 MHz 5,8,10 5,8 speed kHz kHz MHz MHz Bus Width 4 bits 8 bits 8 bits 16 bits 8 bits Number of 2300 3500 6000 29,000 29,000 transistor (microns) (10) (6) (3) (3) Addressabl 640 16kbyt 64kbyte 1MB 1MB e Memory bytes es s Virtual _ _ _ _ _ Memory 4/23/2013 3
  • 4. 1980 Intel processor………………. 80286 386 TM DX 386 TM SX 4867 H DX CPU Introduced 1/2/82 1/10/85 16/6/88 10/4/89 Clock speed 6,1.2,5MHz 16-33MHz 16-33MHz 25-50MHz Bus width 16 bits 32bits 16bits 32bits Number of 134,000(1. 275,000(1) 275,000(1) 1.2 Transistor 5) Million(10.8- (microns) 1) Addressable 16MB 4GB 4GB 4GB memory Virtual 1GB 64TB 64TB 64TB memory 4/23/2013 4
  • 5. 1990 Intel processor………………………. 486 TM SX Pentium Pentium I Pentium II Introduced 22/4/91 22/3/93 01/11/95 07/5/97 Clock 16-133 60- 150- 200- Speed MHz 166MHz 200MHz 300MHz Bus Width 32 bits 32bits 64 bits 64 bits Number of 1.185 3.1 5.5 7.5 Transistor( Million(1) Million(.8) Million(0.6) Million(1.35 microns) ) Addressabl 4GB 4GB 64GB 64GB e Memory Virtual 64TB 64TB 64TB 64TB Memory 4/23/2013 5
  • 6. 2000 Intel Processor……………… Pentium III Pentium 4 Introduced 26/2/99 25/11/2000 Clock speed 450-660MHz 1.3-1.8GHz Bus Width 64 bits 64 bits Number of 95 Million 64 Million Transistor(micro ns) Addressable 64GB 64GB memory Virtual Memory 64 TB 64 TB 4/23/2013 6
  • 7. 1.It has an 8-bit MICROPROCESSOR, it provides 8-bitsdata. 2.It operate in a single +5V power supply at Vcc and ground to Vss. 3.It operates on clock cycle with 50% duty cycle. 4. It has on chip clock generator, it contain like LC ,RS or crystal . 5.It can operate with 3mhz clock frequency. 6.It contain 16 bits address line , 8 bits data line and 64 Kbytes memory and 256 i/o ports. 4/23/2013 7
  • 8. 7.It support 74 instructions with the following addressing modes: a) Immediate b) Register c) Direct d) Indirect e) Implied 8. The ALU of 8085 performs. a) 8 bits binary addition with or without carry b) 16 bits binary addition c) 2 digit BCD addition d) 8 bits binary subtraction with or without borrow . e)8 bits logical AND,OR EX-OR COMPLEMENT (NOT) and bit shift operation. 4/23/2013 8
  • 9. 9. It has 8-bit accumulator ,flag register ,instructional register , six 8-bit general register(B,C,D,E.H)AND 16 BITS register (SP and PC) 10. It provides five hardware interrupts :TRAP,RST7.5,RST 6.5, RST 5.5 and INTR. 11. IT has serial I/O control signal. 12. It provides control signals (IO/M, RD WR,) to control the bus cycles and so external bus controller is not required. 13. It can be used to implemented three chip microcomputer with supporting I/O device like IC 8155 and 8355 4/23/2013 9
  • 10. ARCHITECTURE OF 8085 : It consist of various functional blocks as listed below : •Registers •Arithmetic and logic unit •Instruction decoder and machine cycle encoder •Address buffer •Address/data buffer •Incrementer/decrementer address latch •Interrupt control •Serial I/O control •Timing and control circuitry. 4/23/2013 10
  • 11. INTR INTA RST5.5 RST6.5 RST7.5 TRAP SID SOD 8 Bit internal data bus ACCUMULAT TEMP FLAG W Reg Z Reg INST Reg. OR Reg. Reg. B Reg C Reg D Reg E Reg INSTRUCTI H Reg L Reg ON STACK ALU DECODER POINTER &MACHINE CYCLE PC INCREMENTER/DE ENCODER CREMENTER POWER +5V ADDRESS LATCH SUPPLY GND TIMING AND CONTROL X1 CLK GEN CONTROL STATUS DMA ADD ADD/DATA X2 RESET BUFFER BUFFER A A RD CLK OUT WR ALE SO S1IO/M 15- 8 READY HLDA RESET OUT HOLD RESET IN ADDRESS BUS AD7-AD0 DATA/ADD BUS 11 4/23/2013
  • 12. The 8085 register are classified as………. 1 . General purpose Registers( A,B,C,D,E,H and L 8 OR 16 Bits reg.) 2. Temporary Register a) Temporary data Register b) W and Z Register 3. Special purpose Registers a) Accumulator b) Flag Register ( S,Z,AC,P,CY,-Sign flag) c) Instruction Register 4) Sixteen Bit Register a) Program Counter b) Stack Pointer 4/23/2013 12
  • 13. 1. 16 bit Registers………… a) Program Counter (PC): Program is a sequence of instruction ,it store the address of the next instruction at a given time. b) Stack Pointer(SP): It Reserved area of the memory in the RAM where temporary information may be stored. 2. Arithmetic Logic Unit(ALU): It perform bitwise fundamental arithmetic operation such as ADD,SUB… Also perform logic operation AND,OR, EX-OR. 4/23/2013 13
  • 14. 3. Instruction Decoder : It store opcode, then sent to inst decoder.Inst decoder decodes it and accordingly gives timing and control signals which control the register, the data buffer,ALU and External signal depend on nature of the instruction. 4. Address Buffer : It is 8 bit unidirectional buffer .it is used to drive external high order address bus (A15-A 8). 5.Address/Data buffer : It is Bi- Directional buffer ,it is used to drive multiplexed address/data bus, low order (A7-A0) and data bus (D7-D0). 4/23/2013 14
  • 15. 6. Incrementer/decrementer Address Latch : The 16 bit register is used to increment and decrement the content of program counter or stack pointer as a part of execution of inst related to them. 7. Interrupt Control : The processor fetch ,decodes and executes Instruction in a sequence. Its having special routine Whenever special condition exits within a program. 8. Serial I/O Control : it is used for long distance data transmission and communication .it provides two lines SOD and SID for serial communication. SOD(Serial output data) is used for send data serially and SID(Serial Input data) line used to receive data serially. 9. Timing and control circuitry: it is responsible for all the operations such as control of fetching ,decoding operation, generating appropriate signals for inst execution. 10.Power Supply and Frequency signals: It requires +5v . 4/23/2013 15
  • 16. A6-A1(ADDRESS BUS) AD0-AD7( I/0 3 STATE Multiplexed add/data bus) ALE( output Address Latch Enable) S0-S1(output data bus Status) S1 So 0 0 HALT 0 1 WRITE (S1 Used for advance R/W status) 1 0 READ 1 1 FETCH 4/23/2013 16
  • 17. RD (READ OUTPUT) WR ( WRITE OUTPUT) READY( INPUT) HOLD(INPUT) HLDA (OUTPUT) INTR-INTERRUPT REQUEST ( INPUT) INTR-INTERRUPT ACKNOWLEDGE (OUTPUT) 1) RST 7.5 2) RST 6.5(INPUT) 3) RST 5.5  RESTART INTERRUPTS 1) RST 7.5(HIGHEST PRIORITY) 2) RST 6.5(INPUT) 3) RST 5.5(LOWEST PRIORITY) 4/23/2013 17
  • 18. TRAP (INPUT) RESET IN (INPUT) RESET OUT(OUTPUT) X1,X2 ( INPUT) CLK (OUTPUT) IO/M (OUTPUT) SID (OUTPUT) SOD (OUTPUT) 4/23/2013 18
  • 19. 4/23/2013 19