This document discusses two methods for diagnosing faulty logic blocks in FPGA fabrics: the algebraic logic method and vector-logical method. The algebraic logic method is more useful for processing sparse fault tables with fewer than 20% 1s values, as it reduces the fault table size and simplifies computations to generate sum-of-products expressions to diagnose issues. The method involves removing rows and columns with all 0s, then constructing product-of-sums terms for each 1 in the response vector and converting to sum-of-products form. The vector-logical method is better for dense fault tables with many 1s, as it can more easily analyze tables where 1s predominate over 0s. Both methods aim to localize
This document summarizes a research paper that proposes a technique called reconfigurable built-in self test (RBIST) to detect and correct faults in field programmable gate arrays (FPGAs). The RBIST approach uses the partial reconfiguration capability of FPGAs to dynamically reconfigure logic blocks and implement a self-test controller for fault detection. The self-test controller coordinates test pattern generation, response verification, and identification of faults. The technique was implemented on a Xilinx FPGA board to demonstrate fault detection and correction without disrupting the normal operation of other logic blocks.
Abstract: Design verification is an essential step in the development of any product. It ensures that the product as designed is the same as the product as intended. Software simulation is the common approach for validating hardware design unfortunately, it will take hours together to execute. Difficulties in validation arise due to the complexity of the design and also due to the lack of on chip observability. One common solution to this problem is to instrument the prototype using trace-buffers to record a subset of internal signals into on-chip memory for subsequent analysis. In the proposed system, an example circuit is implemented to perform the tracing operation and various trace buffers are designed to record the different stages of internal signal states. The resulting signal states are to be stored, like a error outputs. Low power methodologies are also implemented to achieve low power consumption. Thus the errors are separately stored in the memory for analyzing the signals. This might be used for changes in the logic wherever needed. Thus this tracing is performed to monitor signal states of an FPGA.
DESIGN APPROACH FOR FAULT TOLERANCE IN FPGA ARCHITECTUREVLSICS Design
Failures of nano-metric technologies owing to defects and shrinking process tolerances give rise to significant challenges for IC testing. In recent years the application space of reconfigurable devices has grown to include many platforms with a strong need for fault tolerance. While these systems frequently contain hardware redundancy to allow for continued operation in the presence of operational faults, the need to recover faulty hardware and return it to full functionality quickly and efficiently is great. In addition to providing functional density, FPGAs provide a level of fault tolerance generally not found in mask-programmable devices by including the capability to reconfigure around operational faults in the field. Reliability and process variability are serious issues for FPGAs in the future. With advancement in process technology, the feature size is decreasing which leads to higher defect densities, more sophisticated techniques at increased costs are required to avoid defects. If nano-technology fabrication are applied the yield may go down to zero as avoiding defect during fabrication will not be a feasible option Hence, feature architecture have to be defect tolerant. In regular structure like FPGA, redundancy is commonly used for fault tolerance. In this work we present a solution in which configuration bit-stream of FPGA is modified by a hardware controller that is present on the chip itself. The technique uses redundant device for replacing faulty device and increases the yield.
This document discusses using genetic algorithms and evolvable hardware techniques to evolve digital circuit designs, specifically a 1-bit adder circuit. It describes representing circuit designs as chromosomes in a genetic algorithm population. Over generations, genetic operators like crossover and mutation create new circuit designs with the goal of optimizing a fitness function. The best designs are kept and used to populate the next generation. The document outlines compiling and executing provided C++ code to evolve a 1-bit adder circuit and interpret the resulting circuit design using graph data structures like adjacency matrices and lists.
Microcontroller Based Testing of Digital IP-CoreVLSICS Design
Testing core based System on Chip [1] is a challenge for the test engineers. To test the complete SOC at one time with maximum fault coverage, test engineers prefer to test each IP-core separately. At speed testing using external testers is more expensive because of gigahertz processor. The purpose of this paper is to develop cost efficient and flexible test methodology for testing digital IP-cores [2]. The prominent feature of the approach is to use microcontroller to test IP-core. The novel feature is that there is no need of test pattern generator and output response analyzer as microcontroller performs the function of both. This approach has various advantages such as at speed testing, low cost, less area overhead and greater flexibility since most of the testing process is based on software.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Programmable logic controller performance enhancement by field programmable g...ISA Interchange
This document proposes designing a programmable logic controller (PLC) using a field programmable gate array (FPGA) to improve performance. The FPGA implementation allows for parallel execution of logic compared to a typical microprocessor-based PLC. A GUI is developed in Visual Basic to program ladder logic into the FPGA by transmitting hex codes representing the logic. The proposed design architecture includes 4 rungs that can each contain up to 16 components. Simulation results demonstrate the FPGA-based PLC functioning for typical logic and alarm applications.
This document summarizes a research paper that proposes a technique called reconfigurable built-in self test (RBIST) to detect and correct faults in field programmable gate arrays (FPGAs). The RBIST approach uses the partial reconfiguration capability of FPGAs to dynamically reconfigure logic blocks and implement a self-test controller for fault detection. The self-test controller coordinates test pattern generation, response verification, and identification of faults. The technique was implemented on a Xilinx FPGA board to demonstrate fault detection and correction without disrupting the normal operation of other logic blocks.
Abstract: Design verification is an essential step in the development of any product. It ensures that the product as designed is the same as the product as intended. Software simulation is the common approach for validating hardware design unfortunately, it will take hours together to execute. Difficulties in validation arise due to the complexity of the design and also due to the lack of on chip observability. One common solution to this problem is to instrument the prototype using trace-buffers to record a subset of internal signals into on-chip memory for subsequent analysis. In the proposed system, an example circuit is implemented to perform the tracing operation and various trace buffers are designed to record the different stages of internal signal states. The resulting signal states are to be stored, like a error outputs. Low power methodologies are also implemented to achieve low power consumption. Thus the errors are separately stored in the memory for analyzing the signals. This might be used for changes in the logic wherever needed. Thus this tracing is performed to monitor signal states of an FPGA.
DESIGN APPROACH FOR FAULT TOLERANCE IN FPGA ARCHITECTUREVLSICS Design
Failures of nano-metric technologies owing to defects and shrinking process tolerances give rise to significant challenges for IC testing. In recent years the application space of reconfigurable devices has grown to include many platforms with a strong need for fault tolerance. While these systems frequently contain hardware redundancy to allow for continued operation in the presence of operational faults, the need to recover faulty hardware and return it to full functionality quickly and efficiently is great. In addition to providing functional density, FPGAs provide a level of fault tolerance generally not found in mask-programmable devices by including the capability to reconfigure around operational faults in the field. Reliability and process variability are serious issues for FPGAs in the future. With advancement in process technology, the feature size is decreasing which leads to higher defect densities, more sophisticated techniques at increased costs are required to avoid defects. If nano-technology fabrication are applied the yield may go down to zero as avoiding defect during fabrication will not be a feasible option Hence, feature architecture have to be defect tolerant. In regular structure like FPGA, redundancy is commonly used for fault tolerance. In this work we present a solution in which configuration bit-stream of FPGA is modified by a hardware controller that is present on the chip itself. The technique uses redundant device for replacing faulty device and increases the yield.
This document discusses using genetic algorithms and evolvable hardware techniques to evolve digital circuit designs, specifically a 1-bit adder circuit. It describes representing circuit designs as chromosomes in a genetic algorithm population. Over generations, genetic operators like crossover and mutation create new circuit designs with the goal of optimizing a fitness function. The best designs are kept and used to populate the next generation. The document outlines compiling and executing provided C++ code to evolve a 1-bit adder circuit and interpret the resulting circuit design using graph data structures like adjacency matrices and lists.
Microcontroller Based Testing of Digital IP-CoreVLSICS Design
Testing core based System on Chip [1] is a challenge for the test engineers. To test the complete SOC at one time with maximum fault coverage, test engineers prefer to test each IP-core separately. At speed testing using external testers is more expensive because of gigahertz processor. The purpose of this paper is to develop cost efficient and flexible test methodology for testing digital IP-cores [2]. The prominent feature of the approach is to use microcontroller to test IP-core. The novel feature is that there is no need of test pattern generator and output response analyzer as microcontroller performs the function of both. This approach has various advantages such as at speed testing, low cost, less area overhead and greater flexibility since most of the testing process is based on software.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Programmable logic controller performance enhancement by field programmable g...ISA Interchange
This document proposes designing a programmable logic controller (PLC) using a field programmable gate array (FPGA) to improve performance. The FPGA implementation allows for parallel execution of logic compared to a typical microprocessor-based PLC. A GUI is developed in Visual Basic to program ladder logic into the FPGA by transmitting hex codes representing the logic. The proposed design architecture includes 4 rungs that can each contain up to 16 components. Simulation results demonstrate the FPGA-based PLC functioning for typical logic and alarm applications.
This document summarizes a seminar on FPGA, CPLD, and VHDL programming basics. The seminar schedule includes sessions on FPGA technologies compared to previous programmable devices like CPLD, Microsemi FPGA devices and VHDL introduction. There is also an application example of using an FPGA for an Ethernet bus interface board and a discussion of current trends and technologies.
This document discusses fault tolerance in FPGA-based systems. It begins by defining an FPGA and its architecture, consisting of programmable logic blocks and a routing matrix. Fault tolerance aims to prevent failures caused by defects introduced during manufacturing. Methods of fault detection discussed include redundant error detection, offline testing, and roving tests. The document also covers single and multiple fault tolerance, as well as hardware, configuration, and system-level approaches. It provides VHDL code examples and concludes that the best solution combines dynamic and static fault tolerance methods to adapt to different environments.
Verilog Ams Used In Top Down Methodology For Wireless Integrated CircuitsRégis SANTONJA
The document discusses using the VerilogAMS language and top-down methodology for wireless integrated circuit designs. Specifically, it discusses:
1) Using the top-down methodology to allow for general functionality verification early in the design process by analyzing the ASIC from top to bottom before individual block implementation.
2) Describing the steps of behavioral modeling of blocks using VerilogA, replacing blocks with transistor-level designs, and simulating the entire design with mixed behavioral and transistor-level blocks.
3) Noting that the top-down methodology can be applied whether the design has a large analog/small digital portion or large digital/small analog portion.
Digitronix Nepal presented on electronics hardware design using field programmable gate arrays (FPGAs). They discussed FPGA technology, applications, opportunities, and trends globally and nationally. Engineering colleges in Nepal are incorporating FPGA courses and some have established FPGA research and development centers with support from Digitronix Nepal. National activities have included FPGA design contests and trainings to promote use of FPGAs in academic projects.
This document discusses fault tolerance techniques for field programmable gate arrays (FPGAs). It begins with an abstract and introduction describing how FPGAs are complex and must work reliably. It then covers FPGA architecture and different types of faults that can occur. The main methods of fault detection discussed are functional redundancy, off-line testing (built-in self-test), and roving testing. Functional redundancy uses additional logic for detection and has fast detection but high area overhead. Off-line testing has no performance impact but can only detect faults during dedicated test modes. Roving testing exploits run-time reconfiguration to test parts of the FPGA online with low overhead.
This document summarizes several papers on implementing feedforward neural networks using field programmable gate arrays (FPGAs). It discusses how FPGAs offer parallelism and flexibility for neural network designs while reducing costs compared to application-specific integrated circuits. The document reviews mathematical models of artificial neurons and different types of neural network architectures. It also examines challenges in efficiently implementing activation functions like the sigmoid on FPGAs. Several papers presented hardware implementations of multilayer feedforward neural networks in VHDL for applications such as digital pre-distortion.
This document discusses the architecture of Xilinx Cool Runner CPLDs. It provides an overview of Xilinx CPLD technologies including Cool Runner XPLA3 and Cool Runner-II. For the Cool Runner XPLA3, it describes the features and specifications, and details the architecture including the high-level block diagram, function block, macrocell, and I/O cell. For the Cool Runner-II, it lists the key features and specifications. The document is intended to explain the architectures of these Xilinx CPLD families.
An FPGA (field programmable gate array) is a reprogrammable silicon chip that can be configured to perform different logic functions. It allows for personalized hardware design without physical chips and wiring. FPGAs offer parallel processing capabilities across different sections of the chip. They contain programmable logic blocks and routing resources that can be configured using hardware description languages. FPGAs provide advantages over processors like true parallel processing, high reliability, maintenance flexibility, and performance that exceeds DSPs. They are useful for applications like signal processing, robotics, and prototyping.
Field-programmable gate array\
only for these students that are intrested in Field-programmable gate array
field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a customer or a designer after manufacturing – hence "field-programmable". The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application-specific integrated circuit (ASIC). (Circuit diagrams were previously used to specify the configuration, as they were for ASICs
The FPGA industry sprouted from programmable read-only memory (PROM) and programmable logic devices (PLDs). PROMs and PLDs both had the option of being programmed in batches in a factory or in the field (field-programmable). However, programmable logic was hard-wired between logic gates.[6]
In the late 1980s, the Naval Surface Warfare Center funded an experiment proposed by Steve Casselman to develop a computer that would implement 600,000 reprogrammable gates. Casselman was successful and a patent related to the system was issued in 1992.[6]
Some of the industry's foundational concepts and technologies for programmable logic arrays, gates, and logic blocks are founded in patents awarded to David W. Page and LuVerne R. Peterson in 1985.
Iaetsd a design of fpga with ledr encoding andIaetsd Iaetsd
This document proposes two techniques for reducing power consumption in asynchronous FPGAs: 1) Fine grain power gating which allows individual lookup tables to power gate independently, putting inactive tables to sleep. 2) Using level encoding dual rail (LEDR) architecture for data encoding which reduces dynamic power compared to existing dual rail encoding by eliminating the need for spacers between data values. Simulation results show the proposed FPGA design consuming 7mW of power which is reduced compared to non power gating approaches.
Implementation of Rotation and Vectoring-Mode Reconfigurable CORDICijtsrd
CORDIC or CO-ordinate Rotation Digital Computer is a fast, simple, efficient and powerful algorithm used for diverse Digital Signal Processing applications. Primarily developed for real-time airborne computations, it uses a unique computing technique which is especially suitable for solving the trigonometric relationships involved in plane co-ordinate rotation and conversion from rectangular to polar form. It comprises a special serial arithmetic unit having three shift registers, three adders/subtractors, Look-Up table and special interconnections. In this project A CORDIC-based processor for sine/cosine calculation was designed using VHDL programming in Xilinx ISE 13.2. The CORDIC module was tested for its functionality and correctness by test-bench analysis. Subsequently, FPGA implementation of the CORDIC core followed by Chip Scope Pro analysis of the output logic waveforms was performed. Kothapally Mounika | P. Pavan Kumar | K. Shobha Rani"Implementation of Rotation and Vectoring-Mode Reconfigurable CORDIC" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-2 | Issue-4 , June 2018, URL: http://www.ijtsrd.com/papers/ijtsrd14396.pdf http://www.ijtsrd.com/engineering/electronics-and-communication-engineering/14396/implementation-of-rotation-and-vectoring-mode-reconfigurable-cordic/kothapally-mounika
This document discusses image processing applications using Vivado for FPGAs. It provides information on FPGA architecture including distributed memory, block RAM features, and core generator. An example of a real-time breast cancer diagnosis application using YOLO on an FPGA board is described. A second example discusses implementing CCSDS standard DWT-based hyperspectral image decompression on an FPGA using techniques like Haar wavelet transform and MAP encoding.
IRJET- An Improved DCM-Based Tunable True Random Number Generator for Xilinx ...IRJET Journal
The document describes an improved tunable true random number generator (TRNG) design for Xilinx FPGAs based on the principle of beat frequency detection. The proposed TRNG uses two digital clock manager (DCM) modules instead of ring oscillators to generate oscillating waveforms. It has the key advantage of on-the-fly tunability through dynamic partial reconfiguration to modify DCM parameters and improve randomness characteristics without impacting normal functionality. Experimental results on a Xilinx Virtex-5 FPGA show the TRNG passes statistical tests and has low hardware overhead and built-in bias removal capabilities.
Deepak Anand Ravindran is seeking a full-time position in digital ASIC RTL design or verification. He has a Master's degree in Electrical Engineering from USC and a Bachelor's degree from NIT Trichy. He has work experience in memory circuit design at Dolphin Technology, chip validation and failure analysis at Broadcom, and digital and power embedded systems design at CDOT Alcatel-Lucent Research Center. His technical skills include Verilog, C, Perl, and digital design tools from Synopsys and Cadence. He has completed academic projects in memory controller design, ATPG, processor performance simulation, and network processor design.
This document discusses hardware design verification and testing techniques. It covers emulation architectures like FPGA-based and processor-based systems. It also discusses formal property verification methods, software formal verification, design for test objectives, chip-level DFT techniques, automatic test pattern generation, and testing techniques for analog/mixed-signal circuits like ADCs, PLLs and oscillators.
This document provides an introduction to semi-custom integrated circuit design and different types of application-specific integrated circuits (ASICs). It discusses the evolution of IC scale and complexity from SSI to VLSI. The main types of ASICs are described as full-custom, cell-based, and gate-array based. Full-custom ASICs have all layers customized, cell-based ASICs use predefined standard cells, and gate-array based ASICs have predefined transistors with customized interconnect. Channeled and channel-less gate arrays are subtypes that differ in routing architecture. The document aims to outline the design approaches and tradeoffs of semi-custom IC design.
This document is a resume for Jaydip Patel seeking an internship or entry-level position in VLSI design and validation. It summarizes his education, including an M.S. in Electrical and Electronics Engineering from California State University, Sacramento and a B.S. in Electronics and Communication Engineering from Gujarat University, India. It also lists relevant coursework, professional experience including internships, tools and software skills, and projects in analog and mixed signal design, logic design, computer architecture, and VLSI validation and testing.
The document discusses programmable logic arrays (PLAs) and their minimization and testing. It describes how PLAs can be used to implement combinational and sequential logic. PLA minimization techniques include removing redundant product terms and raising terms to optimize area usage. Folding is also described as a technique to minimize the PLA by allowing columns and rows to be shared, reducing the overall size. Column and row folding algorithms are discussed as well as their complexity.
This document provides an overview of key concepts in human anatomy and physiology, including definitions of anatomy, physiology, and basic concepts like structure dictates function and homeostasis. It discusses anatomy at different levels from microscopic to macroscopic. Anatomy is the study of the structure and organization of the human body, while physiology is the study of how the body functions. The document emphasizes that understanding the relationship between structure and function is important in anatomy and physiology. It also notes that maintaining homeostasis, or internal stability, is essential for the normal functioning of the body.
The document describes and analyzes the album cover for Beyoncé's 4th album. The cover features a simple design with Beyoncé's name and the album title, along with a powerful central image of Beyoncé in a revealing but tasteful fur jacket and gold wristband pose. The revealing costume helps portray her as a strong, superior woman. The neutral background makes the dark text and her image stand out clearly.
This document summarizes a seminar on FPGA, CPLD, and VHDL programming basics. The seminar schedule includes sessions on FPGA technologies compared to previous programmable devices like CPLD, Microsemi FPGA devices and VHDL introduction. There is also an application example of using an FPGA for an Ethernet bus interface board and a discussion of current trends and technologies.
This document discusses fault tolerance in FPGA-based systems. It begins by defining an FPGA and its architecture, consisting of programmable logic blocks and a routing matrix. Fault tolerance aims to prevent failures caused by defects introduced during manufacturing. Methods of fault detection discussed include redundant error detection, offline testing, and roving tests. The document also covers single and multiple fault tolerance, as well as hardware, configuration, and system-level approaches. It provides VHDL code examples and concludes that the best solution combines dynamic and static fault tolerance methods to adapt to different environments.
Verilog Ams Used In Top Down Methodology For Wireless Integrated CircuitsRégis SANTONJA
The document discusses using the VerilogAMS language and top-down methodology for wireless integrated circuit designs. Specifically, it discusses:
1) Using the top-down methodology to allow for general functionality verification early in the design process by analyzing the ASIC from top to bottom before individual block implementation.
2) Describing the steps of behavioral modeling of blocks using VerilogA, replacing blocks with transistor-level designs, and simulating the entire design with mixed behavioral and transistor-level blocks.
3) Noting that the top-down methodology can be applied whether the design has a large analog/small digital portion or large digital/small analog portion.
Digitronix Nepal presented on electronics hardware design using field programmable gate arrays (FPGAs). They discussed FPGA technology, applications, opportunities, and trends globally and nationally. Engineering colleges in Nepal are incorporating FPGA courses and some have established FPGA research and development centers with support from Digitronix Nepal. National activities have included FPGA design contests and trainings to promote use of FPGAs in academic projects.
This document discusses fault tolerance techniques for field programmable gate arrays (FPGAs). It begins with an abstract and introduction describing how FPGAs are complex and must work reliably. It then covers FPGA architecture and different types of faults that can occur. The main methods of fault detection discussed are functional redundancy, off-line testing (built-in self-test), and roving testing. Functional redundancy uses additional logic for detection and has fast detection but high area overhead. Off-line testing has no performance impact but can only detect faults during dedicated test modes. Roving testing exploits run-time reconfiguration to test parts of the FPGA online with low overhead.
This document summarizes several papers on implementing feedforward neural networks using field programmable gate arrays (FPGAs). It discusses how FPGAs offer parallelism and flexibility for neural network designs while reducing costs compared to application-specific integrated circuits. The document reviews mathematical models of artificial neurons and different types of neural network architectures. It also examines challenges in efficiently implementing activation functions like the sigmoid on FPGAs. Several papers presented hardware implementations of multilayer feedforward neural networks in VHDL for applications such as digital pre-distortion.
This document discusses the architecture of Xilinx Cool Runner CPLDs. It provides an overview of Xilinx CPLD technologies including Cool Runner XPLA3 and Cool Runner-II. For the Cool Runner XPLA3, it describes the features and specifications, and details the architecture including the high-level block diagram, function block, macrocell, and I/O cell. For the Cool Runner-II, it lists the key features and specifications. The document is intended to explain the architectures of these Xilinx CPLD families.
An FPGA (field programmable gate array) is a reprogrammable silicon chip that can be configured to perform different logic functions. It allows for personalized hardware design without physical chips and wiring. FPGAs offer parallel processing capabilities across different sections of the chip. They contain programmable logic blocks and routing resources that can be configured using hardware description languages. FPGAs provide advantages over processors like true parallel processing, high reliability, maintenance flexibility, and performance that exceeds DSPs. They are useful for applications like signal processing, robotics, and prototyping.
Field-programmable gate array\
only for these students that are intrested in Field-programmable gate array
field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a customer or a designer after manufacturing – hence "field-programmable". The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application-specific integrated circuit (ASIC). (Circuit diagrams were previously used to specify the configuration, as they were for ASICs
The FPGA industry sprouted from programmable read-only memory (PROM) and programmable logic devices (PLDs). PROMs and PLDs both had the option of being programmed in batches in a factory or in the field (field-programmable). However, programmable logic was hard-wired between logic gates.[6]
In the late 1980s, the Naval Surface Warfare Center funded an experiment proposed by Steve Casselman to develop a computer that would implement 600,000 reprogrammable gates. Casselman was successful and a patent related to the system was issued in 1992.[6]
Some of the industry's foundational concepts and technologies for programmable logic arrays, gates, and logic blocks are founded in patents awarded to David W. Page and LuVerne R. Peterson in 1985.
Iaetsd a design of fpga with ledr encoding andIaetsd Iaetsd
This document proposes two techniques for reducing power consumption in asynchronous FPGAs: 1) Fine grain power gating which allows individual lookup tables to power gate independently, putting inactive tables to sleep. 2) Using level encoding dual rail (LEDR) architecture for data encoding which reduces dynamic power compared to existing dual rail encoding by eliminating the need for spacers between data values. Simulation results show the proposed FPGA design consuming 7mW of power which is reduced compared to non power gating approaches.
Implementation of Rotation and Vectoring-Mode Reconfigurable CORDICijtsrd
CORDIC or CO-ordinate Rotation Digital Computer is a fast, simple, efficient and powerful algorithm used for diverse Digital Signal Processing applications. Primarily developed for real-time airborne computations, it uses a unique computing technique which is especially suitable for solving the trigonometric relationships involved in plane co-ordinate rotation and conversion from rectangular to polar form. It comprises a special serial arithmetic unit having three shift registers, three adders/subtractors, Look-Up table and special interconnections. In this project A CORDIC-based processor for sine/cosine calculation was designed using VHDL programming in Xilinx ISE 13.2. The CORDIC module was tested for its functionality and correctness by test-bench analysis. Subsequently, FPGA implementation of the CORDIC core followed by Chip Scope Pro analysis of the output logic waveforms was performed. Kothapally Mounika | P. Pavan Kumar | K. Shobha Rani"Implementation of Rotation and Vectoring-Mode Reconfigurable CORDIC" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-2 | Issue-4 , June 2018, URL: http://www.ijtsrd.com/papers/ijtsrd14396.pdf http://www.ijtsrd.com/engineering/electronics-and-communication-engineering/14396/implementation-of-rotation-and-vectoring-mode-reconfigurable-cordic/kothapally-mounika
This document discusses image processing applications using Vivado for FPGAs. It provides information on FPGA architecture including distributed memory, block RAM features, and core generator. An example of a real-time breast cancer diagnosis application using YOLO on an FPGA board is described. A second example discusses implementing CCSDS standard DWT-based hyperspectral image decompression on an FPGA using techniques like Haar wavelet transform and MAP encoding.
IRJET- An Improved DCM-Based Tunable True Random Number Generator for Xilinx ...IRJET Journal
The document describes an improved tunable true random number generator (TRNG) design for Xilinx FPGAs based on the principle of beat frequency detection. The proposed TRNG uses two digital clock manager (DCM) modules instead of ring oscillators to generate oscillating waveforms. It has the key advantage of on-the-fly tunability through dynamic partial reconfiguration to modify DCM parameters and improve randomness characteristics without impacting normal functionality. Experimental results on a Xilinx Virtex-5 FPGA show the TRNG passes statistical tests and has low hardware overhead and built-in bias removal capabilities.
Deepak Anand Ravindran is seeking a full-time position in digital ASIC RTL design or verification. He has a Master's degree in Electrical Engineering from USC and a Bachelor's degree from NIT Trichy. He has work experience in memory circuit design at Dolphin Technology, chip validation and failure analysis at Broadcom, and digital and power embedded systems design at CDOT Alcatel-Lucent Research Center. His technical skills include Verilog, C, Perl, and digital design tools from Synopsys and Cadence. He has completed academic projects in memory controller design, ATPG, processor performance simulation, and network processor design.
This document discusses hardware design verification and testing techniques. It covers emulation architectures like FPGA-based and processor-based systems. It also discusses formal property verification methods, software formal verification, design for test objectives, chip-level DFT techniques, automatic test pattern generation, and testing techniques for analog/mixed-signal circuits like ADCs, PLLs and oscillators.
This document provides an introduction to semi-custom integrated circuit design and different types of application-specific integrated circuits (ASICs). It discusses the evolution of IC scale and complexity from SSI to VLSI. The main types of ASICs are described as full-custom, cell-based, and gate-array based. Full-custom ASICs have all layers customized, cell-based ASICs use predefined standard cells, and gate-array based ASICs have predefined transistors with customized interconnect. Channeled and channel-less gate arrays are subtypes that differ in routing architecture. The document aims to outline the design approaches and tradeoffs of semi-custom IC design.
This document is a resume for Jaydip Patel seeking an internship or entry-level position in VLSI design and validation. It summarizes his education, including an M.S. in Electrical and Electronics Engineering from California State University, Sacramento and a B.S. in Electronics and Communication Engineering from Gujarat University, India. It also lists relevant coursework, professional experience including internships, tools and software skills, and projects in analog and mixed signal design, logic design, computer architecture, and VLSI validation and testing.
The document discusses programmable logic arrays (PLAs) and their minimization and testing. It describes how PLAs can be used to implement combinational and sequential logic. PLA minimization techniques include removing redundant product terms and raising terms to optimize area usage. Folding is also described as a technique to minimize the PLA by allowing columns and rows to be shared, reducing the overall size. Column and row folding algorithms are discussed as well as their complexity.
This document provides an overview of key concepts in human anatomy and physiology, including definitions of anatomy, physiology, and basic concepts like structure dictates function and homeostasis. It discusses anatomy at different levels from microscopic to macroscopic. Anatomy is the study of the structure and organization of the human body, while physiology is the study of how the body functions. The document emphasizes that understanding the relationship between structure and function is important in anatomy and physiology. It also notes that maintaining homeostasis, or internal stability, is essential for the normal functioning of the body.
The document describes and analyzes the album cover for Beyoncé's 4th album. The cover features a simple design with Beyoncé's name and the album title, along with a powerful central image of Beyoncé in a revealing but tasteful fur jacket and gold wristband pose. The revealing costume helps portray her as a strong, superior woman. The neutral background makes the dark text and her image stand out clearly.
David arrives home late from work, which upsets his wife Fearne. She accuses him of being unfaithful with another woman. When David tries to calm Fearne down, she becomes violent and pushes him away with a knife in her hand. The audience hears sirens, and then sees the knife drop to the floor. The screen then shows the back door open with no one there.
Alfred Fendi Nasrallah attended the WG453 Interplay Central Services training from June 22-26, 2015. The Avid Training document confirms that Alfred Fendi Nasrallah attended the specified training on the listed dates. Jason Plews, Director of Worldwide Consulting & Training, signed the confirmation.
This document describes the development of an electrically operated cassava slicing machine. Key points:
- The machine was designed to require only one operator, improve efficiency over manual processing, and produce uniform chips at a rate of 10 kg per minute.
- It consists of a hopper, slicing disc made of galvanized steel, cover to direct chips, and electric motor connected via pulleys.
- Testing showed it produced an average of 5.3 kg of 10mm chips per minute. Efficiency tests found it processed cassava into chips with 95.6% efficiency on average.
- The machine is meant to reduce labor needs for medium-scale cassava processing in Nigeria by providing an electrically powered
Este documento repete a frase "OTROS VENTOS" várias vezes, sem fornecer mais informações ou detalhes sobre o assunto. Não é possível resumir o conteúdo, já que não há informações significativas no texto.
Acceso abierto - Open access #infografiaJuanjo Bote
What Open Access is? ¿Qué es el Acceso Abierto? el acceso abierto es un tema muy largo. En esta infografia, tienes 5 consejos sobre el Acceso Abierto.
Te ayudo con tus trabajos de investigación
Este documento presenta un examen de matemáticas para estudiantes de 2o de ESO. Incluye 7 problemas que abarcan operaciones combinadas, factorización, mínimo común múltiplo, máximo común divisor, y problemas sobre la velocidad de vehículos, el tamaño de baldosas, el corte de cuerdas, y los cambios de temperatura a lo largo del día.
This document discusses RFID (Radio Frequency Identification) technology. It defines RFID as an automated data collection technology that uses radio waves to identify items tagged with RFID tags. The document outlines the key components of an RFID system including RFID tags, RFID readers, and a data processing subsystem. It describes the differences between active and passive RFID tags and provides examples of applications for RFID technology in manufacturing, warehousing, and security.
The document discusses using handwritten signature verification as an additional security measure for computer systems. It notes that signature verification must be cheap, reliable, and unobtrusive. It explains that online signature verification analyzes dynamic features of signing, like speed and pressure, which presents challenges in differentiating consistent versus varying behavioral elements of a person's signature over time. The document outlines the signature acquisition and identification process using global features and training models, and notes the benefits of low error rates, ability to detect forgery even with copied signatures, fast training, and cheap storage requirements.
Collection and Handling of Specimens for Laboratory DiagnosisPerez Eric
This document provides guidance on collecting, handling, and transporting specimens for laboratory diagnosis of animal diseases. It discusses the purposes of collecting samples, such as for direct examination, isolation of microorganisms, serological and molecular testing. Key steps include using proper protective equipment, collecting sufficient samples before treatment, using sterile containers, maintaining cold chain transport, and providing epidemiological information. A checklist is provided for field sample collection kits and samples that should always be collected from various tissues and body fluids. Proper handling and rapid transport of samples to the laboratory is emphasized.
Hospitals generate wastewater containing pathogens, pharmaceuticals, heavy metals and other pollutants. This wastewater requires specialized treatment to remove contaminants before discharge. A biological MBBR/IFAS process using Levapor carriers is an effective treatment method. The porous carriers adsorb inhibitory substances and pollutants, allowing specialized biofilm to develop and remove contaminants through biological and chemical processes. This results in consistently high quality effluent meeting discharge standards.
7 Things You Should Know About Flipped Classrooms - EducauseLuciano Sathler
1. A flipped classroom reverses the traditional lecture and homework elements, having students watch short video lectures at home and devote class time to exercises, projects, and discussions. This allows class time to focus on active learning.
2. In a common flipped classroom model, students watch video lectures outside of class and complete quizzes. In class, instructors lead discussions and help students apply what they learned through hands-on activities and problem solving.
3. Several colleges and universities have implemented flipped classroom techniques in courses like video production, accounting, physics, and more. This allows more flexible learning and moves instruction to an active, collaborative model.
Monash University has improved its global rankings, now placing 99th in the world according to Times Higher Education magazine. The university achieved its best result in the Academic Ranking of World Universities, placing 137th. Several courses saw changes to their availability for international students or had new courses introduced. The university also highlighted rankings improvements, a new website for Monash South Africa, a new Bachelor of Pharmaceutical Science Advanced with Honours course, and opportunities for on-campus accommodation.
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Getting to Emory from Agnes Scott on the Cliff BusMcCain Library
The document provides directions for students from Agnes Scott College to travel via public transportation to the Woodruff Library at Emory University using the Cliff Bus shuttle service. It details taking the CCTMA route Cliff Bus from the MARTA station bus loading area, exiting at the first Clifton Road stop, then following a short walking route past markers for Fishburne Drive and Ashbury Circle to reach the library's main entrance within its central courtyard. A review section recaps the key steps of taking the bus and navigating the short walk from the stop to the library.
This document provides information about various points of interest in and around Columbia, Missouri, including historic sites, art galleries, museums, and upcoming community events in July and August 2008. Some of the key locations and events mentioned include Arrow Rock State Historic Site, Les Bourgeois Winery & Vineyards, the Columbia Art League gallery, outdoor movies at Stephens Lake Park, the Show Me State Games occurring throughout July and August, and the Festival of Lights in Boonville on August 4th, 11th, 18th, and 25th.
An FPGA is described as a reconfigurable integrated circuit containing an array of logic blocks and programmable interconnects. The document discusses an FPGA's architecture, including configurable logic blocks and routing resources. It also provides VHDL code for an 8-bit ALU implementation on an FPGA, including a process to handle data display on an LCD screen.
The document discusses implementing convolution on an FPGA. It begins by introducing convolution and its applications in image processing. It then discusses the scope and technical approach of implementing discrete linear convolution on FPGA kits in order to perform convolution on images in real-time. The document outlines the structure of FPGAs, including configurable logic blocks and wiring tracks. It also discusses software requirements and provides an organization plan for subsequent chapters on linear convolution, FPGA technology, and a literature survey.
https://www.corelis.com/education/tutorials/jtag-tutorial/what-is-jtag/
JTAG allows for the testing and programming of digital and analog circuits, including microprocessors, memory devices, and other digital and mixed-signal components.
#JTAG
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
An application specific reconfigurable architecture for fault testing and dia...eSAT Journals
This document discusses application-specific reconfigurable architectures for fault testing and diagnosis in FPGAs. It provides an overview of different types of faults that can occur in FPGAs at runtime, including logical faults, interconnect faults, and delay faults. It then reviews several previous works that proposed various techniques for application-independent and application-dependent fault diagnosis in FPGAs, focusing on methods for detecting and locating logical faults and interconnect faults. The goal is to remove faults at the application level to improve FPGA performance and reliability.
An FPGA (Field-Programmable Gate Array) is an integrated circuit device that can be reconfigured to implement different logic functions. It contains a matrix of configurable logic blocks and programmable interconnects. Unlike processors, FPGAs use dedicated hardware rather than an operating system, allowing truly parallel processing. FPGAs can be reconfigured after deployment to change their internal circuitry. A single FPGA can replace thousands of discrete components. FPGAs are classified based on their internal structure and the technology used for user programmable switches. The FPGA design flow involves system design, design description, synthesis, implementation, verification and testing.
One of the key benefits of JTAG is that it provides access to the internal circuitry of a device without the need for additional hardware such as a test probe or emulator. This is possible because JTAG uses a series of test access ports (TAPs) that are built into a device's boundary-scan architecture.
Three-phase ac motors have been the workhorse of industry since the earliest days of electrical engineering. They are reliable, efficient, cost-effective and need little or no maintenance. In addition, ac motors such as induction and reluctance motors need no electrical connection to the rotor, so can easily be made flameproof for use in hazardous environments such as in mines.
In order to provide proper speed control of an ac motor, it is necessary to supply the motor with a three phase supply of which both the voltage and the frequency can be varied. Such a supply will create a variable speed rotating field in the stator that will allow the rotor to rotate at the required speed with low slip. This ac motor drive can efficiently provide full torque from zero speed to full speed, can overspeed if necessary, and can, by changing phase rotation, easily provide bi-directional operation of the motor. A drive with these characteristics is known as a PWM (Pulse Width Modulated) motor drive.
Drives and motors are an integral part of industrial equipment from packaging,robotics, computer numerical control (CNC), machine tools, industrial pumps,and fans. Designing next-generation drive systems to lower operating costs requires complex control algorithms at very low latencies as well as a flexibleplatform to support changing needs and the ability to design multiple-axis systems.
Traditional drive systems based on ASICs, digital signal processors (DSPs), and microcontroller units lack the performance and flexibility to address these needs. Altera’s family of FPGAs provides a scalable platform that can be used to offload control algorithm elements in hardware. You may also integrate the whole drive system with industry-proven processor architectures while supporting multipletypes of encoders and industrial Ethernet protocols. This “drive on a chip” system reduces cost and simplifies development.
Implementation of CAN on FPGA for Security Evaluation PurposeIRJET Journal
This document describes the implementation of a Controller Area Network (CAN) bus on an FPGA for the purpose of evaluating security measures. It discusses how implementing CAN on an FPGA-based testbed allows for faster development and evaluation of cryptographic algorithms and other security primitives for securing CAN communications compared to using a real vehicle. The testbed design uses a Xilinx Zynq SoC with a modified OpenCores SJA1000 CAN controller in the programmable logic interfaced to a CAN transceiver. A Linux system is built on the processing system for application development and interfacing with the CAN controller to test security measures for the CAN bus.
The document discusses the architecture of CPLDs and FPGAs. It begins by explaining the problems with using basic logic gates on PCBs and introduces programmable logic devices as a solution. It then describes different types of PLDs including PLA, PAL, GAL, CPLD and FPGA. CPLDs have a complexity between FPGAs and basic PLDs, containing non-volatile memory and supporting larger logic than PLDs. FPGAs contain logic cells, interconnects, and can implement thousands of gates. The document provides examples of implementing logic with different PLDs and describes the architecture and programming of CPLDs and FPGAs.
IRJET- PCB Test, Debug & Programming Made Easy with Universal Test JigIRJET Journal
This document discusses a universal test jig that uses XJTAG technology to test printed circuit boards. XJTAG allows testing, troubleshooting, and programming of PCBs containing both JTAG and non-JTAG devices. The universal test jig includes an I/O board connected to an XJLink 2.0 adapter to interface between the computer and device under test on the PCB. XJDeveloper software is used to develop and execute test programs, while the XJLink 2.0 hardware connects to the computer via USB to drive signals to and from the device under test.
This document describes a chemical extraction system controlled by an FPGA programmed using VHDL. The system extracts acetone from a water/acetone solution based on the different boiling points. The FPGA controls valves and monitors temperature and concentration sensors. A VHDL program was developed and divided into four parts to control the system. The program was synthesized and downloaded to the FPGA. The system successfully extracted 99% pure acetone by opening and closing valves based on sensor readings. FPGAs provide facilities to control systems in parallel, allowing control of many elements with minimal delay.
This document discusses system designing and modeling using field programmable gate arrays (FPGAs). It provides an overview of FPGA architecture, including logic blocks, interconnects, switch boxes, and input/output pads. Programming FPGAs involves using a hardware description language (HDL) like VHDL or Verilog to define the design, which is then synthesized, placed, and routed to the FPGA. Common applications of FPGAs include digital signal processing, image processing, cryptography, and ASIC prototyping. The document provides examples of FPGA components and programming.
This document discusses three options for implementing digital designs: microcontrollers, ASICs, and FPGAs. It provides details on the differences between FPGAs and microcontrollers, and between FPGAs and ASICs. FPGAs offer reconfigurable hardware, faster speeds than microcontrollers due to parallel processing, and more flexible I/O. However, ASICs are best for high volume manufacturing due to lower costs. The document also provides information on the internal architecture of FPGAs, including configurable logic blocks, look up tables, programmable interconnects, and I/O blocks.
This document compares FPGAs and microcontrollers. FPGAs can provide much higher performance per watt than microcontrollers due to their ability to perform thousands of calculations per clock cycle. However, microcontrollers are better suited for floating point calculations and have an advantage for tasks that require dynamic parallelism. FPGAs are well-suited for problems that can be parallelized, while microcontrollers may be preferable for unpredictable tasks. Both device types have pros and cons related to factors like power usage, programming difficulty, cost, and interfaces. The selection depends on the specific application requirements and developer resources.
HIGH PERFORMANCE ETHERNET PACKET PROCESSOR CORE FOR NEXT GENERATION NETWORKSijngnjournal
As the demand for high speed Internet significantly increasing to meet the requirement of large data transfers, real-time communication and High Definition ( HD) multimedia transfer over IP, the IP based network products architecture must evolve and change. Application specific processors require high
performance, low power and high degree of programmability is the limitation in many general processor based applications. This paper describes the design of Ethernet packet processor for system-on-chip (SoC) which performs all core packet processing functions, including segmentation and reassembly, packetization classification, route and queue management which will speedup switching/routing performance making it
more suitable for Next Generation Networks (NGN). Ethernet packet processor design can be configured for use with multiple projects targeted to a FPGA device the system is designed to support 1/10/20/40/100 Gigabit links with a speed and performance advantage. VHDL has been used to implement and simulated the required functions in FPGA
IRJET- A Review- FPGA based Architectures for Image Capturing Consequently Pr...IRJET Journal
This document presents a review of FPGA-based architectures for image capturing, processing, and display using a VGA monitor. It discusses using the Xilinx AccelDSP tool to develop the system on a Spartan 3E FPGA. The AccelDSP tool allows converting a MATLAB design into HDL for implementation on the FPGA. It summarizes the FPGA-based system architecture, which includes units for initialization, data transfer, image processing, and memory management. It then outlines the Xilinx AccelDSP design flow, which verifies the functionality at each stage of converting the floating-point MATLAB model to a fixed-point hardware implementation on the FPGA. The goal is to accelerate image processing applications using the parallel
LOGIC OPTIMIZATION USING TECHNOLOGY INDEPENDENT MUX BASED ADDERS IN FPGAVLSICS Design
Adders form an almost obligatory component of every contemporary integrated circuit. The prerequisite of the adder is that it is primarily fast and secondarily efficient in terms of power consumption and chip area. Therefore, careful optimization of the adder is of the greatest importance. This optimization can be attained
in two levels; it can be circuit or logic optimization. In circuit optimization the size of transistors are manipulated, where as in logic optimization the Boolean equations are rearranged (or manipulated) to optimize speed, area and power consumption. This paper focuses the optimization of adder through technology independent mapping. The work presents 20 different logical construction of 1-bit adder cell in CMOS logic and its performance is analyzed in terms of transistor count, delay and power dissipation. These performance issues are analyzed through Tanner EDA with TSMC MOSIS 250nm technology. From this analysis the optimized equation is chosen to construct a full adder circuit in terms of multiplexer. This logic optimized multiplexer based adders are incorporated in selected existing adders like ripple carry
adder, carry look-ahead adder, carry skip adder, carry select adder, carry increment adder and carry save adder and its performance is analyzed in terms of area (slices used) and maximum combinational path delay as a function of size. The target FPGA device chosen for the implementation of these adders was Xilinx ISE 12.1 Spartan3E XC3S500-5FG320. Each adder type was implemented with bit sizes of: 8, 16, 32, 64 bits. This variety of sizes will provide with more insight about the performance of each adder in terms of area and delay as a function of size.
Remote field-programmable gate array laboratory for signal acquisition and de...IJECEIAES
A remote laboratory utilizing field-programmable gate array (FPGA) technologies enhances students’ learning experience anywhere and anytime in embedded system design. Existing remote laboratories prioritize hardware access and visual feedback for observing board behavior after programming, neglecting comprehensive debugging tools to resolve errors that require internal signal acquisition. This paper proposes a novel remote embeddedsystem design approach targeting FPGA technologies that are fully interactive via a web-based platform. Our solution provides FPGA board access and debugging capabilities beyond the visual feedback provided by existing remote laboratories. We implemented a lab module that allows users to seamlessly incorporate into their FPGA design. The module minimizes hardware resource utilization while enabling the acquisition of a large number of data samples from the signal during the experiments by adaptively compressing the signal prior to data transmission. The results demonstrate an average compression ratio of 2.90 across three benchmark signals, indicating efficient signal acquisition and effective debugging and analysis. This method allows users to acquire more data samples than conventional methods. The proposed lab allows students to remotely test and debug their designs, bridging the gap between theory and practice in embedded system design.
Particle Swarm Optimization (PSO)-Based Distributed Power Control Algorithm f...Oyeniyi Samuel
This document summarizes a research paper that proposes a new particle swarm optimization (PSO)-based distributed power control algorithm for wireless radio systems. The algorithm aims to minimize transmitted power while achieving an acceptable quality of service (QoS) level, measured by carrier-to-interference ratio (CIR). It formulates the power control problem as a multi-objective optimization problem solved using PSO. Simulations show the proposed algorithm converges faster than conventional methods, with lower average transmitted power but comparable QoS. The algorithm is also modified to maximize throughput, with power constraints derived through iterative calculations.
Equilibrium and Kinetic Studies of Adsorption of Safranin-O from Aqueous Solu...Oyeniyi Samuel
This document presents a study on the equilibrium and kinetic modeling of adsorption of Safranin-O dye from aqueous solutions using pineapple peel waste (PPW) as a low-cost adsorbent. Batch experiments were conducted to analyze the effects of various parameters such as PPW dose, initial dye concentration, pH, and contact time. The experimental data fit the Freundlich isotherm model and followed pseudo-second order kinetics. Scanning electron microscopy and Fourier-transform infrared spectroscopy characterization showed changes in PPW surface morphology and functional groups before and after dye adsorption, indicating dye removal occurred via surface interactions. The results demonstrate that raw PPW is a potentially low-cost and effective adsorbent for removing
Design Description of a Tentacle Based Scanning SystemOyeniyi Samuel
This document describes the design of a tentacle-based 3D scanning device. The scanner uses a camera and two lasers for distance measurement via triangulation. As an object on a turntable rotates, the camera and lasers move up and down via a lead screw to scan the entire object. The scanner is intended to be low-cost and portable for use in scanning small objects up to 15x15x20 cm in size and 500g in weight. It is designed using inexpensive and readily available materials like a polymer composite for rigidity. The main mechanisms are NEMA stepper motors to control the turntable and lead screw for camera/laser movement.
Profiled Deck Composite Slab Strength Verification: A ReviewOyeniyi Samuel
This document reviews different methods for verifying the strength of profiled deck composite slabs (PDCS) without expensive laboratory testing. It discusses two common methods - the slope-intercept method and partial shear connection method - which both require experimental test data. The document also reviews attempts to use numerical modeling as an alternative to testing, but notes limitations in accurately modeling the complex shear behavior. It concludes that laboratory testing remains the most accurate assessment of PDCS strength, and further work is needed to develop a rational, reliability-based numerical approach to determine strength without testing.
Optimization of Mechanical Expression of Castor Seeds Oil (Ricinus communis) ...Oyeniyi Samuel
This document summarizes an optimization study that examined the effects of processing parameters (moisture content, roasting temperature, and roasting duration) on the oil yield from mechanical expression of castor seeds. The study used response surface methodology with a central composite design to evaluate 20 experimental runs across the parameters. Regression analysis found moisture content and roasting duration had significant individual effects on oil yield, while moisture content and roasting temperature had a significant interactive effect. The maximum observed oil yield was 26.5% at 6.68% moisture content, 100°C temperature, and 15 minutes duration. The model fit the data well with R2 values over 0.97. The optimal conditions predicted by the model were 7% moisture content
Inundation and Hazard Mapping on River Asa, using GISOyeniyi Samuel
This document discusses using GIS to create inundation and hazard maps of River Asa in Ilorin, Nigeria. Land use maps from 1976-2004 were digitized and analyzed, showing increases in built up area and cultivation over time. A digital elevation model was generated from contour lines. Rainfall data from 1984-2013 showed more years exceeding 100mm annually in later periods. Floodplains were mapped based on land use, rainfall, elevation, and slope data. Discharge values were calculated for return periods up to 200 years. The 50-year discharge value was used with GIS, HEC-RAS, and HEC-GeoRAS to produce an inundation map of areas at risk of flooding
A Review of Smart Grids Deployment Issues in Developing CountriesOyeniyi Samuel
This document provides a review of smart grid deployment issues in developing countries. It discusses several key challenges: 1) wide demand-supply gaps in developing nations have hindered smart grid deployments which require reliable energy supply; 2) rollouts of smart electricity meters have faced issues like high costs, electricity theft, and slow deployment; 3) cyberattacks, infrastructure theft, vandalism, and terrorism pose security risks for smart grids; and 4) poor research/investment, low budgets, and corruption have also impeded smart grid progress in developing nations. The document argues that addressing these challenges is important for enabling sustainable smart grid deployments.
NOx Emission in Iron and Steel Production: A Review of Control Measures for S...Oyeniyi Samuel
This document reviews control measures for nitrogen oxide (NOx) emissions from iron and steel production. It describes the iron and steel making processes that generate NOx emissions, including sintering, pelletizing, coking, blast furnace production, and basic oxygen furnace steelmaking. The mechanisms for thermal, fuel, and prompt NOx formation during combustion are explained. Environmental impacts of NOx emissions are also outlined. The document then analyzes NOx control technologies, including combustion modification with low-NOx burners and flue gas recirculation, and post-combustion approaches like selective catalytic reduction. Selective catalytic reduction uses ammonia injection and a catalyst to convert NOx to nitrogen and water and can
Artificial Neural Network Modelling of the Energy Content of Municipal Solid ...Oyeniyi Samuel
This document describes a study that used an artificial neural network model with backpropagation learning to predict the calorific (energy) value of municipal solid waste in major cities in Northern Nigeria. Experimental data on the energy content and composition of waste samples were used as input parameters for the neural network. Different numbers of neurons in the hidden layer were tested, and the model with eight neurons in the hidden layer produced the lowest error and highest accuracy compared to actual measured energy values, with a mean squared error of 4.377x10-5 and R2 value of 0.96881. This study demonstrated the artificial neural network approach can successfully predict energy content from municipal solid waste composition in Northern Nigeria.
Development of Inundation Map for Hypothetical Asa Dam Break using HEC-RAS an...Oyeniyi Samuel
This document describes the development of an inundation map for a hypothetical dam break scenario of the Asa Dam in Ilorin, Nigeria using HEC-RAS and ArcGIS modeling. Hydraulic modeling was conducted for a 100-year flood event to simulate water surface elevations along the 12 km river channel. The results showed that several important areas like industrial zones, residential areas, and places of worship would be inundated based on the water surface elevations exceeding local ground elevations. Floodplain boundaries were extracted from HEC-RAS and an inundation map was generated in ArcGIS to identify areas vulnerable to flooding from a potential dam failure.
Job Safety Assessment of Woodwork Industry in the South-western NigeriaOyeniyi Samuel
The document summarizes a study that assessed job safety in the woodworking industry in Southwest Nigeria. Through surveys of 310 woodworkers, the study found that 85.5% had suffered injuries. The most common risk factors reported were manual lifting, forceful gripping, wood dust, and exposure to hazardous chemicals. Finishing, planning/scraping, and hammering operations were most often linked to injuries. A job safety analysis identified high risks from environmental hazards, getting caught in machinery, cuts, and inhaling substances. Personal protective equipment and improper dressing were inadequate. The analysis provided recommendations to eliminate hazards and improve worker safety.
Anaerobicaly - Composted Environmental Wastes as Organic Fertilizer and Ident...Oyeniyi Samuel
This document summarizes a study that anaerobically composted sawdust, wood shavings, and poultry manure to produce organic fertilizer. The compost was high in nutrients like organic carbon, nitrogen, phosphorus, and minerals. Nine fungi species were isolated from the compost, including Aspergillus candidus, Aspergillus fumigatus, Penicillium aethiopicum, and Fusarium species. These fungi helped decompose the lignified materials during the composting process. The compost produced was found to be rich in organic matter and nutrients, making it a suitable supplement to inorganic fertilizers for sustainable crop production.
Security Architecture for Thin Client NetworkOyeniyi Samuel
This document summarizes a research paper on security architecture for thin client networks. It discusses some of the security challenges with thin client computing, such as the inability to identify users based on static IP addresses. It proposes using Dynamic Host Control Protocol (DHCP) to dynamically assign IP addresses to clients, enabling detection of MAC address spoofing. When login parameters don't match server information, an IP address conflict would be detected by the administrator. The paper also recommends segmenting the network and assigning a range of clients to each user account, making it possible for administrators to identify which network segment an attacker is on. All user data, applications and operating systems would be stored on the server rather than the client desktops.
Algorithm for the Dynamic Analysis of Plane Rectangular Rigid Frame Subjected...Oyeniyi Samuel
This document presents an algorithm for dynamically analyzing a plane rectangular rigid frame subjected to ground motion. The algorithm involves:
1) Using a matrix stiffness method and static condensation to reduce the global stiffness matrix size.
2) Deriving a characteristic polynomial equation from the condensed matrix and mass matrix.
3) Solving the polynomial equation using Newton-Raphson iteration to obtain eigenvalues and eigenvectors.
4) Calculating modal responses like shear force and overturning moment, which provide dynamic responses of the frame.
The algorithm aims to simplify dynamic analysis calculations that typically require software. It was applied to a three-story frame example.
Comparism of the Properties and Yield of Bioethanol from Mango and Orange WasteOyeniyi Samuel
This document summarizes a study that compared the properties and yield of bioethanol produced from mango and orange waste through fermentation. Samples of 100g mango waste, 100g orange waste, and a 50g/50g mixture were pretreated and fermented using Saccharomyces cerevisiae yeast. The highest ethanol yield was 19.98% for mango waste, 19.17% for orange waste, and 17.38% for the mixture. Analysis of variance showed no significant difference in properties except flash point, possibly due to moisture. Producing bioethanol from fruit wastes could provide an eco-friendly fuel alternative while reducing agricultural waste.
The document describes the development of a farm records software. The software was developed using Java programming languages and technologies like Java Server Faces, Enterprise Java Beans, and MySQL database. The software allows users to securely keep records of crops, livestock, finance and other farm operations. It provides functions for adding, updating, searching and retrieving farm records in an organized digital format compared to traditional paper-based record keeping. The software was tested against various use cases to identify and resolve bugs. It aims to help farmers better manage their farm operations and make informed decisions through analysis of past farm records data.
Compressive Strength of Concrete made from Natural Fine Aggregate Sources in ...Oyeniyi Samuel
This document presents the results of a study investigating the compressive strength of concrete made from five different sources of natural fine aggregate in Minna, Nigeria. Tests were conducted on the aggregates to determine properties like specific gravity, bulk density, moisture content, and sieve analysis. Concrete mixes were designed using aggregate-cement ratios of 1:2:4, 1:2:3, and 1:1:2 at water-cement ratios ranging from 0.4 to 0.6. The compressive strength of 150mm concrete cubes cured for 28 days ranged from 18.97 to 34.98 N/mm2 across the different aggregate sources and mix designs. Statistical models were developed relating the compressive strength to the water-
Evaluation of Chemical and Physico-Mechanical Properties of Ado-Ekiti Natural...Oyeniyi Samuel
This document evaluates the chemical and physical properties of natural moulding sands from Ado-Ekiti, Nigeria for use in foundry applications. Samples were collected from four locations around Ado-Ekiti and tested based on American Foundry Society guidelines. The chemical analysis found high contents of silica and aluminium oxide. Testing found the sands suitable for casting various metals except one sample. This study provides data on local sands' properties to enhance foundry industry and reduce foreign sand imports.
Modeling and Simulation of Pyrolysis Process for a Beech Wood MaterialOyeniyi Samuel
The document describes a study that used Aspen Plus software to model and simulate the pyrolysis process of beech wood. The model represented the pyrolysis reactor as a non-stoichiometric reactor (RYield) that decomposed the wood into solid, liquid, and gas products based on the wood's composition. The simulation was run at temperatures from 400-600°C and particle sizes from 1.6-2.0 mm. The results showed that carbon dioxide yield from gaseous products decreased with increasing temperature, while carbon monoxide and methane increased. Liquid products like acetic acid were affected more at temperatures over 500°C. The model was validated by comparing results to experimental data, with less than 1%
An Investigation into the Effectiveness of Machine Learning Techniques for In...Oyeniyi Samuel
The document investigates the effectiveness of machine learning techniques for intrusion detection. It evaluates six machine learning algorithms (Naive Bayes, Multi-Layer Perceptron Neural Networks, Support Vector Machine, Random Forests, Logistic Model Tree Induction, and Decision Tree) on the NSL-KDDTrain+ dataset. The experimental results show that the Logistic Model Tree Induction method performs best with a classification accuracy of 99.40%, F-measure of 0.991, and lowest false positive rate of 0.32%.
The CBC machine is a common diagnostic tool used by doctors to measure a patient's red blood cell count, white blood cell count and platelet count. The machine uses a small sample of the patient's blood, which is then placed into special tubes and analyzed. The results of the analysis are then displayed on a screen for the doctor to review. The CBC machine is an important tool for diagnosing various conditions, such as anemia, infection and leukemia. It can also help to monitor a patient's response to treatment.
Advanced control scheme of doubly fed induction generator for wind turbine us...IJECEIAES
This paper describes a speed control device for generating electrical energy on an electricity network based on the doubly fed induction generator (DFIG) used for wind power conversion systems. At first, a double-fed induction generator model was constructed. A control law is formulated to govern the flow of energy between the stator of a DFIG and the energy network using three types of controllers: proportional integral (PI), sliding mode controller (SMC) and second order sliding mode controller (SOSMC). Their different results in terms of power reference tracking, reaction to unexpected speed fluctuations, sensitivity to perturbations, and resilience against machine parameter alterations are compared. MATLAB/Simulink was used to conduct the simulations for the preceding study. Multiple simulations have shown very satisfying results, and the investigations demonstrate the efficacy and power-enhancing capabilities of the suggested control system.
CHINA’S GEO-ECONOMIC OUTREACH IN CENTRAL ASIAN COUNTRIES AND FUTURE PROSPECTjpsjournal1
The rivalry between prominent international actors for dominance over Central Asia's hydrocarbon
reserves and the ancient silk trade route, along with China's diplomatic endeavours in the area, has been
referred to as the "New Great Game." This research centres on the power struggle, considering
geopolitical, geostrategic, and geoeconomic variables. Topics including trade, political hegemony, oil
politics, and conventional and nontraditional security are all explored and explained by the researcher.
Using Mackinder's Heartland, Spykman Rimland, and Hegemonic Stability theories, examines China's role
in Central Asia. This study adheres to the empirical epistemological method and has taken care of
objectivity. This study analyze primary and secondary research documents critically to elaborate role of
china’s geo economic outreach in central Asian countries and its future prospect. China is thriving in trade,
pipeline politics, and winning states, according to this study, thanks to important instruments like the
Shanghai Cooperation Organisation and the Belt and Road Economic Initiative. According to this study,
China is seeing significant success in commerce, pipeline politics, and gaining influence on other
governments. This success may be attributed to the effective utilisation of key tools such as the Shanghai
Cooperation Organisation and the Belt and Road Economic Initiative.
artificial intelligence and data science contents.pptxGauravCar
What is artificial intelligence? Artificial intelligence is the ability of a computer or computer-controlled robot to perform tasks that are commonly associated with the intellectual processes characteristic of humans, such as the ability to reason.
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Artificial intelligence (AI) | Definitio
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Optimizing Gradle Builds - Gradle DPE Tour Berlin 2024Sinan KOZAK
Sinan from the Delivery Hero mobile infrastructure engineering team shares a deep dive into performance acceleration with Gradle build cache optimizations. Sinan shares their journey into solving complex build-cache problems that affect Gradle builds. By understanding the challenges and solutions found in our journey, we aim to demonstrate the possibilities for faster builds. The case study reveals how overlapping outputs and cache misconfigurations led to significant increases in build times, especially as the project scaled up with numerous modules using Paparazzi tests. The journey from diagnosing to defeating cache issues offers invaluable lessons on maintaining cache integrity without sacrificing functionality.
2. Ngene and Hahanov: Technologies for fault diagnosis of FPGA logic blocks. AZOJETE, 8: 37-45, 2012
38
Figure 1: FPGA structure
In most cases FPGAs end up in Printed circuit boards (PCB) alongside other chips and
passive elements. In order to test PCB interconnects and other components on board a boundary
scan infrastructure (BSI) is provided. Boundary scan infrastructure is primarily used for the
testing of component interconnect. As a standard all devices that are placed on PCB must also
contain boundary scan infrastructure for the testing of that component. Though FPGAs provide
infrastructure for implementing SoCs, they also contain BSI for their testing and programming.
The principle of boundary scan is to allow the outputs of each IC to be controlled and inputs to
be observed. A board with boundary scan infrastructure is shown in Figure 2 and the detail of a
typical boundary scan cell is depicted in Figure 3. Every boundary scan-compliant component
(e.g. FPGA) has common test architecture, shown in Figure 4.
Compliant component
Board
Boundary Scan Cell
Test Data In
TDI
Test Data Out
TDO
Serial data in
Serial data out
Internal system logic
E.g. FPGA
Figure 2: Board with Boundary Scan
Q2
Q2'
DQ1
Q1'
D
MUX
MUX
Clk UpdateMode
Shift/Load
Mode
Shift/Load
TDI
Serial In
Input pin
(or data from
core logic
TDO Serial Out
To core logic
(or Output pin)
Figure 3: Typical Boundary Scan Cell
3. Arid Zone Journal of Engineering, Technology and Environment. August, 2012; Vol. 8, 37-45
39
Any Internal
Register
Any Digital Chip
Identification Register
Instruction Register
TAP
Controller
1
1
1
Test Data In
TDI Test Data Out
TDO
Test Mode Select
TMS
Test Clock
TCK
Test Reset
TRST (Optional)*
Bypass Register
Figure 4: Boundary Scan Infrastructure IEEE 1149.1
In order to diagnose and repair faulty logic blocks within FPGA some level of redundancy is
provided inform of replacement units. The more redundancy that is provided the easier it
becomes to carryout replacement of multiple defective logic blocks. Physical defects in a chip,
resulting from manufacturing process or operation appear as logical or delay defects and lead to
malfunction of digital products. Defects are linked not only to gates or LUT-components, but
also to a particular place on the chip.
2. Previous Work
In recent years there have been dozens of works that address issues relating to the problem of
testing, diagnosis and repair of digital systems on chips FPGA. The critical issue of restoration
of functionality the FPGA depends largely on the effectiveness and efficiency of locating and
replacing failed components. The summary of various solutions that have been proposed include
but not limited to the following.
In Ross and Hall (2006), the duplication of logic elements or regions of the chip, leading to a
doubling of the hardware implementation was considered. When you locate a defective element
or area a switching from the defective component to a good one is done with the help of a
multiplexer). The proposed models for the repair of FPGAs from Xilinx can also be used for the
repair of Altera FPGAs since the basic unit of repair is a column and row. The use of genetic
algorithms to diagnose and restore functionality based on autonomous reconfiguration of FPGA
chip without any external control devices (Habermann et al., 2006). This result in high reliability
of defects diagnosis up to 99% and repair time of 36 milliseconds instead of 660 seconds
required for the standard configuration of the project. Restoration of functionality of FPGA
chips is not time-critical, by replacing the local CLB with a spare as suggested in Pontarelli et al.
(2006) and Koal and Vierhaus (2008). Moderate level of combining CLBs to be replaced for
mission-critical applications is in the order of thousands of logic elements.
4. Ngene and Hahanov: Technologies for fault diagnosis of FPGA logic blocks. AZOJETE, 8: 37-45, 2012
40
Repair of defective components in digital systems leads to the exclusion of the defective
component at first instance and then replacing it with a healthy component. In an autonomous
system this replacement is done independent of human intervention. This requires an extra
circuit to carry out this procedure. Such a circuit is known as built-in-self repair (BISR). There
are two procedures that exist for the replacement of the faulty component. One of the procedures
requires repetitive Place and Route procedures after diagnosis. Restoration of failed CLB can be
done by repeatedly carrying out the procedure of place and route to isolate the failed CLB.
Repetition of place and route is time consuming and therefore, not suitable for time critical
systems. In real time systems the preliminary preparation of all possible bitstreams are required
to isolate future defective areas as part of the redundant non-functional region of the chip.
In order to handle multiple defects that are not covered by a reserve area, the project should be
segmented, breaking it first into disjoint parts, which have their own maps of Place and Route. In
this case, you can repair a failed digital system with distributed n defects on the wafer with m
spare segments. In this case, the total chip area is n + m equal parts. This could be desirable for
only mission critical systems which require high availability.
3. Technology for diagnosing FPGA blocks
The main role in the diagnosis of faulty FPGA blocks is assigned to the built-in chip boundary
scan infrastructure (IEEE, 2001), which is aimed at solving practically all problems of service
support for FPGA functionality. Access Controller provides monitoring of all problematic
internal lines of the design with the help of boundary-scan register. The number of bits must
conform to a prescribed depth of diagnosis or diagnostic resolution, and therefore the number of
FPGA LUTs or cells. The service infrastructure for the diagnosis of defects in FPGA is shown in
Figure 5.
ATPG
Model
DUT
XOR
Boundary
Scan Register
Scoreboard
Diagnosis
Good
Observing
ATPG – Automatic Test Pattern Generator
DUT – Device Under Test
XOR – Exclusive OR
Figure 5: Process model for diagnosing FPGA
The exclusive-OR (XOR) block examines the module output response of the model and the real
device (DUT) on the test vectors coming from the internal oscillator input sequences. The
Boundary Scan Register Block is a multi-probe designed to monitor the state of all blocks or
cells and components of the chip. The Scoreboard module performs the function of analyzing the
results of monitoring for the diagnosis and subsequent repair of the components of SoC. The
result of diagnosis of chip is a set of faulty units to be excluded from a functional operation by
replacing them with spare components. An interesting solution to the problem of diagnosis can
be obtained through the use of Boolean algebra to analyze the fault table (FT) M, which is the
Cartesian product of the test T and the set of predetermined defects F. The output response
vector R is equal to the length of the distinguishable test segments, which allows the procedure
for search of defects to be used for coverage problem. This provides the most accurate results in
5. Arid Zone Journal of Engineering, Technology and Environment. August, 2012; Vol. 8, 37-45
41
a sum of product form (SOP), where each term is a possible option of the presence of subset or a
combination of defects in the device. The process model of diagnosis is presented in the
following form:
}.1,0{},,,{);()(
);,...,,...,,(;,1;,1,
);,...,,...,,();,...,,...,,(
,,,,
*
21
2121
jijiiiii
niij
mjni
FMTRTGTGR
RRRRRmjniMM
FFFFFTTTTT
RMFTA
(1)
The value of the coordinates of vector R is the result of the XOR operation on the generalized
model and the actual response output of the device. If the vector R is 1 for the i-th test segment
on at least one output of the device, the generalized state of the output is 1. Otherwise, the value
of the vector R is equal to 0.
4. Algebraic logic method for diagnosing faulty logic blocks
The solution to diagnostic problem is reduced to the analysis of fault table derived from the
simulation of the defects of FPGA components. This is achieved by writing a product of sums
(POS) of faults table rows recorded for which the output response vector R assumes the binary
value 1:
).(
1
,1,1
1
j
M
mjni
R
FF
iji
(2)
∧ - Logical conjunctive operator (logical AND); ∨ - Logical disjunctive operator (logical OR)
The product of sum (POS) obtained from fault table is transformed to a sum of product (SOP)
using the equivalence transformations (logical multiplication to minimization and absorption)
(Rossen, 2003). The result is a Boolean function, where the terms - logical product represents the
complete set of solutions in the form of a combination of defects (which gives the binary
coordinates of V at the outputs of the FPGA or its components):
}.1,0{),()(
1
2
11
,1,1
1
jjj
m
ji
aaa
babaj
M
mjni
R
kFkFF
m
iji
(3)
where: k is fixed number of 1s per row.
Equation 3 expresses diagnosis as a subset or combinations (multiple) of defects that need to be
further clarified by the use of additional internal sensing points using boundary-scan register.
The number of one’s (1s) in R forms the number of sum terms of POS (3). Each term is the
progressive (per line) recording of defects (through logical OR operation) affecting output
functionality. Table M1 is presented in the analytical form and by using the POS it is possible to
significantly reduce the amount of diagnostic information to locate defects. The subsequent
conversion of POS to SOP on the basis of the identities of Boolean algebra can significantly
reduce the Boolean function.
6. Ngene and Hahanov: Technologies for fault diagnosis of FPGA logic blocks. AZOJETE, 8: 37-45, 2012
42
The Algebra-logical method for a given a fault table M1 shown in figure 6 is based on the following
algorithm.
Figure 6: Fault Table
1. Definition of fault table rows corresponding to R equal to zero values in order to reset the
one (1) coordinates in the matched rows. In this case - this corresponds to row T5 in figure 6.
2. Location of all the columns that have zero values in the row coordinates corresponding to
R equal to zero. Reset the one (1s) values in the located columns. In this case: F2, F5, F6.
3. Remove from the fault table all rows and columns with only zero values (found in points 1
and 2). This is depicted in figure 7.
The empty cells in the table are zeroes and signify that a given test pattern T is unable to
detect a specific fault F. For simplicity 0 has not been shown in the empty cells.
Figure 7: Reduced Fault Table
4. Construction of a POS for every R= 1. POS is converted to SOP by multiplying all the sum
terms and further minimise the Boolean function using other minimization techniques. And this
is expressed in equation 4.
.
)()()()()(
434131
43431434143131
443431433331441411431311
3144414331314341
FFFFFF
FFFFFFFFFFFFFF
FFFFFFFFFFFFFFFFFFFFFFFF
FFFFFFFFFFFFFFFFF
(4)
The proposed algorithm is focused on the analysis of faults table in order to reduce its size and
simplify subsequent computations relating to the construction of SOP, which generates all the
solutions for the diagnosis of FPGA functionality. The algorithm enables the processing of
sparse faults tables when the number of coordinates with 1s values with respect to zero values is
not more than 20%. Further refinement of the diagnosis is only possible with the use of a multi-
sensor based on boundary-scan register (IEEE 2001).
Ti
Fj
F1 F2 F3 F4 F5 F6 Ri
T1 1 1 1
T2 1
T3 1 1 1 1
T4 1 1 1
T5 1 1 1 0
Ti
Fj
F1 F2 F3 F4 F5 F6 Ri
T1 1 1 1
T2 0 0 1
T3 1 1 0 1
T4 1 1 1
T5 0 0 0 0
Ti
Fj
F1 F3 F4 Ri
T1 1 1 1
T3 1 1 1
T4 1 1 1
M1 =
M1 =
=
7. Arid Zone Journal of Engineering, Technology and Environment. August, 2012; Vol. 8, 37-45
43
5. The vector-logical method of diagnosing faults
The processing of FT for diagnosis is performed according to scenario that is based on the use
of logical AND, logical OR and negation (NOT) operations on the rows of the fault table.
Analytic vector-logical model of diagnosis of multiple defects is determined by the conjunction
of two components, where the first is the disjunction of the vectors corresponding to the
coordinates of the output response vector with ones (1s) values and the second - an inversion of
the disjunctions of vectors corresponding to zero coordinates of R as expressed in equation 5.
i
R
i
R
MMMMF
ii 01
01
. (5)
The diagnostic model for a single defect is different in execution from the first step using
conjunction operation (instead of disjunction) of all vectors corresponding to the coordinates
with R equals 1 as expressed in equation 6.
i
R
i
R
MMMMF
ii 01
01
. (6)
Example1. In this example a multiple defects diagnosis of FPGA is carried out by using vector-
logical method for which specified faults table and output response vector are provided:
Table 1: Example of Multiple Defects Table
S/No. Ti
Fj
F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 R
1. T1 1 1 1
2. T2 1 1 0
3. T3 1 1 1 0
4. T4 1 0
5. T5 1 1 1
6. T6 1 1 0
7. T7 1 0
8. T8 1 1
9. T9 1 1 0
10. T10 1 0
11. T11 1 1 1 1
12.
∨
1
M 1 1 1 1 1 1
13.
∧
1
M 0 0 0 1 0 0 0 1 0 1 1
14.
∨
0
M 1 1 1 1 1 1 1 0
15. 0
M
0 0 0 1 0 0 0 1 0 1 1
16. F 0 0 0 1 0 0 0 1 0 1 1
Table 1 shows eleven test vectors (T1 – T11) used to diagnose ten faults (F1 – F10). The
processing of the fault table in accordance with equation (5) yields the results shown in the last
four rows (rows 12 to 15) of Table 1. The last row of the table 1 is derived using equation (6) by
taking logical conjunction of rows 13 and 15. This indicates the presence of defects in the
circuit, which is represented in a vector or a set-theoretic form F = (0001000101) = {F4, F8, F10}.
This shows that faults F4, F8, and F10 have been detected. Taking a closer look at the table you
find out that T1 detects two faults F4 and F10 and the two faults are not distinguishable but T8
8. Ngene and Hahanov: Technologies for fault diagnosis of FPGA logic blocks. AZOJETE, 8: 37-45, 2012
44
detects only F4. Most of the Test vectors could not distinguish the faults hence the use of
equation (6) to determine the exact fault and their subsequent location.
The list of detected faults can be further reduced by transforming this solution to SOP of the
multiple defects. This is achieved by masking vector F in table 1 using equation 7.
).(
1
1
FMFMF i
Ri
(7)
The resulting vectors, which is limited by the number of 1s available in R and the vectors are
logically multiplied. In addition, each vector can be compactly written as a disjunction of the
coordinates with ones (1s) values. The synthesis of the SOP results in equation 8.
.FFFFFFFFFFFFF
FFFFFFFFFFFFFFFF
)FF)(F)(F)(FF(F
8448101084481084
10481010484448104484
10448104
(8)
This result is interesting, thanks to the fact that the defects were written in the form of SOP,
which covers all 1s coordinates of R. It is now possible to eliminate the defect FF10 from the
list of faults.
The advantage of vector-logical method is in its use to analyse technological effectiveness of
the fault table with computational complexity that has a multiplicative dependence on the
number of defects and the power of test: mnQ . The method should be used with a
predominance of coordinates with ones (1s) values in the faults table when algebraic logic
method gives a high assessment by using Quine complexity for SOP and POS. The disadvantage
is the inability to represent all combinations of defects that form terms that cover the ones
coordinates of the output response vector.
6. Conclusions
The proposed methods of diagnosis: algebraic logic and vector-logical offer to a specialist in the
area of design and test of digital systems-on-chip mathematical tools that can accomplish
diagnosis of defective parts given a pre-built faults table. With the vector solutions that were
effectively obtained in the second method, we can represent all possible combinations of defects
in the form of terms of SOP, which is characteristic of the first method. The second method is
effective when the number of ones in a fault matrix exceeds 10-20%.
References
Habermann, S., Kothe, R. and Vierhaus, HT. 2006. Built-in self repair by reconfiguration of
FPGAs // Proceedings of the 12th IEEE International Symposium on On-Line Testing,
pp. 187-188.
IEEE 2001. IEEE Standard 1149.1: Test Access Port and Boundary-Scan Architecture.
Available from: https://standards.ieee.org/findstds/standard/1149.1-2001.html/ accessed
June 20, 2008.
Koal, T. and Vierhaus, HT. 2008. Basic Architecture for Logic Self Repair // 14th IEEE
International On-Line Testing Symposium. pp. 177–178.
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Kwang-Ting, C. 2006. The Need for a SiP Design and Test Infrastructure // IEEE Design and
Test of Computers, May–June, pp. 181.
Pontarelli, S., Ottavi, M., Vankamamidi, V., Salsano, A. and Lombardi, F. 2006. Reliability
Evaluation of Repairable/Reconfigurable FPGAs // 21st IEEE International Symposium
on Defect and Fault-Tolerance in VLSI Systems (DFT'06), October, pp. 227-235.
Ross, R. and Hall, R. 2006. A FPGA Simulation Using Asexual Genetic Algorithms for
Integrated Self-Repair // Adaptive Hardware and Systems, AHS 2006, First NASA/ESA
Conference, 15-18 June, 2006, pp. 301 – 304.
Rossen, K. 2003. Discrete Mathematics and its Applications, McGraw Hill, 2003. Pp 824.
Subhasish, M., Huang, WJ., Saxena, NR., Yu, SY. and McCluskey, EJ. 2004. Reconfigurable
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