As the demand for high speed Internet significantly increasing to meet the requirement of large data transfers, real-time communication and High Definition ( HD) multimedia transfer over IP, the IP based network products architecture must evolve and change. Application specific processors require high
performance, low power and high degree of programmability is the limitation in many general processor based applications. This paper describes the design of Ethernet packet processor for system-on-chip (SoC) which performs all core packet processing functions, including segmentation and reassembly, packetization classification, route and queue management which will speedup switching/routing performance making it
more suitable for Next Generation Networks (NGN). Ethernet packet processor design can be configured for use with multiple projects targeted to a FPGA device the system is designed to support 1/10/20/40/100 Gigabit links with a speed and performance advantage. VHDL has been used to implement and simulated the required functions in FPGA
ETHERNET PACKET PROCESSOR FOR SOC APPLICATIONcscpconf
As the demand for Internet expands significantly in numbers of users, servers, IP addresses,
switches and routers, the IP based network architecture must evolve and change. The design
of domain specific processors that require high performance, low power and high degree of
programmability is the bottleneck in many processor based applications. This paper describes
the design of ethernet packet processor for system-on-chip (SoC) which performs all core
packet processing functions, including segmentation and reassembly, packetization
classification, route and queue management which will speedup switching/routing
performance. Our design has been configured for use with multiple projects ttargeted to a
commercial configurable logic device the system is designed to support 10/100/1000 links with a speed advantage. VHDL has been used to implement and simulated the required functions in FPGA.
Stable Ethernet TCP/IP Real Time Communication In Industrial Embedded Applica...IJRES Journal
A stable Ethernet communication link in industrial embedded applications and networking are possible at all levels of industrial automation, especially in the controller level whereby the data exchanges in real-time communication is mandatory. Designing a Robust and Reliable Industrial Communications Infrastructure with Ethernet has traditionally been used to network enterprise workstations and to transfer non-real-time data. The success of Ethernet in the desktop world has been due to its simplicity, expandability, robustness, and affordable implementation. Based on Ethernet’s success as a data network, embedded soft real-time communication networks are being implemented with standard 100 Mbit/s Ethernet for economy, familiarity, and compatibility with enterprise networks. By using TCP/IP on top of Ethernet, embedded systems can become globally accessible from enterprise networks. This connectivity and interoperability is possible, and affordable using commodity off-the shelf (COTS) hardware and software, which has led to a recent surge in interest in embedded Ethernet.
Greetings from IGeekS Technologies ….
We were humbled to receive your enquiry regarding your academic project. We assure you to give all kinds of guidance for you to successfully complete your project.
IGeekS Technologies is a company located in Bangalore, India. We have being recognized as a quality provider of hardware and software solutions for the student’s in order carry out their academic Projects. We offer academic projects at various academic levels ranging from graduates to masters (Diploma, BCA, BE, M. Tech, MCA, M. Sc (CS/IT)). As a part of the development training, we offer Projects in Embedded Systems & Software to the Engineering College students in all major disciplines.
Academic Projects
As a part of our vision to provide a field experience to young graduates, we offering academic projects to MCA/B.Tech/BE/M.Tech/BCA students. Normally our way of project guidance will start with in-depth training. Why because unless and until a student know the technology, he cannot implement a project. We designed such courses based on industry requirements.
Placements
Our support never ends with training. We are maintaining a dedicated consulting division with 5 HR executives to assist our students to find good opportunities. Once a student finishes his course and project, immediately we will collect their profiles and will contact with the companies. Since January 2010, more than 450 students got placed with the help of our quality training, project assistance and placement support.
Facilities
• Project confirmation and completion certificate.
• Project base paper, synopsis and PPT.
• In-depth training by industry experts
• Project guidance from experienced people
• Regular seminars and group discussions
• Lab facility
• Good placement assistance
• A CD which contains all the required softwares and materials.
• Lab modules with 100s of examples to improve students programming skills.
Please visit our websites for further information:-
www.makefinalyearproject.com
www.igeekstechnoloiges.com
We look forward to have you in our office for a detailed technical discussion for in-depth understanding of the base paper and synopsis. Our training methodology includes to first prepare the candidates to the relevant technology used in the selected project and then start the project implementation; this gives the candidate the pre-requisite knowledge to understand not only the project but also the code in which the project is implemented.The program concludes by issuing of project completion certificate from our organization.
We attached the proposed project titles for the academic year 2015. Find the attachment. Select the titles we will send the synopsis and base paper...If have any own topic (base paper) pls send us.we will check and confirm the implementation.
We will explain the base paper and synopsis, for technical discussion or admission contact Mr. Nandu-9590544567.
ETHERNET PACKET PROCESSOR FOR SOC APPLICATIONcscpconf
As the demand for Internet expands significantly in numbers of users, servers, IP addresses,
switches and routers, the IP based network architecture must evolve and change. The design
of domain specific processors that require high performance, low power and high degree of
programmability is the bottleneck in many processor based applications. This paper describes
the design of ethernet packet processor for system-on-chip (SoC) which performs all core
packet processing functions, including segmentation and reassembly, packetization
classification, route and queue management which will speedup switching/routing
performance. Our design has been configured for use with multiple projects ttargeted to a
commercial configurable logic device the system is designed to support 10/100/1000 links with a speed advantage. VHDL has been used to implement and simulated the required functions in FPGA.
Stable Ethernet TCP/IP Real Time Communication In Industrial Embedded Applica...IJRES Journal
A stable Ethernet communication link in industrial embedded applications and networking are possible at all levels of industrial automation, especially in the controller level whereby the data exchanges in real-time communication is mandatory. Designing a Robust and Reliable Industrial Communications Infrastructure with Ethernet has traditionally been used to network enterprise workstations and to transfer non-real-time data. The success of Ethernet in the desktop world has been due to its simplicity, expandability, robustness, and affordable implementation. Based on Ethernet’s success as a data network, embedded soft real-time communication networks are being implemented with standard 100 Mbit/s Ethernet for economy, familiarity, and compatibility with enterprise networks. By using TCP/IP on top of Ethernet, embedded systems can become globally accessible from enterprise networks. This connectivity and interoperability is possible, and affordable using commodity off-the shelf (COTS) hardware and software, which has led to a recent surge in interest in embedded Ethernet.
Greetings from IGeekS Technologies ….
We were humbled to receive your enquiry regarding your academic project. We assure you to give all kinds of guidance for you to successfully complete your project.
IGeekS Technologies is a company located in Bangalore, India. We have being recognized as a quality provider of hardware and software solutions for the student’s in order carry out their academic Projects. We offer academic projects at various academic levels ranging from graduates to masters (Diploma, BCA, BE, M. Tech, MCA, M. Sc (CS/IT)). As a part of the development training, we offer Projects in Embedded Systems & Software to the Engineering College students in all major disciplines.
Academic Projects
As a part of our vision to provide a field experience to young graduates, we offering academic projects to MCA/B.Tech/BE/M.Tech/BCA students. Normally our way of project guidance will start with in-depth training. Why because unless and until a student know the technology, he cannot implement a project. We designed such courses based on industry requirements.
Placements
Our support never ends with training. We are maintaining a dedicated consulting division with 5 HR executives to assist our students to find good opportunities. Once a student finishes his course and project, immediately we will collect their profiles and will contact with the companies. Since January 2010, more than 450 students got placed with the help of our quality training, project assistance and placement support.
Facilities
• Project confirmation and completion certificate.
• Project base paper, synopsis and PPT.
• In-depth training by industry experts
• Project guidance from experienced people
• Regular seminars and group discussions
• Lab facility
• Good placement assistance
• A CD which contains all the required softwares and materials.
• Lab modules with 100s of examples to improve students programming skills.
Please visit our websites for further information:-
www.makefinalyearproject.com
www.igeekstechnoloiges.com
We look forward to have you in our office for a detailed technical discussion for in-depth understanding of the base paper and synopsis. Our training methodology includes to first prepare the candidates to the relevant technology used in the selected project and then start the project implementation; this gives the candidate the pre-requisite knowledge to understand not only the project but also the code in which the project is implemented.The program concludes by issuing of project completion certificate from our organization.
We attached the proposed project titles for the academic year 2015. Find the attachment. Select the titles we will send the synopsis and base paper...If have any own topic (base paper) pls send us.we will check and confirm the implementation.
We will explain the base paper and synopsis, for technical discussion or admission contact Mr. Nandu-9590544567.
International Journal of Engineering and Science Invention (IJESI)inventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online.
Fault Injection Approach for Network on Chipijsrd.com
Packet-based on-chip interconnection networks, or Network-on-Chips (NoCs) are progressively replacing global on-chip interconnections in Multi-processor System-on-Chips (MP-SoCs) thanks to better performances and lower power consumption. However, modern generations of MP-SoCs have an increasing sensitivity to faults due to the progressive shrinking technology. Consequently, in order to evaluate the fault sensitivity in NoC architectures, there is the need of accurate test solution which allows evaluating the fault tolerance capability of NoCs. Presents an innovative test architecture based on a dual-processor system which is able to extensively test mesh based NoCs. The proposed solution improves previously developed methods since it is based on a NoC physical implementation which allows investigating the effects induced by several kind of faults thanks to the execution of on-line fault injection within all the network interface and router resources during NoC run-time operations. The solution has been physically implemented on an FPGA platform using a NoC emulation model adopting standard communication protocols. The obtained results demonstrated the effectiveness of the developed solution in term of testability and diagnostic capabilities and make our solutions suitable for testing large scale.
InfiniBand In-Network Computing Technology and Roadmapinside-BigData.com
In this video from the UK HPC Conference, Richard Graham from Mellanox presents: InfiniBand In-Network Computing Technology and Roadmap.
"In-Network Computing transforms the data center interconnect to become a "distributed CPU", and "distributed memory", enables to overcome performance barriers and to enable faster and more scalable data analysis. HDR 200G InfiniBand In-Network Computing technology includes several elements - Scalable Hierarchical Aggregation and Reduction Protocol (SHARP), smart Tag Matching and rendezvoused protocol, and more. These technologies are in use at some of the recent large scale supercomputers around the world, including the top TOP500 platforms. The session will discuss the InfiniBand In-Network Computing technology and performance results, as well as view to future roadmap."
Watch the video:
Learn more: http://mellanox.com
and
http://hpcadvisorycouncil.com/events/2019/uk-conference/agenda.php
Sign up for our insideHPC Newsletter: http://insidehpc.com/newsletter
Performance analysis and implementation of modified sdm based noc for mpsoc o...eSAT Journals
Abstract To meet todays demanding requirements lowpower consumption, high performance while maintaing flexibility and scalability,
system-On-Chip will combine several number of processors cores and other IPs with network-On-chip. To implement NoC based
MPSoC on an FPGA, NoCs should provide guaranteed services and be run-time reconfigurable. Current TDM and SDM based
NoCs takes more area and would not support run-time reconfiguration. This paper presents modified spatial division multiplexing
based NoC on FPGA, in this we have modified complex network interface and proposed flexible network interface and efficient
SDM based NoC.This architecture explored feasibility of connection requirements from IP cores during run-time.
Keywords: NoC, MPSoC, FPGA, NoCs, SDM Based NoC
The router is a network device that is used to connect subnetwork and packet-switched networking by directing the data packets to the intended IP addresses. It succeeds the traffic between different systems and allows several devices to share the internet connection. The router is applicable for the effective commutation in system on chip (SoC) modules for network on chip (NoC) communication. The research paper emphasizes the design of the two dimensional (2D) router hardware chip in the Xilinx integrated system environment (ISE) 14.7 software and further logic verification using the data packets transmitted from all input/output ports. The design evaluation is done based on the pre-synthesis device utilization summary relating to different field programmable gate array (FPGA) boards such as Spartan-3E (XC3S500E), Spartan-6 (XC6SLX45), Virtex-4 (XC4VFX12), Virtex-5 (XC5VSX50T), and Virtex-7 (XC7VX550T). The 64-bit data logic is verified on the different ports of the router configuration in the Xilinx and Modelsim waveform simulator. The Virtex-7 has proven the fast-switching speed and optimal hardware parameters in comparison to other FPGAs.
High speed customized serial protocol for IP integration on FPGA based SOC ap...IJMER
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
International Journal of Modern Engineering Research (IJMER) covers all the fields of engineering and science: Electrical Engineering, Mechanical Engineering, Civil Engineering, Chemical Engineering, Computer Engineering, Agricultural Engineering, Aerospace Engineering, Thermodynamics, Structural Engineering, Control Engineering, Robotics, Mechatronics, Fluid Mechanics, Nanotechnology, Simulators, Web-based Learning, Remote Laboratories, Engineering Design Methods, Education Research, Students' Satisfaction and Motivation, Global Projects, and Assessment…. And many more.
Turbo codes are error-correcting codes with performance that is close to the
Shannon theoretical limit (SHA). The motivation for using turbo codes is
that the codes are an appealing mix of a random appearance on the channel
and a physically realizable decoding structure. The communication systems
have the problem of latency, fast switching, and reliable data transfer. The
objective of the research paper is to design and turbo encoder and decoder
hardware chip and analyze its performance. Two convolutional codes are
concatenated concurrently and detached by an interleaver or permuter in the
turbo encoder. The expected data from the channel is interpreted iteratively
using the two related decoders. The soft (probabilistic) data about an
individual bit of the decoded structure is passed in each cycle from one
elementary decoder to the next, and this information is updated regularly.
The performance of the chip is also verified using the maximum a posteriori
(MAP) method in the decoder chip. The performance of field-programmable
gate array (FPGA) hardware is evaluated using hardware and timing
parameters extracted from Xilinx ISE 14.7. The parallel concatenation offers
a better global rate for the same component code performance, and reduced
delay, low hardware complexity, and higher frequency support.
International Journal of Engineering and Science Invention (IJESI)inventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online.
Fault Injection Approach for Network on Chipijsrd.com
Packet-based on-chip interconnection networks, or Network-on-Chips (NoCs) are progressively replacing global on-chip interconnections in Multi-processor System-on-Chips (MP-SoCs) thanks to better performances and lower power consumption. However, modern generations of MP-SoCs have an increasing sensitivity to faults due to the progressive shrinking technology. Consequently, in order to evaluate the fault sensitivity in NoC architectures, there is the need of accurate test solution which allows evaluating the fault tolerance capability of NoCs. Presents an innovative test architecture based on a dual-processor system which is able to extensively test mesh based NoCs. The proposed solution improves previously developed methods since it is based on a NoC physical implementation which allows investigating the effects induced by several kind of faults thanks to the execution of on-line fault injection within all the network interface and router resources during NoC run-time operations. The solution has been physically implemented on an FPGA platform using a NoC emulation model adopting standard communication protocols. The obtained results demonstrated the effectiveness of the developed solution in term of testability and diagnostic capabilities and make our solutions suitable for testing large scale.
InfiniBand In-Network Computing Technology and Roadmapinside-BigData.com
In this video from the UK HPC Conference, Richard Graham from Mellanox presents: InfiniBand In-Network Computing Technology and Roadmap.
"In-Network Computing transforms the data center interconnect to become a "distributed CPU", and "distributed memory", enables to overcome performance barriers and to enable faster and more scalable data analysis. HDR 200G InfiniBand In-Network Computing technology includes several elements - Scalable Hierarchical Aggregation and Reduction Protocol (SHARP), smart Tag Matching and rendezvoused protocol, and more. These technologies are in use at some of the recent large scale supercomputers around the world, including the top TOP500 platforms. The session will discuss the InfiniBand In-Network Computing technology and performance results, as well as view to future roadmap."
Watch the video:
Learn more: http://mellanox.com
and
http://hpcadvisorycouncil.com/events/2019/uk-conference/agenda.php
Sign up for our insideHPC Newsletter: http://insidehpc.com/newsletter
Performance analysis and implementation of modified sdm based noc for mpsoc o...eSAT Journals
Abstract To meet todays demanding requirements lowpower consumption, high performance while maintaing flexibility and scalability,
system-On-Chip will combine several number of processors cores and other IPs with network-On-chip. To implement NoC based
MPSoC on an FPGA, NoCs should provide guaranteed services and be run-time reconfigurable. Current TDM and SDM based
NoCs takes more area and would not support run-time reconfiguration. This paper presents modified spatial division multiplexing
based NoC on FPGA, in this we have modified complex network interface and proposed flexible network interface and efficient
SDM based NoC.This architecture explored feasibility of connection requirements from IP cores during run-time.
Keywords: NoC, MPSoC, FPGA, NoCs, SDM Based NoC
The router is a network device that is used to connect subnetwork and packet-switched networking by directing the data packets to the intended IP addresses. It succeeds the traffic between different systems and allows several devices to share the internet connection. The router is applicable for the effective commutation in system on chip (SoC) modules for network on chip (NoC) communication. The research paper emphasizes the design of the two dimensional (2D) router hardware chip in the Xilinx integrated system environment (ISE) 14.7 software and further logic verification using the data packets transmitted from all input/output ports. The design evaluation is done based on the pre-synthesis device utilization summary relating to different field programmable gate array (FPGA) boards such as Spartan-3E (XC3S500E), Spartan-6 (XC6SLX45), Virtex-4 (XC4VFX12), Virtex-5 (XC5VSX50T), and Virtex-7 (XC7VX550T). The 64-bit data logic is verified on the different ports of the router configuration in the Xilinx and Modelsim waveform simulator. The Virtex-7 has proven the fast-switching speed and optimal hardware parameters in comparison to other FPGAs.
High speed customized serial protocol for IP integration on FPGA based SOC ap...IJMER
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
International Journal of Modern Engineering Research (IJMER) covers all the fields of engineering and science: Electrical Engineering, Mechanical Engineering, Civil Engineering, Chemical Engineering, Computer Engineering, Agricultural Engineering, Aerospace Engineering, Thermodynamics, Structural Engineering, Control Engineering, Robotics, Mechatronics, Fluid Mechanics, Nanotechnology, Simulators, Web-based Learning, Remote Laboratories, Engineering Design Methods, Education Research, Students' Satisfaction and Motivation, Global Projects, and Assessment…. And many more.
Turbo codes are error-correcting codes with performance that is close to the
Shannon theoretical limit (SHA). The motivation for using turbo codes is
that the codes are an appealing mix of a random appearance on the channel
and a physically realizable decoding structure. The communication systems
have the problem of latency, fast switching, and reliable data transfer. The
objective of the research paper is to design and turbo encoder and decoder
hardware chip and analyze its performance. Two convolutional codes are
concatenated concurrently and detached by an interleaver or permuter in the
turbo encoder. The expected data from the channel is interpreted iteratively
using the two related decoders. The soft (probabilistic) data about an
individual bit of the decoded structure is passed in each cycle from one
elementary decoder to the next, and this information is updated regularly.
The performance of the chip is also verified using the maximum a posteriori
(MAP) method in the decoder chip. The performance of field-programmable
gate array (FPGA) hardware is evaluated using hardware and timing
parameters extracted from Xilinx ISE 14.7. The parallel concatenation offers
a better global rate for the same component code performance, and reduced
delay, low hardware complexity, and higher frequency support.
Multi port network ethernet performance improvement techniquesIJARIIT
An Ethernet has its own importance and space in network subsystem. In today’s resource-intensive engineering the
applications need to deal with the real-time data processing, server virtualization, and high-volume data transactions. The realtime
technologies such as video on demand and Voice over IP operations demand the network devices with efficient network
data processing as well as better networking bandwidth. The performance is the major issues with the multi-port network
devices. It requires the sufficient network bandwidth and CPU processing speed to process the real-time data at the context.
And this demand is goes on increasing. The new multi-port hardware technologies can help to improvements in the
performance of the virtualized server environments. But, these hardware technologies having their own limitations in terms of
CPU utilization levels and power consumption. It also impacts on latency and the overall system cost. This thesis will provide
the insights to some of the key configuration decisions at hardware as well as software designs in order to facilitate multi-port
network devices performance improvement over the existing infrastructure. This thesis will also discuss the solutions such as
Virtual LAN and balanced or symmetric network to reduce the cost and hardware dependency to improve the multi-port
network system performance significantly over the currently existing infrastructure. This performance improvement includes
CPU utilization and bandwidth in the heavy network loads.
FPGA IMPLEMENTATION OF PRIORITYARBITER BASED ROUTER DESIGN FOR NOC SYSTEMSIAEME Publication
An efficient Priority-Arbiter based Router is designed along with 2X2 and 3X3 mesh
topology based NOC architecture are designed. The Priority –Arbiter based Router
design includes Input registers, Priority arbiter, and XY- Routing algorithm. The
Priority-Arbiter based Router and NOC 2X2 and 3X3 Router designs are synthesized
and implemented using Xilinx ISE Tool and simulated using Modelsim6.5f. The
implementation is done by Artix-7 FPGA device, and the physically debugging of the
NOC 2X2 Router design is verified using Chipscope pro tool. The performance results
are analyzed in terms of the Area (Slices, LUT’s), Timing period, and Maximum
operating frequency. The comparison of the Priority-Arbiter based Router is made
concerning previous similar architecture with improvements.
FPGA IMPLEMENTATION OF PRIORITYARBITER BASED ROUTER DESIGN FOR NOC SYSTEMSIAEME Publication
An efficient Priority-Arbiter based Router is designed along with 2X2 and 3X3 mesh
topology based NOC architecture are designed. The Priority –Arbiter based Router
design includes Input registers, Priority arbiter, and XY- Routing algorithm. The
Priority-Arbiter based Router and NOC 2X2 and 3X3 Router designs are synthesized
and implemented using Xilinx ISE Tool and simulated using Modelsim6.5f. The
implementation is done by Artix-7 FPGA device, and the physically debugging of the
NOC 2X2 Router design is verified using Chipscope pro tool. The performance results
are analyzed in terms of the Area (Slices, LUT’s), Timing period, and Maximum
operating frequency. The comparison of the Priority-Arbiter based Router is made
concerning previous similar architecture with improvements.
Many intellectual property (IP) modules are present in contemporary system on chips (SoCs). This could provide an issue with interconnection among different IP modules, which would limit the system's ability to scale. Traditional bus-based SoC architectures have a connectivity bottleneck, and network on chip (NoC) has evolved as an embedded switching network to address this issue. The interconnections between various cores or IP modules on a chip have a significant impact on communication and chip performance in terms of power, area latency and throughput. Also, designing a reliable fault tolerant NoC became a significant concern. In fault tolerant NoC it becomes critical to identify faulty node and dynamically reroute the packets keeping minimum latency. This study provides an insight into a domain of NoC, with intention of understanding fault tolerant approach based on the XY routing algorithm for 4×4 mesh architecture. The fault tolerant NoC design is synthesized on field programmable gate array (FPGA).
Design and implementation of secured agent based NoC using shortest path rout...IJECEIAES
Network on chip (NoC) is a scalable interconnection architecture for every increasing communication demand between many processing cores in system on chip design. Reliability aspects are becoming an important issue in fault tolerant architecture. Hence there is a demand for fault tolerant Agent architecture with suitable routing algorithm which plays a vital role in order to enhance the NoC performance. The proposed fault tolerant Agent based NoC method is used to enhance the reliability and performance of the Multiprocessor System on Chip (MPSoC) design against faulty links and nodes. These agents are placed in hierarchical manner to collect, process, classify and distribute different fault information related to the faulty links and nodes of the network. This fault information is used for further packet routing in the network with the help of shortest path routing algorithm. In addition to this the agent will provide the security for the node by setting firewall, which then decides whether the packet has to be processed or not. This intern provides high performance, low latency NoC by avoiding deadlock and live lock with low area overhead.
Communication Performance Over A Gigabit Ethernet NetworkIJERA Editor
A present computing imposes heavy demands on the optical communication network. Gigabit Ethernet technology can provide the required bandwidth to meet these demands. However, it has also involve the communication Impediment to progress from network media to TCP(Transfer control protocol) processing. In this paper, present an overview of Gigabit per second Ethernet technology and study the end-to-end Gigabit Ethernet communication bandwidth and retrieval time. Performance graphs are collected using NetPipe in this clearly show the performance characteristics of TCP/IP over Gigabit Ethernet. These indicate the impact of a number of factors such as processor speeds, network adaptors, versions of the Linux Kernel or opnet softwar and device drivers, and TCP/IP(Internet protocol) tuning on the performance of Gigabit Ethernet between two Pentium II/350 PCs. Among the important conclusions are the marked superiority of the 2.1.121 and later development kernels and 2.2.x production kernels of Linux or opnet softwar used and that the ability to increase the MTU(maximum transmission unit) Further than the Ethernet standard of 1500 could significantly enhance the throughput reachable.
International Journal of Engineering Research and Development (IJERD)IJERD Editor
International Journal of Engineering Research and Development is an international premier peer reviewed open access engineering and technology journal promoting the discovery, innovation, advancement and dissemination of basic and transitional knowledge in engineering, technology and related disciplines.
Similar to HIGH PERFORMANCE ETHERNET PACKET PROCESSOR CORE FOR NEXT GENERATION NETWORKS (20)
Trend-Based Networking Driven by Big Data Telemetry for Sdn and Traditional N...ijngnjournal
Organizations face a challenge of accurately analyzing network data and providing automated action based on the observed trend. This trend-based analytics is beneficial to minimize the downtime and improve the performance of the network services, but organizations use different network management tools to understand and visualize the network traffic with limited abilities to dynamically optimize the network. This research focuses on the development of an intelligent system that leverages big data
telemetry analysis in Platform for Network Data Analytics (PNDA) to enable comprehensive trendbased networking decisions. The results include a graphical user interface (GUI) done via a web application for effortless management of all subsystems, and the system and application developed in
this research demonstrate the true potential for a scalable system capable of effectively benchmarking the network to set the expected behavior for comparison and trend analysis. Moreover, this research provides a proof of concept of how trend analysis results are actioned in both a traditional network and a software-defined network (SDN) to achieve dynamic, automated load balancing.
TREND-BASED NETWORKING DRIVEN BY BIG DATA TELEMETRY FOR SDN AND TRADITIONAL N...ijngnjournal
Organizations face a challenge of accurately analyzing network data and providing automated action
based on the observed trend. This trend-based analytics is beneficial to minimize the downtime and
improve the performance of the network services, but organizations use different network management
tools to understand and visualize the network traffic with limited abilities to dynamically optimize the
network. This research focuses on the development of an intelligent system that leverages big data
telemetry analysis in Platform for Network Data Analytics (PNDA) to enable comprehensive trendbased networking decisions. The results include a graphical user interface (GUI) done via a web
application for effortless management of all subsystems, and the system and application developed in
this research demonstrate the true potential for a scalable system capable of effectively benchmarking
the network to set the expected behavior for comparison and trend analysis. Moreover, this research
provides a proof of concept of how trend analysis results are actioned in both a traditional network and
a software-defined network (SDN) to achieve dynamic, automated load balancing.
PERFORMANCE PREDICTION OF 5G: THE NEXT GENERATION OF MOBILE COMMUNICATIONijngnjournal
The 5G standard is a mobile communication of the 5th generation, which presupposes an increase of the information exchange speed up to 10 Gbit/s. It is 30 times quicker than the speed of 4G network. It is a new stage in the development of technologies connecting society. This standard will provide an unlimited access to the network for individual users and devices. When developing the 5G standard, the advanced opportunities of LTE and HSPA, as well as other technologies of a radio access focused on the solution of specific objectives are considered. The main advantage of the mass introduction of the 5G communication development represents the so-called Internet of Things (IoT). There the devices and not people will be the main consumers of traffic. The functional requirements of5G networks, their speed, and its traffic parameters for HD video services and massifs of M2M-devices are analyzed in the paper. They will have been the most demandedones by 2020.
PERFORMANCE EVALUATION OF VERTICAL HARD HANDOVERS IN CELLULAR MOBILE SYSTEMSijngnjournal
With the rapid increase of new and diverse cellular mobile services, the overlapping of cells has become typical in the majority of the coverage area of the network. Vertical handovers occur between two layers of cells when a user is switched from one layer to the other. In this paper we investigate the influence of network parameters on vertical hard handover performance in a cell environment. The work considers two layers of cells: a layer of macrocells and a layer of microcells. Handover requests enter the macrocell from neighbor macrocells and from microcells that belong to a different layer. Using Markov chain analysis and simulation we calculate network performance parameters such as mean queue delay, handover dropping probability and channel utilization. We also compare the handover performance for the macrocell and macrocell traffic separately. Our results show the influence of total channels, maximum queue size and handover request arrival rate on handover performance. They also show that when the traffic from each layer is treated with equal priority in the system, the performance of each layer is comparable.
PERFORMANCE EVALUATION OF VERTICAL HARD HANDOVERS IN CELLULAR MOBILE SYSTEMSijngnjournal
With the rapid increase of new and diverse cellular mobile services, the overlapping of cells has become typical in the majority of the coverage area of the network. Vertical handovers occur between two layers of cells when a user is switched from one layer to the other. In this paper we investigate the influence of network parameters on vertical hard handover performance in a cell environment. The work considers two layers of cells: a layer of macrocells and a layer of microcells. Handover requests enter the macrocell from neighbor macrocells and from microcells that belong to a different layer. Using Markov chain analysis and simulation we calculate network performance parameters such as mean queue delay, handover dropping probability and channel utilization. We also compare the handover performance for the macrocell and macrocell traffic separately. Our results show the influence of total channels, maximum queue size and handover request arrival rate on handover performance. They also show that when the traffic from each layer is treated with equal priority in the system, the performance of each layer is comparable.
COMPARISON OF RADIO PROPAGATION MODELS FOR LONG TERM EVOLUTION (LTE) NETWORKijngnjournal
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The Performance of a Cylindrical Microstrip Printed Antenna for TM10 Mode as...ijngnjournal
A temperature is one of the parameters that have a great effect on the performance of microstrip antennas for TM10 mode at 2.4 GHz frequency range. The effect of temperature on a resonance frequency, input impedance, voltage standing wave ratio, and return loss on the performance of a cylindrical microstrip printed antenna is studied in this paper. The effect of temperature on electric and magnetic fields are also studied. Three different substrate materials RT/duroid-5880 PTFE, K-6098 Teflon/Glass, and Epsilam-10 ceramic-filled Teflon are used for verifying the new model.
Optimization of Quality of Service Parameters for Dynamic Channel Allocation ...ijngnjournal
As the spectrum for wireless transmission gets crowded due to the increase in the users and applications, the efficient use of the spectrum is a major challenge in today’s world. A major affecting factor is the inefficient usage of the frequency bands. Interference in the neighboring cells affects the reuse of the frequency bands. In this paper, some of the quality of service parameters such as residual bandwidth, number of users, duration of calls, frequency of calls and priority are considered. This paper presents work based on the optimization of dynamic channel allocation using genetic algorithm (GA). This attempts to allocate the channel to users such that overall congestion in the network is minimized by reusing already allocated frequencies. The working of Genetic Algorithm which is used in the optimization procedure is also explained. The optimized channel is then compared with a non-optimized channel to check the efficiency of the genetic algorithm.
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SERVICES AS PARAMETER TO PROVIDE BEST QOS : AN ANALYSIS OVER WIMAXijngnjournal
In this paper it is proposed to provide the QoS to the user by using the degradation of service under hostile environment being itself be a parameter to improve the QoS. Here the relation between the service and environment of its best performance drawn on the basis of simulation and analysis .The service then taken as a parameter to decide present environment of the user and to take measurable steps to improve the QoS either doing handover to nearby station or increasing power or to provide some marginal bandwidth etc.All analysis done over a WiMax network i.e. being designed and simulated using the Qualnet wireless simulator.
ENSURING QOS GUARANTEES IN A HYBRID OCS/OBS NETWORKijngnjournal
The bursting aggregation assembly in edge nodes is one of the key technologies in OBS (Optical Burst Switching) network, which has a direct impact on flow characteristics and packet loss rate. An optical burst assembly technique supporting QoS is presented through this paper, which can automatically adjust the threshold along with the increasing and decreasing volume of business, reduce the operational burst, and generate corresponding BDP (Burst Data Packet) and BCP (Burst Control Packet). In addition to the burst aggregation technique a packet recovery technique by restoration method is also described. The data packet loss due to the physical optical link failure is not currently included in the QoS descriptions. This link failure is also a severe problem which reduces the data throughput of the transmitter node. A mechanism for data recovery from this link failure is vital for guaranteeing the QoS demanded by each user. So this paper will also discusses a specific protocol for reducing the packet loss by utilizing the
features of both optical circuit switching (OCS) and Optical Burst switching (OBS) techniques
SECURITY ANALYSIS AND DELAY EVALUATION FOR SIP-BASED MOBILE MASS EXAMINATION ...ijngnjournal
IP Multimedia Subsystem (IMS) is considered to be one of the important features in Mobile Next Generation Networks (MNGN). It adds value to the mobile services and applications by integrating mobile network resources, such as location, billing and authentication. This is achieved by enabling a third party access to network resources. In previous work [1] we have presented a testbed to be used as platform for testing mobile application prior to actual deployment. We have chosen a novel IMS based MObile Mass EXamination (MOMEX) system to showcase the benefit of designing an IMS based mobile application. We identify two aspects essential to of the application namely security threats and delay analysis. In this paper we identify MOMEX security threats and suggest strategies to mitigate system vulnerabilities. We then
evaluate the performance of MOMEX system in terms of delay and security threats and vulnerabilities. The results presented show system performance limitation and tradeoffs.
OPTIMIZATION OF QOS PARAMETERS IN COGNITIVE RADIO USING ADAPTIVE GENETIC ALGO...ijngnjournal
Genetic algorithm based optimization rely on explicit relationships between parameters, observations and criteria. GA based optimization when done in cognitive radio can provide a criteria to accommodate the secondary users in best possible space in the spectrum by interacting with the dynamic radio environment at real time. In this paper we have proposed adaptive genetic algorithm with adapting crossover and mutation parameters for the reasoning engine in cognitive radio to obtain the optimum radio configurations. This method ensure better controlling of the algorithm parameters and hence the increasing the performance. The main advantage of genetic algorithm over other soft computing techniques is its multi – objective handling capability. We focus on spectrum management with a hypothesis that inputs are provided by either sensing information from the radio environment or the secondary user. Also the QoS requirements condition is also specified in the hypothesis. The cognitive radio will sense the radio frequency parameter from the environment and the reasoning engine in the cognitive radio will take the required decisions in order to provide new spectrum allocation as demanded by the user. The transmission parameters which can be taken into consideration are modulation method, bandwidth, data rate, symbol rate, power consumption etc. We simulated cognitive radio engine which is driven by genetic algorithm to determine the optimal set of radio transmission parameters. We have fitness objectives to guide one system to an optimal state. These objectives are combined to one multi – objective fitness function using weighted sum approach so that each objective can be represented by a rank which represents the importance of each objective. We have transmission parameters as decision variables and environmental parameters are used as inputs to the objective function. We have compared the proposed adaptive genetic algorithm (AGA) with conventional genetic algorithm (CGA) with same set of conditions. MATLAB simulations were used to analyze the scenarios
ESTIMATION AND COMPENSATION OF INTER CARRIER INTERFERENCE IN WIMAX PHYSICAL L...ijngnjournal
WiMAX is Wireless Interoperability for Microwave Access has emerged as a promising solution for transmission of higher data rates for fixed and mobile applications. IEEE 802.16d and e are the standards proposed by WiMAX group for fixed and mobile. As the wireless channel have so many limitation Such as Multipath, Doppler spread, Delay spread and Line Of Sight (LOS)/Non Line Of Sight (NLOS) components. To attain higher data rates the Multi Carrier System with Multiple Input and Multiple Output (MIMO) is incorporated in the WiMAX. The Orthogonal Frequency Division Multiplexing (OFDM) is a multi carrier technique used with the WiMAX systems. In OFDM the available spectrum is split into numerous narrow band channels of dissimilar frequencies to achieve high data rate in a multi path fading environment. And all these sub carriers are considered to be orthogonal to each other. As the number of sub carriers is increased there is no guarantee of sustained orthogonality, i.e. at some point the carriers are not
independent to each other, and hence where the orthogonality can be loosed which leads to interference and also owing to the synchronization between transmitter and receiver local oscillator, it causes interference known as Inter Carrier Interference (ICI). The systems uses MIMO-OFDM will suffer with the effects of ICI and Carrier Frequency Offset (CFO) “ε”. However these affect the power leakage in the midst of sub carriers, consequently degrading the system performance. In this paper a new approach is proposed in order to reduce the ICI caused in WiMAX and improve the system performance. In this scheme at the transmitter side the modulated data and a few predefined pilot symbols are mapped onto the non
neighboring sub carriers with weighting coefficients of +1 and -1. With the aid of pilot symbols the frequency offset is exactly estimated by using Maximum Likelihood Estimation (MLE) and hence can be minimized. At demodulation stage the received signals are linearly combined along with their weighted
coefficients and pilot symbols, called as Pilot Aided Self Cancellation Method (PASCS). And also to realize the various wireless environments the simulations are carried out on Stanford University Interim (SUI) channels. The simulation results shows that by incorporating this method into WiMAX systems it performs better when the Line Of Sight (LOS) component is present in the transmission and also it improves the Bit Error Rate (BER) and Carrier to Interference Ratio (CIR). The CIR can be improved 20 dB. In this paper the effectiveness of PASCS scheme is compared with the Self Cancellation Method (SCM). It provides accurate estimation of frequency offset and when residual CFO is less significant the ICI can be diminished successfully.
OPTIMUM EFFICIENT MOBILITY MANAGEMENT SCHEME FOR IPv6 ijngnjournal
Mobile IPv6 (MIPv6) and Hierarchical Mobile IPv6 (HMIPv6) both are the mobility management solutions proposed by the Internet Engineering Task Force (IETF) to support IP Mobility. It’s been an important issue, that upon certain condition, out of MIPv6 and HMIPv6 which one is better. In this paper an Optimum Efficient Mobility Management (OEMM) scheme is described on the basis of analytical model which shows that OEMM Scheme is better in terms of performance and applicability of MIPv6 and HMIPv6. It shows that which one is better alternative between MIPv6 and HMIPv6 and if HMIPv6 is adopted it chooses the best Mobility Anchor Point (MAP). Finally it is illustrated that OEMM scheme is
better than that of MIPv6 and HMIPv6.
INVESTIGATION OF UTRA FDD DATA AND CONTROL CHANNELS IN THE PRESENCE OF NOISE ...ijngnjournal
In this paper, the main aim is to design and simulate UTRA FDD control channel in the presence of noise and wireless channel by using FDD library/Matlab box set that can be used to design and implement some
systems. Moreover, a test and verification of the library is achieved with different channel models such as Additive White Gaussian Noise (AWGN), fading and moving channel models. FDD library are employed to design whole transmitter and receiver. Then we had tested AWGN channel and some other channel models.
Also we illustrated what are control channels DCCH and the other one as understanding the whole system. Moreover, the standards have been covered as well as implemented the whole transmit and receive chain plus the generation of DPCH, DPCCH channel. we had tested the performance against the AWGN noise.
Then we have studied different channel models that are defined in the standard, used the few of them like the fading channel and moving channel. We have tried to compare the performance in terms of Monte Carlo simulation by producing the BER curves. We have also change some channel parameters like phase, number of multipaths and we have tried to see the performance of the model in the presence of actual channel model.
TOWARDS FUTURE 4G MOBILE NETWORKS: A REAL-WORLD IMS TESTBEDijngnjournal
In the near future, current mobile communication networks will converge towards an All-IP network in order to provide richer applications, stronger customer satisfaction, andfurther return on investment for the industry. However, such a convergence induces a strong level of complexity when handling interoperability between different operators and different handset vendors. In this context, the 3GPP consortium is working on the standardization of the convergence, and IMS is emerging as the internationally agreed upon standard that is multi-operator and multi-vendor. In this paper, we shed further light on the subtleties of IMS, and we delineate a blueprint for the implementation of a real-world
IMS testbed. An open source Presence Server is deployed as well. The operation of the IMS testbed and the Presence Server are checked to assess their conformance with 3GPP standards. A simple third party application is developed on top the IMS testbed to further assess its operation.
Harnessing WebAssembly for Real-time Stateless Streaming PipelinesChristina Lin
Traditionally, dealing with real-time data pipelines has involved significant overhead, even for straightforward tasks like data transformation or masking. However, in this talk, we’ll venture into the dynamic realm of WebAssembly (WASM) and discover how it can revolutionize the creation of stateless streaming pipelines within a Kafka (Redpanda) broker. These pipelines are adept at managing low-latency, high-data-volume scenarios.
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Using recycled concrete aggregates (RCA) for pavements is crucial to achieving sustainability. Implementing RCA for new pavement can minimize carbon footprint, conserve natural resources, reduce harmful emissions, and lower life cycle costs. Compared to natural aggregate (NA), RCA pavement has fewer comprehensive studies and sustainability assessments.
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as sensible heat due to lowering the flue gas exit temperature.
Additionally, harmful acids released from the stack can be
reduced in a condensing heat exchanger by acid condensation. reduced in a condensing heat exchanger by acid condensation.
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condenser depends on the knowledge and understanding of the
heat and mass transfer processes. A computer program for
numerical simulations of water (H2O) and sulfuric acid (H2SO4)
condensation in a flue gas condensing heat exchanger was
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mass and energy balances for the system were derived to
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HIGH PERFORMANCE ETHERNET PACKET PROCESSOR CORE FOR NEXT GENERATION NETWORKS
1. International Journal of Next-Generation Networks (IJNGN) Vol.4, No.3,September 2012
DOI : 10.5121/ijngn.2012.4307 89
HIGH PERFORMANCE ETHERNET PACKET
PROCESSOR CORE FOR NEXT GENERATION
NETWORKS
Raja Jitendra Nayaka1
, R. C. Biradar2
1
Research and Development, ITI Limited. Bangalore, INDIA
1
rjnayaka@yahoo.com
2
Department of Electronics and Communication Engineering
2
REVA Institute of Technology and Management, Bangalore, INDIA.
2
raj.biradar@revainstitution.org
ABSTRACT
As the demand for high speed Internet significantly increasing to meet the requirement of large data
transfers, real-time communication and High Definition ( HD) multimedia transfer over IP, the IP based
network products architecture must evolve and change. Application specific processors require high
performance, low power and high degree of programmability is the limitation in many general processor
based applications. This paper describes the design of Ethernet packet processor for system-on-chip (SoC)
which performs all core packet processing functions, including segmentation and reassembly, packetization
classification, route and queue management which will speedup switching/routing performance making it
more suitable for Next Generation Networks (NGN). Ethernet packet processor design can be configured
for use with multiple projects targeted to a FPGA device the system is designed to support 1/10/20/40/100
Gigabit links with a speed and performance advantage. VHDL has been used to implement and simulated
the required functions in FPGA.
KEYWORDS
Ethernet, SoC, FPGA, NGN, LAN Router and Switches, IP networks, 1/10/20/40/100 Gigabit.
1. INTRODUCTION
With the advancements in networking technology, most networks converge on Ethernet and IP as
the dominant transport technology and the ability to manage and process the IP packets at high
speed is a key to offering successful new services. There are different speeds 1/10/20/40/100
Gigabit with electrical and optical interfaces available in modern networks. Packet processors
intercept individual IP data packets and to process them using hardware solution which can be
easily enhanced to add new capabilities. In the next generation network high speed packet
processing is critical for low-latency applications such as multimedia and Voice over IP (VoIP).
Multicore packet processing building blocks are found in SoC based Ethernet Packet Processor to
meet the high performance. Next Generation Networks (NGN) need to be designed for high
performance requirements.
2. International Journal of Next-Generation Networks (IJNGN) Vol.4, No.3,September 2012
90
Data encapsulation process includes frame assembly before transmission and frame decoding
upon reception of a frame. While encoding the frame MAC layer adds a header and trailer to the
layer 3 payload. The use of frames in the transmission of bits as they are placed on the media and
in the grouping of bits at the receiving node. Frame encode process provides important delimiters
that are used to identify a group of bits that make up a frame. This process provides
synchronization between the transmitting and receiving nodes. Encapsulation process also
provides for Data Link layer addressing. Each Ethernet header added in the frame contains the
physical MAC address that enables a frame to be delivered to a destination node. Also function of
data encapsulation is error detection. Each Ethernet frame contains a trailer with a cyclic
redundancy check (CRC) of the frame contents. After reception of a frame, the receiving node
creates a CRC to compare to the one in the frame. If these two CRC calculations match and the
frame can be trusted to have been received without error.
The Ethernet packet processor handles following fields:
Preamble (PR): seven bytes. it is an alternating pattern of ones and zeros that tells receiving
stations that a frame is coming, and that provides a means to synchronize the frame-reception
portions of receiving physical layers with the incoming bit stream.
Start-of-frame delimiter (SFD): one byte. The SOF (start of frame) is an alternating pattern of
ones and zeros, ending with two consecutive 1-bits indicating that the next bit is the left-most bit
in the left-most byte of the destination address.
Destination address (DA): one bytes. The DA field identifies which station should receive the
frame.
Source addresses (SA): one bytes. The SA field identifies the sending station.
Length Type: it is two bytes. This field indicates either the number of MAC- data bytes that are
contained in the data field of the frame, or the frame type ID if the frame is assembled using an
optional format.
Data- it is a sequence of bytes from 46 to 1500 of any value. Minimum frame size is 64bytes.
Cyclic redundancy check (CRC) - 4 bytes. This sequence contains a 32-bit cyclic redundancy
check (CRC) value, which is created by the sending MAC and is recalculated by the receiving
MAC to check for damaged frames. The packet format is as shown in Figure 1 and decoding of
Ethernet Frame is shown in Figure 2.
Figure1.Ethernet Frame Format
3. International Journal of Next-Generation Networks (IJNGN) Vol.4, No.3,September 2012
91
Figure 2. Decoding Ethernet Frame
1.1 SYSTEM ON CHIP (SoC)
System on chip (SoC or SOC) refers to integrating many functional or peripherals of a embedded
system or other electronic system into a single integrated circuit . It may contain digital, analog,
mixed-signal, and often radio-frequency functions - all on a single chip substrate. A typical
application is in the area of embedded systems. The contrast with a microcontroller is one of
degree. Microcontrollers typically have multi functional blocks each block perform specific
function and are single-chip-systems; whereas the term SoC is typically used with more powerful
processors, capable of running software such as embedded OS like UCLinux, which need
external memory chips like DDR, FLASH and which are used with various external peripherals
increasing chip integration to reduce manufacturing costs, power and smaller systems.
Application specific processors are too complex to fit on just one chip built with a process
optimized for just one of the application tasks.
A SoC consists of both the hardware and the software that controls the microcontroller,
microprocessor or DSP cores, peripherals and interfaces. Most SoCs are developed from pre-
qualified hardware blocks for the hardware elements described above, together with the software
drivers that control their operation. The hardware blocks are put together using EDA tools; the
software modules are integrated using a software development environment. A key step in the
design flow is emulation: the hardware is mapped onto an emulation platform based on a field
programmable gate array (FPGA) that mimics the behavior of the SoC, and the software modules
are loaded into the memory of the emulation platform. SoC the emulation platform enables the
hardware and software of the SoC to be tested and debugged at close to its full operational speed.
After emulation the hardware of the SoC follows the place and route phase of the design of an
integrated circuit before it is fabricated.
In this paper Ethernet packet processor core is developed to use in SoC application for design of
high performance switches, router and other IP based products for next generation networks
(NGN). Ethernet packet processor code acts as hardware accelerator for processing packets in
SoC.
1.2 OUR CONTRIBUTIONS
In this paper, we provide the design and implementation aspects of Ethernet packet processors for
new generation IP Network technology, which is designed to address the performance and
flexibility problems of new generation IP products (1/10/20/40/100 Gigabit).we proposed to use
4. International Journal of Next-Generation Networks (IJNGN) Vol.4, No.3,September 2012
92
Ethernet packet processor for next generation internet protocol based products to meet high
performance requirements by providing hardware acceleration for frequently handled functions in
packet processing. The usage Ethernet packet processor (EPP) in design and development of
multiport switches and router is also discussed.
2. LITERARURE SURVEY
General purpose processors cannot provide wire speed performance for Packet processing and
analysis. Embedded ASIC hardware has extremely high cost and is difficult to implement and
requires many months of fabricate a chip for even small changes. The embedded processor can
handle only specified functionality with limited wire speed performance. Packet processing needs
balance between the architecture and network flow. Developing Real time packet Analysis which
can receive the packets processes the packets and forwards the packet with wire speed while
utilizing the maximum network bandwidth as well as to marinating security in the network is an
ideal application. Network traffic analysis includes capturing of data from network and inspecting
of data at each layer. The exponential growth of Internet traffic, network bandwidth and Internet
based applications rise problems of performance, flexibility in network traffic analysis. Flexibility
achieved through the programmable devices like General purpose processors and performance
can achieve through hardwired solutions like Field Programmable Gate Arrays. Implementation
comparison is shown in Figure 2.1 [23].
Network processors and field-programmable gate arrays (FPGAs) offer an interesting middle
ground. Network processors are CPUs tuned for performing networking tasks. While they are
sometimes faster for very specific tasks, they achieve that speed by optimizing for a very specific
task: network processing. It's very easy to push a network processor outside the design target by
adding new functionality. The network processor is often slower than a general-purpose processor
performing the same task. Network processors often have very low clock speeds.. Finally, the
costs for network processors is often on-par or even more expensive than a general-purpose CPU,
since volumes are smaller and the market more specialized. With General purpose processors we
can’t achieve wire speed performance; with FPGA technology Network processors are new
generation technology, which is designed to address the performance and flexibility problems.
Network processors, analyzes Lower level layers by hardware and higher level layer by software
with parallel and pipelined architecture. With multiple micro engines and with parallel and
pipelining programming architecture network processors makes network processing at wire speed
[18][19][20][21][22].
5. International Journal of Next-Generation Networks (IJNGN) Vol.4, No.3,September 2012
93
Figure 2.1 Implementation Comparison Courtesy [23]
The features of Ethernet packet Processors (EPP) are compared from the following perspectives.
Performance - by multiple parallel EPPs in SoC, EPPs are able to perform many applications at
wire speed.
Flexibility – having hardware IP (intellectual properties) core as a major part of the system
allows network equipment to easily adapt to changing standards and applications
Fast TTM – reuse of ready EPP core is much faster (and cheaper) than designing hardware and
software of equivalent functionality
Power – while EPPs are optimized for low power consumption and area, their power
consumption is important for cost reasons (e.g. implications on packaging).
Major goal of the designing EPP is that may include functionality, performance, power
consumption and manufacturing cost. Performance means the processing speed of the product,
which may be a combination of soft deadlines such as approximate time to perform a user-level
function and hard deadlines by which a particular operation must be completed. Since EPP uses
parallel blocks, the single clock is used for these blocks to perform individual requirements; the
power consumption is brought down. And manufacturing cost primarily defines the cost of the
hardware components.
Performance and flexibility. Traditional network processing mainly focuses on forwarding
packet at high speed in order to eliminate the network bottlenecks. Network devices are expected
to perform at high speed with low latency. However, as the Internet Protocol keeps maturing,
newer protocols have been emerging and will emerge in the future. Such newer protocols include
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IPv6, security, signaling, and various network managements, etc. Ethernet packet processors are
also expected to flexibly support these newer protocols and applications with high performance.
3. PROPOSED ARCHITECTURE AND DESIGN METHODOLOGY
Those general purpose processors based architecture suffers from very low performance that
hinder them from being suitable for many applications such as L2/L3 switches, routers and
Gigabit routers. Because of architectural constraints and number of clocks requirement for
executing instructions to perform functions application specific processors are not suitable for
high performance and low power requirements, however Ethernet packet processor allow much
faster packet processing capability by using multi functional parallel processing blocks. Each
individual blocks in the Ethernet packet processor receives data at MII, RMII, GMII etc interface
parallel data and perform specific functions like extraction and encapsulation of SFD, source or
destination MAC ID,L2,L3, CRC calculation and IFG.
The potential solution is to make use of the Field Programmable Gate Arrays (FPGAs), have
introduced a great deal of speed and flexibility and performance into machine fast controls and
operations. Ethernet is a popular protocol choice in FPGAs because of its flexibility, reliability,
and performance they are extensively used to implement highly specialized tasks where
simplicity, low production cost, and reliability are big assets. Even if simple and reliable, these
systems need means for communications.
Figure 3. Ethernet Packet Processor
An outline of the proposed architecture design is shown in Figure 3. Main components are
Ethernet packet Processor, 1/10/20/40/100 Gigabit interface Connector. Ethernet Packet
Processor consists of six VHDL Modules. The core functionality is implemented in the Aggregate
module, which has been custom-designed using VHDL. Such as detection of SFD, source MAC,
destination MAC, payload length and CRC detection/calculation. A clean separation between
these module and rest of the design allows for flexibility and portability, benefiting from well
defined independent interfaces. Networking cores provides fertile ground for designing highly
modular and re-usable components. Packet processing in FPGA is done by a chain of dedicated
pipelined blocks. We implemented programmable synchronous pipeline arrays of individual
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block for high performance. The multi functional blocks integrated into single chip is called
System on Chip (SoC).
The Ethernet Packet Processor analyzes the receiving frame. The packet is received and decoded
to all individual sub entity of the packet. It identifies the type of Ethernet encapsulation, type of
protocol, and extracts the fields in the packet needed by the Address look-up. The Packet
processor performs start of frame preamble (SFD), inter frame gap (IFG) detection, and Packet
length count, source. Destination MAC address and Layer2/Layer3/Layer4 parsing to extract
information from the headers of these three layers. Therefore, protocols of these three layers have
to be considered. The CRC calculation is done to check integrity of transmitted and received
frame. The identification of SFD and calculation/detection of CRC is found to be time and
memory consuming task in all IP based products. In this design we proposed hardware
acceleration of these tasks to offload processor tasks. Similarly source and destination MAC
address, IP address extraction and Frame length count is important tasks in switching and routing,
EPP provides pipelined blocks to meet these task to improve performance of next generation IP
products.
Most of the modern communication protocols use some error detection algorithms. Cyclic
Redundancy Check, or CRC, is the most popular one among these. CRC properties are defined by
the generator polynomial length and coefficients. The protocol specification usually defines CRC
in hex or polynomial notation. Cyclic redundancy check has major role in deciding performance
of system, which is carried repeatedly whenever frame is transmitted and received. The Cyclic
Redundancy Check can be used as a checksum to detect the accidental alteration of data during
transmission or storage. It is used in Ethernet packets to verify the content and detect errors.
CRC-32 block is implemented to meet high performance requirement. It is most optimized CRC-
32 block in Ethernet packet processor, the core accepts data packets with packet start and stop
aligned to any octet boundary. This functional block of CRC-32 generation and checking at high
speed uses an efficient pipelined CRC calculation algorithm. Cyclic redundancy check algorithm
is derived from the mathematics of polynomial division modulo two, as result the code seen in
practice deviates confusingly from 'pure' division and the register may shift left or right. Another
CRC that is other than CRC-8 or CRC-16 is the ubiquitous 32-bit CRC-32, which is used in
Ethernet. The CRC-32 polynomial is x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7
+ x5 + x4 +x2 + x + 1 and its LFSR implementation is shown in Figure 3a.
Figure 3a. Procedure for CRC-32
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3.1 PROOF OF CONCEPT AND APPLICATIONS
EPP play role of hardware acceleration in design of new generation IP products for achieving
high performance. The two simple examples of usage of EPP in design of switches and routers
are discussed.
3.1.1 LAN Switch Design Using Ethernet Packet Processor
Ethernet switch connects multiple Ethernet LAN ports. Each port on the switch can be connected
to a different LAN port; this topology forms a larger Ethernet network. Ethernet switch is used to
interconnect a number of Ethernet local area networks (LANs) to form a large Ethernet network
as shown in Figure4. The switch stores the media access controller (MAC) address in buffer
which is extracted from frames received through each port to identify each network segment.
MAC address are used to switch forward frames from the source port to the destination sport
instead of forwarding the frame to all the connected ports, hence consequently reducing network
traffic. If packet has CRC error, packets are discarded. Otherwise, the switch looks up the MAC
address and sends the packet on to the destination node. Many switches combine the two methods
by using cut-through until a certain error level is reached, then changing over to store and
forward. Few switches are strictly cut-through because this provides no error correction [2] [3]
[4].
Figure4: LAN network using Ethernet Switch.
Since processor based switch design is busy in collecting information required for switching and
switching between port lead to latency. Application specific solutions for multi-port Ethernet
switches are widely available from different vendors and can be used to meet the switching
requirements of a number of applications. However these do not provide a good solution for
applications that require high performance features and such as a configuration of an odd number
of ports or a configuration of ports of varying speeds. Multiple latencies resulting from this
scheme could improve the overall performance when combined with Ethernet Packet Processor in
SoC is shown Figure 4a.
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Figure 4a: High capacity LAN Switch Architecture.
3.1.2 Router Design Using Ethernet Packet Processor
The present networks routers have traditionally been implemented purely in software using ASIC
processors. Because of the software implementation, the performance of a router was limited by
the performance of the ASIC processor executing the protocol code. To achieve wire-speed
routing, high-performance processors together with hardware logic were required. This translated
into higher cost and area
Next Generation IP Routers require multi gigabit (1/10/20/40/100/1000G) networking
technologies where IP routers will be used to interconnect backbone networks. Routers also to act
as points of attachments to high performance WAN links [1]. New generation network routers
require powerful architectures to meet high performance bandwidth requirements.. Therefore, the
design of high speed IP routers has been a major area of research. New generation optical
networking technologies are pushing link rates in high speed IP routers beyond 10G and 40 Gbps.
Such high rates demand that packet forwarding in IP routers must be performed in hardware. The
FPGA based cores are reconfigured to take into account changes in the bandwidth demands and
routing characteristics [15]. While the FPGA is being reconfigured, all traffic is routed by the
hardware logic. When reconfiguration is finished, selected virtual networks are shifted back to the
hardware based on their performance requirements.
Next Generation IP routers require multi gigabit (1/10/20/40/100Gigabit) networking
technologies .The Packets are received at router input and router will open the packet, decode the
Ethernet frame, finds the ultimate destination address and encode the packet, giving it a new IP
header that will send it to next hop. The router checks IP address at the Network layer, source and
destination addresses to determine the path for the packet transportation over the network. Router
carries layer 3 networking activity.
The evolution of IP router designs and highlights the major performance issues affecting IP
routers. The need to build fast IP routers is being studied in a variety of ways. Our literature
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survey summarizes that various router blocks and their mechanism needed for improving high
speed performance operation and architectural constraints imposed by the various router design
alternatives of routers in present networks. Avoiding centralized processor route lookups, and
administration, is the requirements of new generation router design, router hardware can be made
more reliable by adding Ethernet packet processor could be one method for fast packet
processing. One of proposed router architecture using Ethernet packet processor is shown in
figure5 for various LAN and WAN interfaces.
Figure 5: High Speed high performance Router Design
4. CONCLUSIONS
A novel design methodology to design a internet protocol specific packet processor has been
introduced to have hardware acceleration for process and pass packets at high speed
1/10/20/40/100 Gigabit. We have designed an interface that directly translates the way packets
need to be processed into a simple clean pipeline that has enough flexibility to allow for
designing some powerful extensions to a basic switches and routers. Using this methodology, a
very compact domain specific SoC can be designed using Ethernet packet processing core while
maintaining the high speed requirements of Ethernet/IP switches and router. This Method finds
wide application in design of Ethernet based products including high performance high capacity
L2/L3 switches and router at 1/10/40/100 Gigabit is possible with this method.
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Authors
Raja Jitendra Nayaka, Working as Senior Engineer at R&D, ITI Ltd, Govt Of India, He
has over 18Yrs experience in design and development of telecom products, He has vast
experience in Switching, Transmission, Internet, SDH, and optical communication, His field
of interest is telecom and FPGA based designs.
Dr. R. C. Biradar is working as Professor in ECE Department Reva Institute of Technology
and Management, Bangalore, India. He obtained his Ph. D from VTU Belgaum, India. He
has many publications in reputed national/international journals and conferences. Some of
the journals where his research articles published are Elsevier, IET and Springer
publications having very good impact factors. His research interests include multicast
routing in mobile ad hoc networks, wireless Internet, group communication in MANETs,
software agent technology, network security, multimedia communication, VLSI design and
FPGA, etc. He is a reviewer of various reputed journals and conferences and chaired many
conferences. He is a member IETE (MIETE) India, member IE (MIE) India, member ISTE (MISTE) India
and member of IEEE (USA) and member of IACSIT. He has been listed in Marqui’s Who’s Who in the
World (2012 Edition), USA and Top 100 Engineers by IBC, UK.