IDT DDR4 RCD register and DB data buffer enable RDIMM and LRDIMM to faster speeds and deeper memories. This video helps you understand the DDR4 feature enhancements of IDT's DDR4 RCD and DB compared to earlier DDR3 technology. An introduction into some available LeCroy testing and debug tools completes the video. Presented by Douglas Malech, Product Marketing Manager at IDT and Mike Micheletti, Product Manager at Teledyne LeCroy. To learn more about IDT's leading portfolio of memory interface products, visit www.idt.com/go/MIP.

1. Understanding and Testing DDR4
R-DIMM and LR-DIMM Technology
Webinar - Recorded June 12, 2013
Presented by
Douglas Malech, Product Marketing Manager at IDT
Mike Micheletti, Product Manager at Teledyne LeCroy
©2013 Integrated Device Technology, Inc.

2. IDT Products
World’s First Complete DDR4 Chipset
for Server Memory Modules
www.IDT.com
PAGE 2
©2013 Integrated Device Technology, Inc.

3. IDT agenda
●DDR4
RDIMM – LRDIMM
●Comparing
●Signal
Modules DDR4 – DDR3
Paths
DD
www.IDT.com
R
D
4R
IM
it
Mw
h ID
t er
gis
e
Tr
PAGE 3
an
r
the
d
ma
ns
l se
or
©2013 Integrated Device Technology, Inc.

4. DDR4 RDIMM and LRDIMM Comparison
DDR4 LRDIMM
DDR4 RDIMM
DB
DB
DB
DB
DB
DB
DB
DB
DB
1-4 DRAM loads
1 DB load CMD/ADD/CTRL
CMD/ADD/CTRL
DDR4 RDIMM
DDR4 LRDIMM
DRAM CMD/ADD/CTRL signals are buffered
by RCD
DRAM CMD/ADD/CTRL and DB signals are
buffered by RCD
(DB CTRL signals are disabled)
DRAM DQ/DQS loads for all ranks are
connected to the channel bus (1-4)
www.IDT.com
(DB CTRL signals are enabled)
Only DDR4DB MDQ/MDQS loads are
connected to the channel bus (1)
PAGE 4
©2013 Integrated Device Technology, Inc.

5. DDR4 vs DDR3 DIMM Comparison
DDR4 LRDIMM
DDR4 RDIMM
DB
DB
DB
DB
DB
DB
DDR3 LRDIMM Module
DB
DB
DDR3 RDIMM
DDR3 LRDIMM
DB
DDR4
DDR3
Scalable: RDIMM (RCD)
LRDIMM (RCD+9DB)
Scalable: RDIMM (RCD)
LRDIMM (MB)
Up to 3200 MT/s
Up to 2133 MT/s
1TB possible (32R, 16Gb)
64GB (8R, 4Gb)
4 package, 8 logical (3DS 8H)
All rank aware
8 package (QDP)
Not all rank aware
Parity:
RDIMM (RCD + 36DRAM)
LRDIMM (RCD + 36DRAM + 9DB)
Parity:
RDIMM (RCD)
LRDIMM (MB)
Debug:
RDIMM (RCW read/write)
LRDIMM (RCW/BCW read/write)
Debug:
RDIMM (RCW write-only)
LRDIMM (MB read only through SMBus)
Sig:Gnd:
1:1 (better)
Sig:Gnd:
2:1
RAS:
Tapered for lower insertion force
RAS:
Not tapered
www.IDT.com
PAGE 5
©2013 Integrated Device Technology, Inc.

6. LRDIMM Data Signal Flow
DDR4 LRDIMM
DDR3 LRDIMM Module
DDR3 LRDIMM
backside bus
DB
DB
DB
DB
DB
DB
DB
DB
fr o n t s id
DB
DDR4 LRDIMM
DDR3 LRDIMM
DQ/DQS better routing
(0.2” trace variance)
Host controlled training
DQ/DQS large trace variability
(2”-6” trace variance)
Autonomous backside training
Standardized training
e b us
Vendor Specific training
www.IDT.com
PAGE 6
©2013 Integrated Device Technology, Inc.

7. DDR4 LRDIMM CMD/ADD/CTRL Signal Flow
SIDE A
SIDE B
DB
DB
DB
DB
DB
DB
BCOM BUS TO DB FROM RCD
DQ/DQS
BUS
DB
DB
DB
CMD/ADD/CTRL TO RCD FROM Host
(Parity)
ERROR_OUT
I2C SERIAL COMMUNICATION BUS
RCD RCW
DB BCW
DRAM MRS
Host  RCD (Write)
RCD  DRAM  Host (Read)
I2C  RCD (Write/Read)
N/A
Host  RCD  DB (Write)
DB  Host (Read)
I2C  RCD  DB (Write)
Broadcast
PBA (Host only)
Host  RCD  DRAM (MRS Write)
DRAM  Host (MPR Read)
Even Parity option
Even Parity option
Even Parity option
www.IDT.com
PAGE 7
Broadcast
PDA (Host only)
©2013 Integrated Device Technology, Inc.

8. RCW & BCW Communication Protocol
● MRS Command (Direct Method)
● Mode Register Set
● MRS0-6: DRAM mapped
● MRS7: RCW and DB mapped
● Address comes from subset of Address Bus
● Data comes from subset of Address Bus
● RC06 Commands (Indirect
● Control Word Read (CMD 4)
● Control Word Write (CMD 5)
MRS
MRS(0-6)
Method)
A12=0
● I2C Interface
● Write/Read access to all control words in RCD
MRS
RCW
RC00-RC0F
RCW
RC1x-RCFx
BCW
BC00-BC0F
BCW
BC1x-BCFx
www.IDT.com
ACT_n
A16/
RAS_
n
A15/
CAS_n
MRS(7)
Side A
Rank 0
A14/
WE_
n
BG1
side A/B
RCD
Access
DRAM
Access
BG0,BA1:BA
0
A12=1
DB
Access
A12
RCW/BCW
A11:8
1
0
0
0
0
7
0
0
1
0
0
0
0
7
0
RCW
ADDR
1
0
0
0
0
7
1
0
1
0
0
0
0
7
1
PAGE 8
A7:4
A3:0
RCW
ADDR
DATA
DATA
BCW
ADDR
DATA
BCW
DATA
ADDR
©2013 Integrated Device Technology, Inc.

9. Transcript
●
Doug: First I'm going to compare DDR4 RDIMM with DDR4 LRDIMM. On the RDIMM, all commands, address and control are buffered by the register. Here shown as the device in the middle
of the RDIMM with the acronym RCD which stands for register clock driver. That's the acronym used by the industry. However as you can see, the data outputs from the DRAM are not
buffered on the RDIMM. Therefore, that can be from one to four DRAM loads presented at the RDIMM connector. This picture shows the front side of the RDIMM, there are just as many
DRAMs on the backside. So you can imagine four DRAMs vertically placed where I'm showing one to four DRAM loads. These additional loads degrade signal integrity. Off to the right, on the
LRDIMM, command address and control buffering are similarly buffered by the register like on the RDIMM. However the DRAM outputs are also buffered by the data buffers. Here shown as
the chips with DB. This means that there will only be one load presented at the LRDIMM connector instead of four, like there were on the RDIMM. This leads to better signal integrity on the
data signals at the edge connector also referred to as DQ bits on the edge connector. However, having fewer loads at the connector is why LRDIMMs can be populated into your server with
less degradation in performance. Imagine three RDIMMs populating a server. That would mean up to three times four loads, or twelve DRAMs loads, connected onto the DQ path of the
motherboard. On the LRDIMM, that would mean only three times one or three loads on the DQ path. Fewer loads, LRDIMM.
●
This concept of RDIMM vs. LRDIMM is the same for DDR4 as it was in DDR3. However, we will see later that the DDR4 LRDIMM has a better architecture improving signal integrity.
●
So now I'm going to start showing the advantages of DDR4 versus DDR3 and here I'm going to be talking about both RDIMMs and LRDIMMs. As far as scalability goes, DDR4 RDIMMs and
DDR3 LRDIMMs use the same approach of having a central register device to buffer command and address for the memory module. However, in my opinion, DDR4 load reduced LRDIMMs
are more scalable than DDR4 RDIMMs.
●
And I'm showing it here by bringing in the red checks on the top, okay? As you can see in the pictures, the same central RCD is used in both DDR4 LRDIMMs and DDR4 RDIMMs. Therefore
all of the software used to control the DRAMs through the RCD on a DDR4 RDIMM can be reuse for controlling DRAMs on LRDIMMs. Hence the scalability. In addition to the register,
LRDIMMs also have nine data buffers, located between the lower DRAMs and the edge connector. The data buffers are controlled through the register and intercept the memory read, write
data. In a DDR3 LRDIMM a completely different buffering device called the memory buffer, is communicating with the host controller. Therefore, completely new software must be developed to
address the DRAMs on the DDR3 LRDIMM, because the register software cannot be reused. Item two; DDR4 modules will eventually reach speeds of 3200 mega transfers per second,
whereas DDR3 modules have topped out at 2133. Currently DDR4 is defined for operating speeds between 1600 and 2400 mega transfers per second, but there are plans to increase the
speed in future products. Additionally an incredible amount of DRIM memory is possible on these DDR4 modules. DDR4 addressing schemes are prepared to handle one terabyte of memory.
In DDR3, while 64 gigabytes modules might be realizable, I don't expect any higher densities from DDR3 module vendors.
●
I wanted to get back to comparing DDR3 and DDR4 again. In this case, I want to point out the DDR4 improvements in the signal flow for the DQ bits. These pictures show the DQ data paths.
You can see that the DDR4 DQ data path is very consistent from column to column of DRAMs. Shown here as vertical path connections. In DDR3, the trace variability from one DQ bit to the
next is between two inches to six inches in length. This means that data arriving simultaneously for two different DRAMs at the edge connector will have two very different flight times, at which
the data will arrive at the DRAMs. The modules calibrate out this variability in trace lengths but signal integrity and performance are compromised. Another benefit to DDR4 is that the training
algorithms to remove trace length variability in the command address and DQ paths are completely controlled by the host controller. And finally, because these training algorithms are done
completely by the host controller and the backside bus is not isolated, the host can be responsible for creating all of the training software and therefore the training software can be
standardized even if different chipsets are used from companies such as IDT.
●
I wanted to quickly show how the DDR4 commands flow from the host to the register data buffer and DRAM. For the RCD, the register command words are called RCW, or register command
word. You can see here that RCW writes are done directly from the host to the RCD. For reads, an RCW command is sent by the host to the RCD, to move the bits into a special multipurpose
register in the DRAM, and then the data that has been written into these special registers, called MPR registers, is read out of the DRAM onto the DQ bus. The data buffer works in a similar
way, for the data buffer, the buffer control words are called BCW. You can see here that writes are written from the host via the RCD to the data buffer. For reads, a command is sent by the
host to the data buffer to move the appropriate data buffer bits into a special multipurpose register located in the data buffer. Then the register's data is readout of the data buffer onto the DQ
bus. And finally, DRAM mode registers called MRS are written to, from the host, via the RCD to the DRAM. Reading from the MRS registers is also done through the same multipurpose
registers inside the DRAM that are used to readout the RCD register contents. In addition, I wanted to point out that you can individually write to the individual DRAM registers and data buffer
registers which is something that was not available in DDR3, which helps with training. And finally, there's even parody options available to make sure that the signals flowing into the RCD
from the host, as well as into the DRAMs and the data buffers, is valid data. And the difference here is that in DDR3, only the signals flowing from the host into the RCD had parody checking.
There was no parody checking for the DRAMs.
●
This slide is meant to intentionally show you how complicated it can become when writing to RCWs and BCWs and MRS’ etc. And I'm going to elect Mike and Lecroy, go into the specifics of
some of these protocols with their presentation, but I wanted to show them to you here. You can see the table below for details, but there are seven MRS registers, of which MRS zero through
MRS six, are used to write control information into the DRAMs. Writing to MRS7, rank zero, side A, with an A twelve address, bit twelve equals zero writes to the RCWs. Writing to MRS7, rank
zero, side A with, A twelve equal one writes to the data buffer controllers. You can write to them via the host controller. You can also write to them through a serial bus called I 2C. There are
different ways of writing, so for example, you may be booting the server and that would use MRS commands to communicate with all the chipsets on them. And simultaneously, you could
communicate with maybe some kind of debugging software and hardware through the I 2C interface at the same time.
www.IDT.com
PAGE 9
©2013 Integrated Device Technology, Inc.

10. Transcript
●
Doug: First I'm going to compare DDR4 RDIMM with DDR4 LRDIMM. On the RDIMM, all commands, address and control are buffered by the register. Here shown as the device in the middle
of the RDIMM with the acronym RCD which stands for register clock driver. That's the acronym used by the industry. However as you can see, the data outputs from the DRAM are not
buffered on the RDIMM. Therefore, that can be from one to four DRAM loads presented at the RDIMM connector. This picture shows the front side of the RDIMM, there are just as many
DRAMs on the backside. So you can imagine four DRAMs vertically placed where I'm showing one to four DRAM loads. These additional loads degrade signal integrity. Off to the right, on the
LRDIMM, command address and control buffering are similarly buffered by the register like on the RDIMM. However the DRAM outputs are also buffered by the data buffers. Here shown as
the chips with DB. This means that there will only be one load presented at the LRDIMM connector instead of four, like there were on the RDIMM. This leads to better signal integrity on the
data signals at the edge connector also referred to as DQ bits on the edge connector. However, having fewer loads at the connector is why LRDIMMs can be populated into your server with
less degradation in performance. Imagine three RDIMMs populating a server. That would mean up to three times four loads, or twelve DRAMs loads, connected onto the DQ path of the
motherboard. On the LRDIMM, that would mean only three times one or three loads on the DQ path. Fewer loads, LRDIMM.
●
This concept of RDIMM vs. LRDIMM is the same for DDR4 as it was in DDR3. However, we will see later that the DDR4 LRDIMM has a better architecture improving signal integrity.
●
So now I'm going to start showing the advantages of DDR4 versus DDR3 and here I'm going to be talking about both RDIMMs and LRDIMMs. As far as scalability goes, DDR4 RDIMMs and
DDR3 LRDIMMs use the same approach of having a central register device to buffer command and address for the memory module. However, in my opinion, DDR4 load reduced LRDIMMs
are more scalable than DDR4 RDIMMs.
●
And I'm showing it here by bringing in the red checks on the top, okay? As you can see in the pictures, the same central RCD is used in both DDR4 LRDIMMs and DDR4 RDIMMs. Therefore
all of the software used to control the DRAMs through the RCD on a DDR4 RDIMM can be reuse for controlling DRAMs on LRDIMMs. Hence the scalability. In addition to the register,
LRDIMMs also have nine data buffers, located between the lower DRAMs and the edge connector. The data buffers are controlled through the register and intercept the memory read, write
data. In a DDR3 LRDIMM a completely different buffering device called the memory buffer, is communicating with the host controller. Therefore, completely new software must be developed to
address the DRAMs on the DDR3 LRDIMM, because the register software cannot be reused. Item two; DDR4 modules will eventually reach speeds of 3200 mega transfers per second,
whereas DDR3 modules have topped out at 2133. Currently DDR4 is defined for operating speeds between 1600 and 2400 mega transfers per second, but there are plans to increase the
speed in future products. Additionally an incredible amount of DRIM memory is possible on these DDR4 modules. DDR4 addressing schemes are prepared to handle one terabyte of memory.
In DDR3, while 64 gigabytes modules might be realizable, I don't expect any higher densities from DDR3 module vendors.
●
I wanted to get back to comparing DDR3 and DDR4 again. In this case, I want to point out the DDR4 improvements in the signal flow for the DQ bits. These pictures show the DQ data paths.
You can see that the DDR4 DQ data path is very consistent from column to column of DRAMs. Shown here as vertical path connections. In DDR3, the trace variability from one DQ bit to the
next is between two inches to six inches in length. This means that data arriving simultaneously for two different DRAMs at the edge connector will have two very different flight times, at which
the data will arrive at the DRAMs. The modules calibrate out this variability in trace lengths but signal integrity and performance are compromised. Another benefit to DDR4 is that the training
algorithms to remove trace length variability in the command address and DQ paths are completely controlled by the host controller. And finally, because these training algorithms are done
completely by the host controller and the backside bus is not isolated, the host can be responsible for creating all of the training software and therefore the training software can be
standardized even if different chipsets are used from companies such as IDT.
●
I wanted to quickly show how the DDR4 commands flow from the host to the register data buffer and DRAM. For the RCD, the register command words are called RCW, or register command
word. You can see here that RCW writes are done directly from the host to the RCD. For reads, an RCW command is sent by the host to the RCD, to move the bits into a special multipurpose
register in the DRAM, and then the data that has been written into these special registers, called MPR registers, is read out of the DRAM onto the DQ bus. The data buffer works in a similar
way, for the data buffer, the buffer control words are called BCW. You can see here that writes are written from the host via the RCD to the data buffer. For reads, a command is sent by the
host to the data buffer to move the appropriate data buffer bits into a special multipurpose register located in the data buffer. Then the register's data is readout of the data buffer onto the DQ
bus. And finally, DRAM mode registers called MRS are written to, from the host, via the RCD to the DRAM. Reading from the MRS registers is also done through the same multipurpose
registers inside the DRAM that are used to readout the RCD register contents. In addition, I wanted to point out that you can individually write to the individual DRAM registers and data buffer
registers which is something that was not available in DDR3, which helps with training. And finally, there's even parody options available to make sure that the signals flowing into the RCD
from the host, as well as into the DRAMs and the data buffers, is valid data. And the difference here is that in DDR3, only the signals flowing from the host into the RCD had parody checking.
There was no parody checking for the DRAMs.
●
This slide is meant to intentionally show you how complicated it can become when writing to RCWs and BCWs and MRS’ etc. And I'm going to elect Mike and Lecroy, go into the specifics of
some of these protocols with their presentation, but I wanted to show them to you here. You can see the table below for details, but there are seven MRS registers, of which MRS zero through
MRS six, are used to write control information into the DRAMs. Writing to MRS7, rank zero, side A, with an A twelve address, bit twelve equals zero writes to the RCWs. Writing to MRS7, rank
zero, side A with, A twelve equal one writes to the data buffer controllers. You can write to them via the host controller. You can also write to them through a serial bus called I 2C. There are
different ways of writing, so for example, you may be booting the server and that would use MRS commands to communicate with all the chipsets on them. And simultaneously, you could
communicate with maybe some kind of debugging software and hardware through the I 2C interface at the same time.
www.IDT.com
PAGE 9
©2013 Integrated Device Technology, Inc.