Design for testability is important as chip complexity increases. It involves making chips easier to test by improving controllability and observability of internal signals. Controllability refers to the ability to set a node to a specific value, while observability refers to the ability to observe a node's value. Test generation algorithms aim to improve testability by making internal signals easier to control and observe.

1. Design for Testability

2.  Design for testability
 The ability to put a design into a known initial state, and then controlled and observe
internal signal values is called as testability.
 Two basic properties determine the testability of a node are controllability (The ability to
set node to a specific value) and observability (The ability to observe a node's value).
 As the number of transistors integrated into a single chip increases, the task of chip testing
to ensure correct functionality becomes increasing more difficult.
 In a production environment, many chips must be tested within a short time for timely
delivery to costumers. To overcome such difficult issues, design for testability has become
ever more critical.

3. Controllability and Observability
 The Controllability:
 The controllability of a circuit is a measure of the ease (or difficulty) with which the
controller (test engineer) can establish a specific signal value at each node by setting values
at the circuit input terminals

4.  The observability:
 The observability is the measure of the ease (or difficulty) with which one can determine
the signal value at any logic node in the circuit by controlling its primary input and
observing the primary output. Here the term primary refers to the I/O boundary of the
circuit under test.
 The degree of controllability and observability or the degree of testability of a circuit, can
be measured with respect to whether test vectors are generated deterministically or
randomly.

5.  There are deterministic procedures for test generation for combinational circuits, such as
D-algorithm which uses a reclusive search procedure advancing one gate at a time and
backtracking, if necessity, until all the faults are detected. The D-algorithm, requires a large
amount of computer time.
 To overcome such shortcomings, many improved algorithms have been introduced such as
 Path-Oriented Decision Making (PODEM)
 Fan-out-oriented test generation (FAN)
 Sequential circuit test generation is several orders of magnitude more difficult than these
algorithms.