Abstract The power consumption of a system is crucial parameter in modern VLSI circuits especially for low power applications. In this project, a low power Double Edge Triggered D-Flip Flop (DETFF) design is proposed in 65nm CMOS technology. The proposed DETFF is having less number of transistors than earlier designs. Simulations are carried out using HSPICE tool with different clock frequencies ranging from 400MHz to 2GHz and with different supply voltages ranging from 0.8V to 1.2V. In general, a power delay product (PDP)-based comparison is appropriate for low power portable systems. At nominal condition, the PDP of the proposed DETFF is improved by 65.48% and 44.85% over earlier designs DETFF1 and DETFF2 respectively. Simulation results show lowest power dissipation and least delay than existing designs, which claims that the proposed DETFF is suitable for low power and high speed applications. Keywords: CMOS, flip-flops, Double-edge triggered, power dissipation, delay and PDP.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Novel low power half subtractor using avl technique based on 0.18µm cmos tech...IJARIIT
Now a day’s arithmetic circuit plays an important role in designing of any VLSI system. Such as subtractor is one of
them. In this paper, half-subtractor is designed by using the adaptive voltage technique (AVL). By using the AVL technique,
half subtractor can reduce the power and delay element. We can reduce the value of total power dissipation by applying the
AVLG (adaptive voltage level at ground) technology in which the ground potential is raised and AVLS (adaptive voltage level
at supply) in which the supply potential is increased. The AVL technique shows the significant reduction in power
consumption and propagation delay. The circuit is simulated on cadence tool in 180 nanometre CMOS technology.
The neural network-based control system of direct current motor driverIJECEIAES
This article aims to propose an adaptive control system for the direct current motor driver based on the neural network. The control system consists of two neural networks: the first neural network is used to estimate the speed of the direct current motor and the second neural network is used as a controller. The plant in this research includes motor and the driver circuit so it is a complex model. It is difficult to determine the exact parameters of the plant so it is difficult to build the controller. To solve the above difficulties, the author proposes an adaptive control system based on the neural network to control the plant reach the high quality in the case of unknowing the parameters of the plant. The results are that the control quality of the system is very good, the response speed always follows the desired speed and the transition time is small. The simulation results of the neural network control system are shown and compared with that of a PID controller to demonstrate the advantages of the proposed method.
Abstract With the increasing interest in nano, micro and small satellites, need arises for miniaturization of satellite systems for small size, low weight, low cost designs and short development periods. For the operation and maintenance of a satellite in the designated orbit, a reliable commanding system is mandatory. This paper presents the work carried out in designing and developing a telecommand modem for use with student satellites. To transmit low bit rate command data, PSK/PM a two level modulation scheme is adopted. The architecture and the simulation and test results of the hardware realized on an FPGA are provided. Keywords –Phase Shift Keying, Phase Modulation, PSK/PM Modem, bit error rate, satellite commanding.
Addition is a fundamental arithmetic operation that is broadly used in many VLSI systems, such as application-specific digital signal processing (DSP) architectures and microprocessors. This addition module is also the core of other arithmetic operations such as subtraction, multiplication, division and address generation. The prime objective of this project is to design a full-adder having low-power consumption and low propagation delay which may result in the efficient implementation of modern digital systems. This model is referred as “hybrid” because of the combination of two different design logic styles namely CMOS logic and pass transistor logic. Performance parameters such as power, delay and hence energy were compared with the existing designs such as complementary CMOS logic full adder. In the existing hybrid systems, over 28 transistors were used. While the optimized hybrid full adder circuit reduces this count to 8 transistors, it still obtains better energy efficiency. Further the proper working of proposed full adder is verified by applying it in a Ripple carry Adder circuit.
The rapid growths of portable electronic devices are increased and they are designing with low power and high speed is critical. To design a three input XOR and XNOR gates using the systematic cell design methodology can be achieved by implementing transmission gate. By this type of designing the low power and high speed can achieved. This architecture is used to maintain summation results for after completing addition process. XOR/XNOR circuits are proposed with high driving capability, full-balanced full-swing outputs and low number transistors of basic structure, high performance and operating at low voltages. This simulation is carried out using TSMC 90nmCMOS technology in Tanner EDA Tool.
Power Optimized Datapath Units of Hybrid Embedded Core Architecture Using Clo...VLSICS Design
Minimizing power consumption is a primary consideration in hardware design of portable devices where
high performance and functionality is required with limited battery power. With the scaling of technology
and the need for high performance and more functionality, power dissipation becomes a major bottleneck
for microprocessor systems design. Clock power can be significant in high performance systems. Dynamic
power can contribute up to 50% of the total power dissipation. The main goal of this work is to implement
a prototype power optimized datapath unit and ALU of Hybrid Embedded Controller Architecture targeted
on to the FPGA chip and analyze the power consumption of the datapath, ALU etc. Dynamic power
management system which includes clock gating, qualified system latches are incorporated into this
design. The whole design is captured using VHDL make use of Xilinx tool. This paper gives complete
guidelines for authors submitting papers for the AIRCC Journals.
Design a Low Power High Speed Full Adder Using AVL Technique Based on CMOS Na...IOSR Journals
Abstract: Power and delay optimization is a very crucial issue in low voltage applications. In this paper, we present a design of Full Adder circuit using AVL techniques for low power operation. The approach for the design is based on XOR/XNOR & Transmission gate for single bit as hybrid design .By using this approach Full Adder is being designed using 12 transistors. We can reduce the value of total power dissipation by applying the AVLG (adaptive voltage level at ground) technology in which the ground potential is raised and AVLS (adaptive voltage level at supply) in which supply potential is increased. The main aim of the design is to investigate the power, Propagation Delay and Power delay Product for low voltage Full Adder for the proposed design style. The simulation results show that there is a significant reduction in power consumption for this proposed cell with the AVL technique. The circuit is designed using 65 nanometer CMOS technology and simulated using MicroWind and DSCH Ver. 3.1 Keywords: Full Adder, AVL Techniques, Low Power, VLSI, High Performance
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Novel low power half subtractor using avl technique based on 0.18µm cmos tech...IJARIIT
Now a day’s arithmetic circuit plays an important role in designing of any VLSI system. Such as subtractor is one of
them. In this paper, half-subtractor is designed by using the adaptive voltage technique (AVL). By using the AVL technique,
half subtractor can reduce the power and delay element. We can reduce the value of total power dissipation by applying the
AVLG (adaptive voltage level at ground) technology in which the ground potential is raised and AVLS (adaptive voltage level
at supply) in which the supply potential is increased. The AVL technique shows the significant reduction in power
consumption and propagation delay. The circuit is simulated on cadence tool in 180 nanometre CMOS technology.
The neural network-based control system of direct current motor driverIJECEIAES
This article aims to propose an adaptive control system for the direct current motor driver based on the neural network. The control system consists of two neural networks: the first neural network is used to estimate the speed of the direct current motor and the second neural network is used as a controller. The plant in this research includes motor and the driver circuit so it is a complex model. It is difficult to determine the exact parameters of the plant so it is difficult to build the controller. To solve the above difficulties, the author proposes an adaptive control system based on the neural network to control the plant reach the high quality in the case of unknowing the parameters of the plant. The results are that the control quality of the system is very good, the response speed always follows the desired speed and the transition time is small. The simulation results of the neural network control system are shown and compared with that of a PID controller to demonstrate the advantages of the proposed method.
Abstract With the increasing interest in nano, micro and small satellites, need arises for miniaturization of satellite systems for small size, low weight, low cost designs and short development periods. For the operation and maintenance of a satellite in the designated orbit, a reliable commanding system is mandatory. This paper presents the work carried out in designing and developing a telecommand modem for use with student satellites. To transmit low bit rate command data, PSK/PM a two level modulation scheme is adopted. The architecture and the simulation and test results of the hardware realized on an FPGA are provided. Keywords –Phase Shift Keying, Phase Modulation, PSK/PM Modem, bit error rate, satellite commanding.
Addition is a fundamental arithmetic operation that is broadly used in many VLSI systems, such as application-specific digital signal processing (DSP) architectures and microprocessors. This addition module is also the core of other arithmetic operations such as subtraction, multiplication, division and address generation. The prime objective of this project is to design a full-adder having low-power consumption and low propagation delay which may result in the efficient implementation of modern digital systems. This model is referred as “hybrid” because of the combination of two different design logic styles namely CMOS logic and pass transistor logic. Performance parameters such as power, delay and hence energy were compared with the existing designs such as complementary CMOS logic full adder. In the existing hybrid systems, over 28 transistors were used. While the optimized hybrid full adder circuit reduces this count to 8 transistors, it still obtains better energy efficiency. Further the proper working of proposed full adder is verified by applying it in a Ripple carry Adder circuit.
The rapid growths of portable electronic devices are increased and they are designing with low power and high speed is critical. To design a three input XOR and XNOR gates using the systematic cell design methodology can be achieved by implementing transmission gate. By this type of designing the low power and high speed can achieved. This architecture is used to maintain summation results for after completing addition process. XOR/XNOR circuits are proposed with high driving capability, full-balanced full-swing outputs and low number transistors of basic structure, high performance and operating at low voltages. This simulation is carried out using TSMC 90nmCMOS technology in Tanner EDA Tool.
Power Optimized Datapath Units of Hybrid Embedded Core Architecture Using Clo...VLSICS Design
Minimizing power consumption is a primary consideration in hardware design of portable devices where
high performance and functionality is required with limited battery power. With the scaling of technology
and the need for high performance and more functionality, power dissipation becomes a major bottleneck
for microprocessor systems design. Clock power can be significant in high performance systems. Dynamic
power can contribute up to 50% of the total power dissipation. The main goal of this work is to implement
a prototype power optimized datapath unit and ALU of Hybrid Embedded Controller Architecture targeted
on to the FPGA chip and analyze the power consumption of the datapath, ALU etc. Dynamic power
management system which includes clock gating, qualified system latches are incorporated into this
design. The whole design is captured using VHDL make use of Xilinx tool. This paper gives complete
guidelines for authors submitting papers for the AIRCC Journals.
Design a Low Power High Speed Full Adder Using AVL Technique Based on CMOS Na...IOSR Journals
Abstract: Power and delay optimization is a very crucial issue in low voltage applications. In this paper, we present a design of Full Adder circuit using AVL techniques for low power operation. The approach for the design is based on XOR/XNOR & Transmission gate for single bit as hybrid design .By using this approach Full Adder is being designed using 12 transistors. We can reduce the value of total power dissipation by applying the AVLG (adaptive voltage level at ground) technology in which the ground potential is raised and AVLS (adaptive voltage level at supply) in which supply potential is increased. The main aim of the design is to investigate the power, Propagation Delay and Power delay Product for low voltage Full Adder for the proposed design style. The simulation results show that there is a significant reduction in power consumption for this proposed cell with the AVL technique. The circuit is designed using 65 nanometer CMOS technology and simulated using MicroWind and DSCH Ver. 3.1 Keywords: Full Adder, AVL Techniques, Low Power, VLSI, High Performance
In this paper, DTC is applied for two-level inverter fed IM drives based on neuronal hysteresis comparators and The Direct Torque Control (DTC) is known to produce quick and robust response in AC drive system. However, during steady state, torque, flux and current ripple. An improvement of electric drive system can be obtained using a DTC method based on ANNs which reduces the torque and flux ripples, the estimated the rotor speed using the KUBOTA observer method based on measurements of electrical quantities of the motor. The validity of the proposed methods is confirmed by the simulation results.The THD (Total Harmonic Distortion) of stator current, torque ripple and stator flux ripple are determined and compared with conventional DTC control scheme using Matlab/Simulink environment.
DTC Scheme for a Four-Switch Inverter-Fed PMBLDC Motor Emulating the Six-Swit...IJRST Journal
The paper deals with the direct torque control (DTC) of brushless DC (BLDC) motor drives fed by four-switch three phase inverters (FSTPI) rather than six-switch inverters (SSTPI) in conventional drives. For any three phase inverter require six switches, but these switches are reduced to four. This reduction of power switches from six to four improves the reliability of the inverter, size of the inverter is reduced and cost of the inverter is also reduces. The FSTPI could be regarded as a reconfigured topology of the SSTPI in case of a switch/leg failure which represents a crucial reliability benefit for many applications especially in electric and hybrid propulsion systems. The DTC of FSTPI-fed BLDC motor drives is treated considering two strategies, such as: 1) DTC-1: a strategy inspired from the one intended to SSTPI-fed BLDC motor drives; 2) DTC-2: a strategy that considers a dedicated vector selection subtable in order to independently control the torques developed by the phases connected to the FSTPI legs during their simultaneous conduction. The operational principle of the four-switch BLDC motor drive and the developed control scheme are theoretically analyzed and the performance is demonstrated by simulation.
Arm based automatic control system of nano positioning stage for micromanufac...csandit
A microcontroller based control system to drive the Physik Instrumente (PI )
piezoelectric ultrasonic nano-positioning (PUN) stage for a micro-factory has been
proposed by the author. The tuning parameters of the PI Line Controller are chosen
such that the PUN stage shows optimum step response. The microcontroller i.e.
LPC2478R provides the user with the choices of operations on the 3.2” QVGA LCD
screen and the choice can be made by a 5-key joystick. The PUN stage moves in
different geometrical patterns as chosen by the user. The stage is placed in the
workspace of the Clark-MXRR,Inc. CPA-2101 femto-second laser. Different patterns
are made on the material in question. As compared to the previous works in this area,
the user is given the power for position control, real time tracking, and trajectory
planning of the actuator. The user interface has been made very easy to comprehend.
The repeatability of tasks, portability of the as- sembly, the reduction in the size of the
system , power consumption and the human involvement are the major achievements
after the inclusion of a microcontroller.
Abstract: The Major contributor to power dissipation using signal switching of high frequency and strong pipeline designs. Total power consumption using clock tree accounts and 20-40% of power is consumed in synchronous circuits. Therefore, by decreasing the clock-tree power, the chip power reduces. In this proposed system a circuit is implemented which is a frequency synthesizer for generating the clock tree. Then the gated latch technique is applied to this circuit for reducing the power consumption. The resulting output is the generation of the clock tree. The clock power can be controlled through gating. Primary goal is to reduce the power in the clock tree. Thus the clock tree synthesis is performed and gated latch technique is applied to the out coming clock signal from the clock tree. The gated latch is the concept of gating the control signal. The gated signal output plays the role of the enable in the latches. Thus whenever we need we can switch off the clock signal and we can use the clock signal for clock tree synthesis. These are all controlled by the control signal. The power consumed is 0.052.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Embedded fuzzy controller for water level control IJECEIAES
This article presents the design of a fuzzy controller embedded in a microcontroller aimed at implementing a low-cost, modular process control system. The fuzzy system's construction is based on a classical proportional and derivative controller, where inputs of error and its derivate depend on the difference between the desired setpoint and the actual level; the goal is to control the water level of coupled tanks. The process is oriented to control based on the knowledge that facilitates the adjustment of the output variable without complex mathematical modeling. In different response tests of the fuzzy controller, a maximum over-impulse greater than 8% or a steady-state error greater than 2.1% was not evidenced when varying the setpoint.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Efficient reconfigurable architecture of baseband demodulator in sdreSAT Journals
Abstract This paper presents the simulation architecture and performance analysis with the use of ZCD technic. A Zero-Crossing based All-Digital Baseband Demodulation architecture is proposed in this work. This architecture supports demodulation of all modulation schemes including MSK, PSK, FSK, and QAM. The proposed structure is very low area, low power, and low latency and can operate in real-time. Moreover it can switch, in run-time, between multiple modulation schemes like GMSK (GSM), QPSK (CDMA), GFSK (Bluetooth), 8-PSK (EDGE), Offset-QPSK (W-CDMA), etc. In addition, the phase resolution of the demodulator is scalable with performance. In addition, bit-wise amplitude quantization based quad-decomposition approach is utilized to demodulate higher order M-ary QAM modulations such as 16-QAM & 64-QAM, which is also a highly scalable architecture. This structure of demodulator provides energy-efficient and resource-efficient implementation of various wireless standards in physical layer of SDR. Keywords — Physical layer, Mobile and Wireless Communication, Software Defined radio (SDR), Zero Cross Detection (ZCD), Modulation Schemes, Architecture, high level synthesis, FPGA.
Fixed-time observer-based distributed secondary voltage and frequency control...IJECEIAES
This paper deals with the problem of voltage and frequency control of distributed generators (DGs) in AC islanded microgrids. The main motivation of this work is to obviate the shortcomings of conventional centralized and distributed control of microgrids by providing a better alternative control strategy with better control performance than state-of-the art approaches. A distributed secondary control protocol based on a novel fixed-time observer-based feedback control method is designed for fixed-time frequency and voltage reference tracking and disturbance rejection. Compared to the existing secondary microgrid controllers, the proposed control strategy ensures frequency and voltage reference tracking and disturbance rejection before the desired fixed-time despite the microgrid initial conditions, parameters uncertainties and the unknown disturbances. Also, the controllers design and tuning is simple, straightforward and model-free.i.e, the knowledge of the microgrid parameters, topology, loads or transmission lines impedance are not needed in the design procedure. The use of distributed control approach enhances the reliability of the system by making the control system geographically distributed along with the power sources, by using the neighboring DGs informations instead of the DG’s local informations only and by cooperatively rejecting external disturbances and maintaining the frequency and the voltage at their reference values at any point of the microgrid. The efficiency of the proposed approach is verified by comparing its performance in reference tracking and its robustness to load power variations to some of the works in literature that addressed distributed secondary voltage and frequency control.
A Novel Technique for Tuning PI-controller in Switched Reluctance Motor Drive...IJECEIAES
This paper presents, an optimal basic speed controller for switched reluctance motor (SRM) based on ant colony optimization (ACO) with the presence of good accuracies and performances. The control mechanism consists of proportional-integral (PI) speed controller in the outer loop and hysteresis current controller in the inner loop for the three phases, 6/4 switched reluctance motor. Because of nonlinear characteristics of a SRM, ACO algorithm is employed to tune coefficients of PI speed controller by minimizing the time domain objective function. Simulations of ACO based control of SRM are carried out using MATLAB /SIMULINK software. The behavior of the proposed ACO has been estimated with the classical Ziegler- Nichols (ZN) method in order to prove the proposed approach is able to improve the parameters of PI chosen by ZN method. Simulations results confirm the better behavior of the optimized PI controller based on ACO compared with optimized PI controller based on classical Ziegler-Nichols method.
Efficient speed governor for blower motoreSAT Journals
Abstract This paper presents an efficient speed governor for the blower motor used in the air conditioning of electric vehicles (EV). Performance optimization of blowers offers tremendous potential for energy saving and hence the running cost. Pulse width modulation (PWM) technique is one of the most economical and widely used techniques in the motor control applications. SG 3525 device is used to generate the required PWM signals for the regulation of the blower motor speed. The PWM signal with 0-100% duty ratio control governs the semiconductor switches such as MOSFETs in controlling the supply voltage to the motor. The proposed control scheme governs the speed by varying the reference voltage to the SG 3525 and also protects the motor from high current as the scheme monitors the current flow through the motor indirectly via gate control signal of the semiconductor switches. Keywords: Pulse width modulation (PWM), Blower, Electric Vehicle (EV), SG 3525, MOSFET, Duty ratio.
FPGA IMPLEMENTATION OF UNIVERSAL SHIFT REGISTER FOR ASYNCHRONOUS DATA SAMPLINGEditor IJMTER
Now a days power consumption plays a vital role in vlsi circuits. The growing market of
mobiles, battery-powered electronic devices demands the design of electronic circuits with low
power consumption.To design a low power circuit, energy efficiency from the clock element is an
important issue.There are different technique for the energy efficiency. One technique for efficiency
is the use of double edge-triggered flip-flops (DETFFs), since they can maintain the same throughput
as single edge-triggered flip-flops (SETFFs) while only using half of the clock frequency. Doubleedge triggered (DET) flip-flops are bistable flip-flop circuits in which data is latched at either edge of
the clock signal. Using such flip-flops permits the rate of data processing to be preserved while using
lower clock. Therefore, power consumption in DETFF based circuit may be reduced. The DETFF
designs provide the best performance not only in power but also in speed. Clock gating is another
well-accepted technique to reduce the dynamic power of idle modules or idle cycles, like the power
wasted by timing components during the time when the system is idle. Clock gating means disabling
the clock signal when the input data does not alter the stored data. However, incorporating clock
gating with DETFFs to further reduce dynamic power consumption introduces an asynchronous data
sampling (i.e., a change in output between clock edges). In this paper are discussing two different
methods to avoid asynchronous data sampling and implement this using universal shift register.
Design and Analysis of Sequential Circuit for Leakage Power Reduction using S...ijsrd.com
The rapid growth in semiconductor device industry has led to the development of high Performance potable systems with improve reliability. In such applications, it is extremely important to minimize current consumption due to the limited availability of battery Power. Consequently, power dissipation is becoming recognized as a top priority issue for VLSI circuit design. Leakage power makes up to 50% of the total power consumption in today's high performance microprocessors. Therefore leakage power reduction becomes the key to a low power design. Leakage power dissipation is the power dissipated by the circuit when it is in Sleep mode or standby mode. A significant portion of the total power consumption in high performance digital circuits in deep submicron regime is mainly due to leakage power. Leakage is the only Source. of power consumption in an idle circuit. Therefore it is important to reduce leakage power in portable system.
In this paper, DTC is applied for two-level inverter fed IM drives based on neuronal hysteresis comparators and The Direct Torque Control (DTC) is known to produce quick and robust response in AC drive system. However, during steady state, torque, flux and current ripple. An improvement of electric drive system can be obtained using a DTC method based on ANNs which reduces the torque and flux ripples, the estimated the rotor speed using the KUBOTA observer method based on measurements of electrical quantities of the motor. The validity of the proposed methods is confirmed by the simulation results.The THD (Total Harmonic Distortion) of stator current, torque ripple and stator flux ripple are determined and compared with conventional DTC control scheme using Matlab/Simulink environment.
DTC Scheme for a Four-Switch Inverter-Fed PMBLDC Motor Emulating the Six-Swit...IJRST Journal
The paper deals with the direct torque control (DTC) of brushless DC (BLDC) motor drives fed by four-switch three phase inverters (FSTPI) rather than six-switch inverters (SSTPI) in conventional drives. For any three phase inverter require six switches, but these switches are reduced to four. This reduction of power switches from six to four improves the reliability of the inverter, size of the inverter is reduced and cost of the inverter is also reduces. The FSTPI could be regarded as a reconfigured topology of the SSTPI in case of a switch/leg failure which represents a crucial reliability benefit for many applications especially in electric and hybrid propulsion systems. The DTC of FSTPI-fed BLDC motor drives is treated considering two strategies, such as: 1) DTC-1: a strategy inspired from the one intended to SSTPI-fed BLDC motor drives; 2) DTC-2: a strategy that considers a dedicated vector selection subtable in order to independently control the torques developed by the phases connected to the FSTPI legs during their simultaneous conduction. The operational principle of the four-switch BLDC motor drive and the developed control scheme are theoretically analyzed and the performance is demonstrated by simulation.
Arm based automatic control system of nano positioning stage for micromanufac...csandit
A microcontroller based control system to drive the Physik Instrumente (PI )
piezoelectric ultrasonic nano-positioning (PUN) stage for a micro-factory has been
proposed by the author. The tuning parameters of the PI Line Controller are chosen
such that the PUN stage shows optimum step response. The microcontroller i.e.
LPC2478R provides the user with the choices of operations on the 3.2” QVGA LCD
screen and the choice can be made by a 5-key joystick. The PUN stage moves in
different geometrical patterns as chosen by the user. The stage is placed in the
workspace of the Clark-MXRR,Inc. CPA-2101 femto-second laser. Different patterns
are made on the material in question. As compared to the previous works in this area,
the user is given the power for position control, real time tracking, and trajectory
planning of the actuator. The user interface has been made very easy to comprehend.
The repeatability of tasks, portability of the as- sembly, the reduction in the size of the
system , power consumption and the human involvement are the major achievements
after the inclusion of a microcontroller.
Abstract: The Major contributor to power dissipation using signal switching of high frequency and strong pipeline designs. Total power consumption using clock tree accounts and 20-40% of power is consumed in synchronous circuits. Therefore, by decreasing the clock-tree power, the chip power reduces. In this proposed system a circuit is implemented which is a frequency synthesizer for generating the clock tree. Then the gated latch technique is applied to this circuit for reducing the power consumption. The resulting output is the generation of the clock tree. The clock power can be controlled through gating. Primary goal is to reduce the power in the clock tree. Thus the clock tree synthesis is performed and gated latch technique is applied to the out coming clock signal from the clock tree. The gated latch is the concept of gating the control signal. The gated signal output plays the role of the enable in the latches. Thus whenever we need we can switch off the clock signal and we can use the clock signal for clock tree synthesis. These are all controlled by the control signal. The power consumed is 0.052.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Embedded fuzzy controller for water level control IJECEIAES
This article presents the design of a fuzzy controller embedded in a microcontroller aimed at implementing a low-cost, modular process control system. The fuzzy system's construction is based on a classical proportional and derivative controller, where inputs of error and its derivate depend on the difference between the desired setpoint and the actual level; the goal is to control the water level of coupled tanks. The process is oriented to control based on the knowledge that facilitates the adjustment of the output variable without complex mathematical modeling. In different response tests of the fuzzy controller, a maximum over-impulse greater than 8% or a steady-state error greater than 2.1% was not evidenced when varying the setpoint.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Efficient reconfigurable architecture of baseband demodulator in sdreSAT Journals
Abstract This paper presents the simulation architecture and performance analysis with the use of ZCD technic. A Zero-Crossing based All-Digital Baseband Demodulation architecture is proposed in this work. This architecture supports demodulation of all modulation schemes including MSK, PSK, FSK, and QAM. The proposed structure is very low area, low power, and low latency and can operate in real-time. Moreover it can switch, in run-time, between multiple modulation schemes like GMSK (GSM), QPSK (CDMA), GFSK (Bluetooth), 8-PSK (EDGE), Offset-QPSK (W-CDMA), etc. In addition, the phase resolution of the demodulator is scalable with performance. In addition, bit-wise amplitude quantization based quad-decomposition approach is utilized to demodulate higher order M-ary QAM modulations such as 16-QAM & 64-QAM, which is also a highly scalable architecture. This structure of demodulator provides energy-efficient and resource-efficient implementation of various wireless standards in physical layer of SDR. Keywords — Physical layer, Mobile and Wireless Communication, Software Defined radio (SDR), Zero Cross Detection (ZCD), Modulation Schemes, Architecture, high level synthesis, FPGA.
Fixed-time observer-based distributed secondary voltage and frequency control...IJECEIAES
This paper deals with the problem of voltage and frequency control of distributed generators (DGs) in AC islanded microgrids. The main motivation of this work is to obviate the shortcomings of conventional centralized and distributed control of microgrids by providing a better alternative control strategy with better control performance than state-of-the art approaches. A distributed secondary control protocol based on a novel fixed-time observer-based feedback control method is designed for fixed-time frequency and voltage reference tracking and disturbance rejection. Compared to the existing secondary microgrid controllers, the proposed control strategy ensures frequency and voltage reference tracking and disturbance rejection before the desired fixed-time despite the microgrid initial conditions, parameters uncertainties and the unknown disturbances. Also, the controllers design and tuning is simple, straightforward and model-free.i.e, the knowledge of the microgrid parameters, topology, loads or transmission lines impedance are not needed in the design procedure. The use of distributed control approach enhances the reliability of the system by making the control system geographically distributed along with the power sources, by using the neighboring DGs informations instead of the DG’s local informations only and by cooperatively rejecting external disturbances and maintaining the frequency and the voltage at their reference values at any point of the microgrid. The efficiency of the proposed approach is verified by comparing its performance in reference tracking and its robustness to load power variations to some of the works in literature that addressed distributed secondary voltage and frequency control.
A Novel Technique for Tuning PI-controller in Switched Reluctance Motor Drive...IJECEIAES
This paper presents, an optimal basic speed controller for switched reluctance motor (SRM) based on ant colony optimization (ACO) with the presence of good accuracies and performances. The control mechanism consists of proportional-integral (PI) speed controller in the outer loop and hysteresis current controller in the inner loop for the three phases, 6/4 switched reluctance motor. Because of nonlinear characteristics of a SRM, ACO algorithm is employed to tune coefficients of PI speed controller by minimizing the time domain objective function. Simulations of ACO based control of SRM are carried out using MATLAB /SIMULINK software. The behavior of the proposed ACO has been estimated with the classical Ziegler- Nichols (ZN) method in order to prove the proposed approach is able to improve the parameters of PI chosen by ZN method. Simulations results confirm the better behavior of the optimized PI controller based on ACO compared with optimized PI controller based on classical Ziegler-Nichols method.
Efficient speed governor for blower motoreSAT Journals
Abstract This paper presents an efficient speed governor for the blower motor used in the air conditioning of electric vehicles (EV). Performance optimization of blowers offers tremendous potential for energy saving and hence the running cost. Pulse width modulation (PWM) technique is one of the most economical and widely used techniques in the motor control applications. SG 3525 device is used to generate the required PWM signals for the regulation of the blower motor speed. The PWM signal with 0-100% duty ratio control governs the semiconductor switches such as MOSFETs in controlling the supply voltage to the motor. The proposed control scheme governs the speed by varying the reference voltage to the SG 3525 and also protects the motor from high current as the scheme monitors the current flow through the motor indirectly via gate control signal of the semiconductor switches. Keywords: Pulse width modulation (PWM), Blower, Electric Vehicle (EV), SG 3525, MOSFET, Duty ratio.
FPGA IMPLEMENTATION OF UNIVERSAL SHIFT REGISTER FOR ASYNCHRONOUS DATA SAMPLINGEditor IJMTER
Now a days power consumption plays a vital role in vlsi circuits. The growing market of
mobiles, battery-powered electronic devices demands the design of electronic circuits with low
power consumption.To design a low power circuit, energy efficiency from the clock element is an
important issue.There are different technique for the energy efficiency. One technique for efficiency
is the use of double edge-triggered flip-flops (DETFFs), since they can maintain the same throughput
as single edge-triggered flip-flops (SETFFs) while only using half of the clock frequency. Doubleedge triggered (DET) flip-flops are bistable flip-flop circuits in which data is latched at either edge of
the clock signal. Using such flip-flops permits the rate of data processing to be preserved while using
lower clock. Therefore, power consumption in DETFF based circuit may be reduced. The DETFF
designs provide the best performance not only in power but also in speed. Clock gating is another
well-accepted technique to reduce the dynamic power of idle modules or idle cycles, like the power
wasted by timing components during the time when the system is idle. Clock gating means disabling
the clock signal when the input data does not alter the stored data. However, incorporating clock
gating with DETFFs to further reduce dynamic power consumption introduces an asynchronous data
sampling (i.e., a change in output between clock edges). In this paper are discussing two different
methods to avoid asynchronous data sampling and implement this using universal shift register.
Design and Analysis of Sequential Circuit for Leakage Power Reduction using S...ijsrd.com
The rapid growth in semiconductor device industry has led to the development of high Performance potable systems with improve reliability. In such applications, it is extremely important to minimize current consumption due to the limited availability of battery Power. Consequently, power dissipation is becoming recognized as a top priority issue for VLSI circuit design. Leakage power makes up to 50% of the total power consumption in today's high performance microprocessors. Therefore leakage power reduction becomes the key to a low power design. Leakage power dissipation is the power dissipated by the circuit when it is in Sleep mode or standby mode. A significant portion of the total power consumption in high performance digital circuits in deep submicron regime is mainly due to leakage power. Leakage is the only Source. of power consumption in an idle circuit. Therefore it is important to reduce leakage power in portable system.
LEAKAGE POWER REDUCTION AND ANALYSIS OF CMOS SEQUENTIAL CIRCUITSVLSICS Design
A significant portion of the total power consumption in high performance digital circuits in deep submicron regime is mainly due to leakage power. Leakage is the only source of power consumption in an idle circuit. Therefore it is important to reduce leakage power in portable systems. In this paper two techniques such as transistor stacking and self-adjustable voltage level circuit for reducing leakage power in sequential circuits are proposed. This work analyses the power and delay of three different types of D flip-flops using pass transistors, transmission gates and gate diffusion input gates. . All the circuits are simulated with and without the application of leakage reduction techniques. Simulation results show that the proposed pass transistor based D flip-flop using self-adjustable voltage level circuit has the least leakage power dissipation of 9.13nW with a delay of 77 nS. The circuits are simulated with MOSFET models of level 54 using HSPICE in 90 nm process technology.
In this paper, a novel low-power dual edge-triggered (DET) D-type flip-flop is proposed. This design achieves dual edge-triggered with two parallel data paths work in opposite phases of the clock single. Among them, a latch circuit structure employs differential input data signals which deposits very little capacitance on the clock line is accomplished. For fair comparison, four previously reported DET flipflops along with the proposed DETFF (DET flip-flop) are compared in terms of power consumption and power-delay product (PDP), under different data activities and different data rates. Several HSPICE simulation results show that the proposed DETFF is superior in power reduction at different parameters as compared to the existing DETFFs. Hence, the proposed DETFF is well suited for low power applications.
DUAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH LOW POWER CONSUMPTIONijcsit
In this paper, a novel low-power dual edge-triggered (DET) D-type flip-flop is proposed. This design achieves dual edge-triggered with two parallel data paths work in opposite phases of the clock single. Among them, a latch circuit structure employs differential input data signals which deposits very little capacitance on the clock line is accomplished. For fair comparison, four previously reported DET flipflops along with the proposed DETFF (DET flip-flop) are compared in terms of power consumption and power-delay product (PDP), under different data activities and different data rates. Several HSPICE simulation results show that the proposed DETFF is superior in power reduction at different parameters as compared to the existing DETFFs. Hence, the proposed DETFF is well suited for low power applications.
Design of area and power efficient half adder using transmission gateeSAT Journals
Abstract This paper gives an idea to reduce power and surface area of half adder circuit using very popular technique i.e. transmission gate. An adder is a digital circuit that performs addition of two numbers. In many computers and other kind of processors, adders are used not only in arithmetic logic unit but also in other parts of the processors where they are used to calculate addresses, table indices and similar operations .in this paper two bit addition has been done using conventional and transmission gate level and power, area and number of transistors are the scope of comparison. According to the simulation result, power and area are reduced by 55.35 % and 40.269% respectively when the circuit is implemented by transmission gate .thus transmission gate has become a very popular and useful technique to implement digital circuits which help to reduce power, surface area as well as number of transistors. Keywords: Transmission gate (TG), Half adder, CMOS logic gates, Surface area, Power.
A NEW DATA ENCODER AND DECODER SCHEME FOR NETWORK ON CHIPEditor IJMTER
System-on-chip (soc) based system has so many disadvantages in power-dissipation as
well as clock rate while the data transfer from one system to another system in on-chip. At the same
time, a higher operated system does not support the lower operated bus network for data transfer.
However an alternative scheme is proposed for high speed data transfer. But this scheme is limited to
SOCs. Unlike soc, network-on-chip (NOC) has so many advantages for data transfer. It has a special
feature to transfer the data in on-chip named as transitional encoder. Its operation is based on input
transitions. At the same time it supports systems which are higher operated frequencies. In this
project, a low-power encoding scheme is proposed. The proposed system yields lower dynamic
power dissipation due to the reduction of switching activity and coupling switching activity when
compared to existing system. Even-though many factors which is based on power dissipation, the
dynamic power dissipation is only considerable for reasonable advantage. The proposed system is
synthesized using quartus II 9.1 software. Besides, the proposed system will be extended up to
interlink PE communication with help of routers and PE’s which are performed by various
operations. To implement this system in real NOC’s contains the proposed encoders and decoders for
data transfer with regular traffic scenarios should be considered.
Area Efficient Pulsed Clock Generator Using Pulsed Latch Shift RegisterIJMTST Journal
Shift Registers are building blocks used for the storage of data in many devices. Currently, Flip flops which have been used in Shift Registers consume more Power and impose a heavy load on Clock distribution networks. The Proposed work overcomes the Power consumption and reduces the delay by using the Pulsed Latches instead of the Flip flops. Conventional Latches-Static differential Sense Amplifier Shared Pulse Latch (SSASPL) has been used where the number of Transistors has been reduced. Trigger generator is used to give non overlap clock signals to the memory elements, which reduced the delay and produced the fast implementation of the data. The Power consumed reduces by 27% and delay reduces by 21% when compared to the Shift Registers using Flip flops.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
A NOVEL LOW POWER HIGH DYNAMIC THRESHOLD SWING LIMITED REPEATER INSERTION FOR...VLSICS Design
In Very Large Scale Integration (VLSI), interconnect design has become a supreme issue in high speed ICs. With the decreased feature size of CMOS circuits, on-chip interconnect now dominates both circuit delay and power consumption. An eminent technique known as repeater/buffer insertion is used in long interconnections to reduce delay in VLSI circuits. This paper deals with some distinct low power alternative circuits in buffer insertion technique and it proposes two new techniques: Dynamic Threshold Swing Limited (DTSL) and High Dynamic Threshold Swing Limited (HDTSL). The DTSL uses Dynamic Threshold MOSFET configuration. In this gate is tied to the body and it limits the output swing. High Dynamic Threshold Swing Limited (HDTSL) also uses the same configuration along with a high threshold voltage(high-Vth). The simulation results are performed in Cadence virtuoso environment tool using 45nm technology. By simulating and comparing these various repeater circuits along with the proposed circuits it is analyzed that there is trade off among power, delay and Power Delay Product and the 34.66% of power is reduced by using the high- Vth in HDTSL when compared to DTSL.
A novel low power high dynamic threshold swing limited repeater insertion for...VLSICS Design
In Very Large Scale Integration (VLSI), interconnect design has become a supreme issue in high speed ICs.
With the decreased feature size of CMOS circuits, on-chip interconnect now dominates both circuit delay
and power consumption. An eminent technique known as repeater/buffer insertion is used in long
interconnections to reduce delay in VLSI circuits. This paper deals with some distinct low power
alternative circuits in buffer insertion technique and it proposes two new techniques: Dynamic Threshold
Swing Limited (DTSL) and High Dynamic Threshold Swing Limited (HDTSL). The DTSL uses Dynamic
Threshold MOSFET configuration. In this gate is tied to the body and it limits the output swing. High
Dynamic Threshold Swing Limited (HDTSL) also uses the same configuration along with a high threshold
voltage(high-Vth). The simulation results are performed in Cadence virtuoso environment tool using 45nm
technology. By simulating and comparing these various repeater circuits along with the proposed circuits it
is analyzed that there is trade off among power, delay and Power Delay Product and the 34.66% of power
is reduced by using the high- Vth in HDTSL when compared to DTSL.
High performance novel dual stack gating technique for reduction of ground bo...eSAT Journals
Abstract The development of digital integrated circuits is challenged by higher power consumption. The combination of higher clock speeds, greater functional integration, and smaller process geometries has contributed to significant growth in power density. Today leakage power has become an increasingly important issue in processor hardware and software design. So to reduce the leakages in the circuit many low power strategies are identified and experiments are carried out. But the leakage due to ground connection to the active part of the circuit is very higher than all other leakages. As it is mainly due to the back EMF of the ground connection we are calling it as ground bounce noise. To reduce this noise, different methodologies are designed. In this paper, a number of critical considerations in the sleep transistor design and implementation includes header or footer switch selection, sleep transistor distribution choices and sleep transistor gate length, width and body bias optimization for area, leakage and efficiency. Novel dual stack technique is proposed that reduces not only the leakage power but also dynamic power. The previous techniques are summarized and compared with this new approach and comparison of both the techniques is done with the help of Digital Schematic( DSCH ) and Microwind low power tools. Stacking power gating technique has been analyzed and the conditions for the important design parameters (Minimum ground bounce noise) have been derived. The Monte-Carlo simulation is performed in Microwind to calculate the values of all the needed parameters for comparison. Index Terms: Ground Bounce Noise ,Power gating schemes ,Static power dissipation, Dynamic power dissipation, Power gating parameters, Sleep transistors, Novel dual stack approach, Transistor leakage power
International Journal of Engineering Research and Applications (IJERA) is a team of researchers not publication services or private publications running the journals for monetary benefits, we are association of scientists and academia who focus only on supporting authors who want to publish their work. The articles published in our journal can be accessed online, all the articles will be archived for real time access.
Our journal system primarily aims to bring out the research talent and the works done by sciaentists, academia, engineers, practitioners, scholars, post graduate students of engineering and science. This journal aims to cover the scientific research in a broader sense and not publishing a niche area of research facilitating researchers from various verticals to publish their papers. It is also aimed to provide a platform for the researchers to publish in a shorter of time, enabling them to continue further All articles published are freely available to scientific researchers in the Government agencies,educators and the general public. We are taking serious efforts to promote our journal across the globe in various ways, we are sure that our journal will act as a scientific platform for all researchers to publish their works online.
A high speed dynamic ripple carry addereSAT Journals
Abstract Adder, which is one of the basic building blocks of a processor affect the performance of the processor. There are many adder architectures each of them have their own advantage. Ripple Carry Adder (RCA) architecture occupies the minimum area among the other architectures with lesser power dissipation. RCA experiences more delay due to its carry propagation in critical path; apart from the delay it also experiences glitches. Constant delay (CD) logic solves both the delay problems and glitch related problems. CD logic, due to its pre-evaluated characteristics delivers high speed but due its bulkier nature it is used only in the critical path. In this paper two new techniques are presented which modifies the conventional timing block (requires ten transistors) in CD logic and two new timing blocks one with eight transistors and other with nine transistors are developed. The CD logic with the two new timing block is used in critical path of RCA to achieve higher speed performance with lesser area compared to conventional CD logic. The CD logic with 9-transistor timing block achieves 70% and 39% delay reduction compared to Static and Domino logics. It also achieves 21% and 5% reduction in power dissipation and delay. The 8-transistor version also achieves reduction of delay by 65% and 29% compared to Static and dynamic logic. The two versions of timing blocks have their own advantages where 9-transistor version provides high speed and 8- transistor version provides lesser power dissipation. Simulations are carried out in 130 nm at 1V power supply using mentor graphics tools. Key Words: Critical Path, Feed Through Logic, Constant Delay logic, Pre-evaluated logic, and Timing block.
Comparative Analysis of Efficient Designs of D Latch using 32nm CMOS Technologyijtsrd
In this paper we have proposed various efficient designs of low power D latch using 32nm CMOS technology. We have designed and simulated these circuits in HSpice simulation tool. In this simulation we have modified W L ratio of each transistor in each circuit. We have taken power supply of 0.9V. We have calculated average power consumed propagation delay and power delay product. Tanusha Beni Vyas | Shubhash Chandra "Comparative Analysis of Efficient Designs of D- Latch using 32nm CMOS Technology" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-3 | Issue-5 , August 2019, URL: https://www.ijtsrd.com/papers/ijtsrd26707.pdf Paper URL: https://www.ijtsrd.com/engineering/computer-engineering/26707/comparative-analysis-of-efficient-designs-of-d--latch-using-32nm-cmos-technology/tanusha-beni-vyas
Codec Scheme for Power Optimization in VLSI InterconnectsIJEEE
This paper presents a codec scheme for optimizing power in VLSI Interconnects. It is based on the traditional bus encoding method which is considered to be one of the most effective ways of power and delay reduction. The work done aims at optimizing power by designing the scheme using Full-Custom design approach. The model has been designed and implemented using Cadence Virtuoso Analog Design Suite in 0.18µm CMOS technology. Power has been computed for different possible combinations of input data. Delay has been reckoned for the maximum power consuming input combination. Layout editor has been used to generate the physical description of the circuit. The 4 bit input data combination consuming maximum dynamic power of 6.44µW and propagation delay of 722.7ps is “1000” with previously transmitted 4 bit data being “0111”. A significant power reduction of 38.89% has been observed by designing the scheme using Full-Custom approach as compared to the conventional Semi-Custom approach of design.
A COMPARATIVE STUDY OF ULTRA-LOW VOLTAGE DIGITAL CIRCUIT DESIGNVLSICS Design
Ultra-low voltage digital circuit design is an active research area, especially for portable applications such as wearable electronics, intelligent remote sensors, implantable medical devices, and energy-harvesting systems. Due to their application scenarios and circuit components, two major goals for these systems are minimizing energy consumption and improving compatibility with low-voltage power supplies and analog components. The most effective solution to achieve these goals is to reduce the supply voltage, which, however, raises the issue of operability. At ultra-low supply voltages, the integrity of digital signals degrades dramatically due to the indifference between active and leakage currents. In addition, the system timing becomes more unpredictable as the impact of process and supply voltage variations being more significant at lower voltages. This paper presents a comparative study among three techniques for designing digital circuits operating at ultra-low voltages, i.e., Schmitt-triggered gate structure, delayinsensitive asynchronous logic, and Fully-Depleted Silicon-on-Insulator technology. Results show that despite the tradeoffs, all eight combinations of these techniques are viable for designing ultra-low voltage circuits. For a given application, the optimum circuit design can be selected from these combinations based on the lowest voltage, the dynamic range, the power budget, the performance requirement, and the available semiconductor process node.
Comparative analysis of lector and stack technique to reduce the leakage curr...eSAT Journals
Abstract CMOS is the latest technology available in today’s world. And the biggest advantage of this technology is it does not consume any power. So the total power consumption is dependent on its leakage power. Since leakage exists in the circuit even if it is in stand by state i.e. the state in which gate of the circuit is not getting power supply. So the power loss in the circuit is high. And that’s why our major concern is to reduce the leakage current in the circuit. Varieties of different techniques are available to reduce the leakage current and still continue to derive more, better techniques. In this paper two different techniques LECTOR and STACK technique which are based on the same principle have been comparatively analyzed. Keywords: Delay, Leakage current, Lector technique, Stack technique.
Similar to Low power and high performance detff using common feedback inverter logic (20)
Mechanical properties of hybrid fiber reinforced concrete for pavementseSAT Journals
Abstract
The effect of addition of mono fibers and hybrid fibers on the mechanical properties of concrete mixture is studied in the present
investigation. Steel fibers of 1% and polypropylene fibers 0.036% were added individually to the concrete mixture as mono fibers and
then they were added together to form a hybrid fiber reinforced concrete. Mechanical properties such as compressive, split tensile and
flexural strength were determined. The results show that hybrid fibers improve the compressive strength marginally as compared to
mono fibers. Whereas, hybridization improves split tensile strength and flexural strength noticeably.
Keywords:-Hybridization, mono fibers, steel fiber, polypropylene fiber, Improvement in mechanical properties.
Material management in construction – a case studyeSAT Journals
Abstract
The objective of the present study is to understand about all the problems occurring in the company because of improper application
of material management. In construction project operation, often there is a project cost variance in terms of the material, equipments,
manpower, subcontractor, overhead cost, and general condition. Material is the main component in construction projects. Therefore,
if the material management is not properly managed it will create a project cost variance. Project cost can be controlled by taking
corrective actions towards the cost variance. Therefore a methodology is used to diagnose and evaluate the procurement process
involved in material management and launch a continuous improvement was developed and applied. A thorough study was carried
out along with study of cases, surveys and interviews to professionals involved in this area. As a result, a methodology for diagnosis
and improvement was proposed and tested in selected projects. The results obtained show that the main problem of procurement is
related to schedule delays and lack of specified quality for the project. To prevent this situation it is often necessary to dedicate
important resources like money, personnel, time, etc. To monitor and control the process. A great potential for improvement was
detected if state of the art technologies such as, electronic mail, electronic data interchange (EDI), and analysis were applied to the
procurement process. These helped to eliminate the root causes for many types of problems that were detected.
Managing drought short term strategies in semi arid regions a case studyeSAT Journals
Abstract
Drought management needs multidisciplinary action. Interdisciplinary efforts among the experts in various fields of the droughts
prone areas are helpful to achieve tangible and permanent solution for this recurring problem. The Gulbarga district having the total
area around 16, 240 sq.km, and accounts 8.45 per cent of the Karnataka state area. The district has been situated with latitude 17º 19'
60" North and longitude of 76 º 49' 60" east. The district is situated entirely on the Deccan plateau positioned at a height of 300 to
750 m above MSL. Sub-tropical, semi-arid type is one among the drought prone districts of Karnataka State. The drought
management is very important for a district like Gulbarga. In this paper various short term strategies are discussed to mitigate the
drought condition in the district.
Keywords: Drought, South-West monsoon, Semi-Arid, Rainfall, Strategies etc.
Life cycle cost analysis of overlay for an urban road in bangaloreeSAT Journals
Abstract
Pavements are subjected to severe condition of stresses and weathering effects from the day they are constructed and opened to traffic
mainly due to its fatigue behavior and environmental effects. Therefore, pavement rehabilitation is one of the most important
components of entire road systems. This paper highlights the design of concrete pavement with added mono fibers like polypropylene,
steel and hybrid fibres for a widened portion of existing concrete pavement and various overlay alternatives for an existing
bituminous pavement in an urban road in Bangalore. Along with this, Life cycle cost analyses at these sections are done by Net
Present Value (NPV) method to identify the most feasible option. The results show that though the initial cost of construction of
concrete overlay is high, over a period of time it prove to be better than the bituminous overlay considering the whole life cycle cost.
The economic analysis also indicates that, out of the three fibre options, hybrid reinforced concrete would be economical without
compromising the performance of the pavement.
Keywords: - Fatigue, Life cycle cost analysis, Net Present Value method, Overlay, Rehabilitation
Laboratory studies of dense bituminous mixes ii with reclaimed asphalt materialseSAT Journals
Abstract
The issue of growing demand on our nation’s roadways over that past couple of decades, decreasing budgetary funds, and the need to
provide a safe, efficient, and cost effective roadway system has led to a dramatic increase in the need to rehabilitate our existing
pavements and the issue of building sustainable road infrastructure in India. With these emergency of the mentioned needs and this
are today’s burning issue and has become the purpose of the study.
In the present study, the samples of existing bituminous layer materials were collected from NH-48(Devahalli to Hassan) site.The
mixtures were designed by Marshall Method as per Asphalt institute (MS-II) at 20% and 30% Reclaimed Asphalt Pavement (RAP).
RAP material was blended with virgin aggregate such that all specimens tested for the, Dense Bituminous Macadam-II (DBM-II)
gradation as per Ministry of Roads, Transport, and Highways (MoRT&H) and cost analysis were carried out to know the economics.
Laboratory results and analysis showed the use of recycled materials showed significant variability in Marshall Stability, and the
variability increased with the increase in RAP content. The saving can be realized from utilization of recycled materials as per the
methodology, the reduction in the total cost is 19%, 30%, comparing with the virgin mixes.
Keywords: Reclaimed Asphalt Pavement, Marshall Stability, MS-II, Dense Bituminous Macadam-II
Laboratory investigation of expansive soil stabilized with natural inorganic ...eSAT Journals
Abstract
Soil stabilization has proven to be one of the oldest techniques to improve the soil properties. Literature review conducted revealed
that uses of natural inorganic stabilizers are found to be one of the best options for soil stabilization. In this regard an attempt has
been made to evaluate the influence of RBI-81 stabilizer on properties of black cotton soil through laboratory investigations. Black
cotton soil with varying percentages of RBI-81 viz., 0, 0.5, 1, 1.5, 2, and 2.5 percent were studied for moisture density relationships
and strength behaviour of soils. Also the effect of curing period was evaluated as literature review clearly emphasized the strength
gain of soils stabilized with RBI-81 over a period of time. The results obtained shows that the unconfined compressive strength of
specimens treated with RBI-81 increased approximately by 250% for a curing period of 28 days as compared to virgin soil. Further
the CBR value improved approximately by 400%. The studies indicated an increasing trend for soil strength behaviour with
increasing percentage of RBI-81 suggesting its potential applications in soil stabilization.
Influence of reinforcement on the behavior of hollow concrete block masonry p...eSAT Journals
Abstract
Reinforced masonry was developed to exploit the strength potential of masonry and to solve its lack of tensile strength. Experimental
and analytical studies have been carried out to investigate the effect of reinforcement on the behavior of hollow concrete block
masonry prisms under compression and to predict ultimate failure compressive strength. In the numerical program, three dimensional
non-linear finite elements (FE) model based on the micro-modeling approach is developed for both unreinforced and reinforced
masonry prisms using ANSYS (14.5). The proposed FE model uses multi-linear stress-strain relationships to model the non-linear
behavior of hollow concrete block, mortar, and grout. Willam-Warnke’s five parameter failure theory has been adopted to model the
failure of masonry materials. The comparison of the numerical and experimental results indicates that the FE models can successfully
capture the highly nonlinear behavior of the physical specimens and accurately predict their strength and failure mechanisms.
Keywords: Structural masonry, Hollow concrete block prism, grout, Compression failure, Finite element method,
Numerical modeling.
Influence of compaction energy on soil stabilized with chemical stabilizereSAT Journals
Abstract
Increase in traffic along with heavier magnitude of wheel loads cause rapid deterioration in pavements. There is a need to improve
density, strength of soil subgrade and other pavement layers. In this study an attempt is made to improve the properties of locally
available loamy soil using twin approaches viz., i) increasing the compaction of soil and ii) treating the soil with chemical stabilizer.
Laboratory studies are carried out on both untreated and treated soil samples compacted by different compaction efforts. Studies
show that increase in compaction effort results in increase in density of soil. However in soil treated with chemical stabilizer, rate of
increase in density is not significant. The soil treated with chemical stabilizer exhibits improvement in both strength and performance
properties.
Keywords: compaction, density, subgradestabilization, resilient modulus
Geographical information system (gis) for water resources managementeSAT Journals
Abstract
Water resources projects are inherited with overlapping and at times conflicting objectives. These projects are often of varied sizes
ranging from major projects with command areas of millions of hectares to very small projects implemented at the local level. Thus,
in all these projects there is seldom proper coordination which is essential for ensuring collective sustainability.
Integrated watershed development and management is the accepted answer but in turn requires a comprehensive framework that can
enable planning process involving all the stakeholders at different levels and scales is compulsory. Such a unified hydrological
framework is essential to evaluate the cause and effect of all the proposed actions within the drainage basins.
The present paper describes a hydrological framework developed in the form of a Hydrologic Information System (HIS) which is
intended to meet the specific information needs of the various line departments of a typical State connected with water related aspects.
The HIS consist of a hydrologic information database coupled with tools for collating primary and secondary data and tools for
analyzing and visualizing the data and information. The HIS also incorporates hydrological model base for indirect assessment of
various entities of water balance in space and time. The framework would be maintained and updated to reflect fully the most
accurate ground truth data and the infrastructure requirements for planning and management.
Keywords: Hydrological Information System (HIS); WebGIS; Data Model; Web Mapping Services
Forest type mapping of bidar forest division, karnataka using geoinformatics ...eSAT Journals
Abstract
The study demonstrate the potentiality of satellite remote sensing technique for the generation of baseline information on forest types
including tree plantation details in Bidar forest division, Karnataka covering an area of 5814.60Sq.Kms. The Total Area of Bidar
forest division is 5814Sq.Kms analysis of the satellite data in the study area reveals that about 84% of the total area is Covered by
crop land, 1.778% of the area is covered by dry deciduous forest, 1.38 % of mixed plantation, which is very threatening to the
environmental stability of the forest, future plantation site has been mapped. With the use of latest Geo-informatics technology proper
and exact condition of the trees can be observed and necessary precautions can be taken for future plantation works in an appropriate
manner
Keywords:-RS, GIS, GPS, Forest Type, Tree Plantation
Factors influencing compressive strength of geopolymer concreteeSAT Journals
Abstract
To study effects of several factors on the properties of fly ash based geopolymer concrete on the compressive strength and also the
cost comparison with the normal concrete. The test variables were molarities of sodium hydroxide(NaOH) 8M,14M and 16M, ratio of
NaOH to sodium silicate (Na2SiO3) 1, 1.5, 2 and 2.5, alkaline liquid to fly ash ratio 0.35 and 0.40 and replacement of water in
Na2SiO3 solution by 10%, 20% and 30% were used in the present study. The test results indicated that the highest compressive
strength 54 MPa was observed for 16M of NaOH, ratio of NaOH to Na2SiO3 2.5 and alkaline liquid to fly ash ratio of 0.35. Lowest
compressive strength of 27 MPa was observed for 8M of NaOH, ratio of NaOH to Na2SiO3 is 1 and alkaline liquid to fly ash ratio of
0.40. Alkaline liquid to fly ash ratio of 0.35, water replacement of 10% and 30% for 8 and 16 molarity of NaOH and has resulted in
compressive strength of 36 MPa and 20 MPa respectively. Superplasticiser dosage of 2 % by weight of fly ash has given higher
strength in all cases.
Keywords: compressive strength, alkaline liquid, fly ash
Experimental investigation on circular hollow steel columns in filled with li...eSAT Journals
Abstract
Composite Circular hollow Steel tubes with and without GFRP infill for three different grades of Light weight concrete are tested for
ultimate load capacity and axial shortening , under Cyclic loading. Steel tubes are compared for different lengths, cross sections and
thickness. Specimens were tested separately after adopting Taguchi’s L9 (Latin Squares) Orthogonal array in order to save the initial
experimental cost on number of specimens and experimental duration. Analysis was carried out using ANN (Artificial Neural
Network) technique with the assistance of Mini Tab- a statistical soft tool. Comparison for predicted, experimental & ANN output is
obtained from linear regression plots. From this research study, it can be concluded that *Cross sectional area of steel tube has most
significant effect on ultimate load carrying capacity, *as length of steel tube increased- load carrying capacity decreased & *ANN
modeling predicted acceptable results. Thus ANN tool can be utilized for predicting ultimate load carrying capacity for composite
columns.
Keywords: Light weight concrete, GFRP, Artificial Neural Network, Linear Regression, Back propagation, orthogonal
Array, Latin Squares
Experimental behavior of circular hsscfrc filled steel tubular columns under ...eSAT Journals
Abstract
This paper presents an outlook on experimental behavior and a comparison with predicted formula on the behaviour of circular
concentrically loaded self-consolidating fibre reinforced concrete filled steel tube columns (HSSCFRC). Forty-five specimens were
tested. The main parameters varied in the tests are: (1) percentage of fiber (2) tube diameter or width to wall thickness ratio (D/t
from 15 to 25) (3) L/d ratio from 2.97 to 7.04 the results from these predictions were compared with the experimental data. The
experimental results) were also validated in this study.
Keywords: Self-compacting concrete; Concrete-filled steel tube; axial load behavior; Ultimate capacity.
Evaluation of punching shear in flat slabseSAT Journals
Abstract
Flat-slab construction has been widely used in construction today because of many advantages that it offers. The basic philosophy in
the design of flat slab is to consider only gravity forces; this method ignores the effect of punching shear due to unbalanced moments
at the slab column junction which is critical. An attempt has been made to generate generalized design sheets which accounts both
punching shear due to gravity loads and unbalanced moments for cases (a) interior column; (b) edge column (bending perpendicular
to shorter edge); (c) edge column (bending parallel to shorter edge); (d) corner column. These design sheets are prepared as per
codal provisions of IS 456-2000. These design sheets will be helpful in calculating the shear reinforcement to be provided at the
critical section which is ignored in many design offices. Apart from its usefulness in evaluating punching shear and the necessary
shear reinforcement, the design sheets developed will enable the designer to fix the depth of flat slab during the initial phase of the
design.
Keywords: Flat slabs, punching shear, unbalanced moment.
Evaluation of performance of intake tower dam for recent earthquake in indiaeSAT Journals
Abstract
Intake towers are typically tall, hollow, reinforced concrete structures and form entrance to reservoir outlet works. A parametric
study on dynamic behavior of circular cylindrical towers can be carried out to study the effect of depth of submergence, wall thickness
and slenderness ratio, and also effect on tower considering dynamic analysis for time history function of different soil condition and
by Goyal and Chopra accounting interaction effects of added hydrodynamic mass of surrounding and inside water in intake tower of
dam
Key words: Hydrodynamic mass, Depth of submergence, Reservoir, Time history analysis,
Evaluation of operational efficiency of urban road network using travel time ...eSAT Journals
Abstract
Efficiency of the road network system is analyzed by travel time reliability measures. The study overlooks on an important measure of
travel time reliability and prioritizing Tiruchirappalli road network. Traffic volume and travel time were collected using license plate
matching method. Travel time measures were estimated from average travel time and 95th travel time. Effect of non-motorized vehicle
on efficiency of road system was evaluated. Relation between buffer time index and traffic volume was created. Travel time model has
been developed and travel time measure was validated. Then service quality of road sections in network were graded based on
travel time reliability measures.
Keywords: Buffer Time Index (BTI); Average Travel Time (ATT); Travel Time Reliability (TTR); Buffer Time (BT).
Estimation of surface runoff in nallur amanikere watershed using scs cn methodeSAT Journals
Abstract
The development of watershed aims at productive utilization of all the available natural resources in the entire area extending from
ridge line to stream outlet. The per capita availability of land for cultivation has been decreasing over the years. Therefore, water and
the related land resources must be developed, utilized and managed in an integrated and comprehensive manner. Remote sensing and
GIS techniques are being increasingly used for planning, management and development of natural resources. The study area, Nallur
Amanikere watershed geographically lies between 110 38’ and 110 52’ N latitude and 760 30’ and 760 50’ E longitude with an area of
415.68 Sq. km. The thematic layers such as land use/land cover and soil maps were derived from remotely sensed data and overlayed
through ArcGIS software to assign the curve number on polygon wise. The daily rainfall data of six rain gauge stations in and around
the watershed (2001-2011) was used to estimate the daily runoff from the watershed using Soil Conservation Service - Curve Number
(SCS-CN) method. The runoff estimated from the SCS-CN model was then used to know the variation of runoff potential with different
land use/land cover and with different soil conditions.
Keywords: Watershed, Nallur watershed, Surface runoff, Rainfall-Runoff, SCS-CN, Remote Sensing, GIS.
Estimation of morphometric parameters and runoff using rs & gis techniqueseSAT Journals
Abstract
Land and water are the two vital natural resources, the optimal management of these resources with minimum adverse environmental
impact are essential not only for sustainable development but also for human survival. Satellite remote sensing with geographic
information system has a pragmatic approach to map and generate spatial input layers of predicting response behavior and yield of
watershed. Hence, in the present study an attempt has been made to understand the hydrological process of the catchment at the
watershed level by drawing the inferences from moprhometric analysis and runoff. The study area chosen for the present study is
Yagachi catchment situated in Chickamaglur and Hassan district lies geographically at a longitude 75⁰52’08.77”E and
13⁰10’50.77”N latitude. It covers an area of 559.493 Sq.km. Morphometric analysis is carried out to estimate morphometric
parameters at Micro-watershed to understand the hydrological response of the catchment at the Micro-watershed level. Daily runoff
is estimated using USDA SCS curve number model for a period of 10 years from 2001 to 2010. The rainfall runoff relationship of the
study shows there is a positive correlation.
Keywords: morphometric analysis, runoff, remote sensing and GIS, SCS - method
-
Effect of variation of plastic hinge length on the results of non linear anal...eSAT Journals
Abstract The nonlinear Static procedure also well known as pushover analysis is method where in monotonically increasing loads are applied to the structure till the structure is unable to resist any further load. It is a popular tool for seismic performance evaluation of existing and new structures. In literature lot of research has been carried out on conventional pushover analysis and after knowing deficiency efforts have been made to improve it. But actual test results to verify the analytically obtained pushover results are rarely available. It has been found that some amount of variation is always expected to exist in seismic demand prediction of pushover analysis. Initial study is carried out by considering user defined hinge properties and default hinge length. Attempt is being made to assess the variation of pushover analysis results by considering user defined hinge properties and various hinge length formulations available in literature and results compared with experimentally obtained results based on test carried out on a G+2 storied RCC framed structure. For the present study two geometric models viz bare frame and rigid frame model is considered and it is found that the results of pushover analysis are very sensitive to geometric model and hinge length adopted. Keywords: Pushover analysis, Base shear, Displacement, hinge length, moment curvature analysis
Effect of use of recycled materials on indirect tensile strength of asphalt c...eSAT Journals
Abstract
Depletion of natural resources and aggregate quarries for the road construction is a serious problem to procure materials. Hence
recycling or reuse of material is beneficial. On emphasizing development in sustainable construction in the present era, recycling of
asphalt pavements is one of the effective and proven rehabilitation processes. For the laboratory investigations reclaimed asphalt
pavement (RAP) from NH-4 and crumb rubber modified binder (CRMB-55) was used. Foundry waste was used as a replacement to
conventional filler. Laboratory tests were conducted on asphalt concrete mixes with 30, 40, 50, and 60 percent replacement with RAP.
These test results were compared with conventional mixes and asphalt concrete mixes with complete binder extracted RAP
aggregates. Mix design was carried out by Marshall Method. The Marshall Tests indicated highest stability values for asphalt
concrete (AC) mixes with 60% RAP. The optimum binder content (OBC) decreased with increased in RAP in AC mixes. The Indirect
Tensile Strength (ITS) for AC mixes with RAP also was found to be higher when compared to conventional AC mixes at 300C.
Keywords: Reclaimed asphalt pavement, Foundry waste, Recycling, Marshall Stability, Indirect tensile strength.
CFD Simulation of By-pass Flow in a HRSG module by R&R Consult.pptxR&R Consult
CFD analysis is incredibly effective at solving mysteries and improving the performance of complex systems!
Here's a great example: At a large natural gas-fired power plant, where they use waste heat to generate steam and energy, they were puzzled that their boiler wasn't producing as much steam as expected.
R&R and Tetra Engineering Group Inc. were asked to solve the issue with reduced steam production.
An inspection had shown that a significant amount of hot flue gas was bypassing the boiler tubes, where the heat was supposed to be transferred.
R&R Consult conducted a CFD analysis, which revealed that 6.3% of the flue gas was bypassing the boiler tubes without transferring heat. The analysis also showed that the flue gas was instead being directed along the sides of the boiler and between the modules that were supposed to capture the heat. This was the cause of the reduced performance.
Based on our results, Tetra Engineering installed covering plates to reduce the bypass flow. This improved the boiler's performance and increased electricity production.
It is always satisfying when we can help solve complex challenges like this. Do your systems also need a check-up or optimization? Give us a call!
Work done in cooperation with James Malloy and David Moelling from Tetra Engineering.
More examples of our work https://www.r-r-consult.dk/en/cases-en/
Explore the innovative world of trenchless pipe repair with our comprehensive guide, "The Benefits and Techniques of Trenchless Pipe Repair." This document delves into the modern methods of repairing underground pipes without the need for extensive excavation, highlighting the numerous advantages and the latest techniques used in the industry.
Learn about the cost savings, reduced environmental impact, and minimal disruption associated with trenchless technology. Discover detailed explanations of popular techniques such as pipe bursting, cured-in-place pipe (CIPP) lining, and directional drilling. Understand how these methods can be applied to various types of infrastructure, from residential plumbing to large-scale municipal systems.
Ideal for homeowners, contractors, engineers, and anyone interested in modern plumbing solutions, this guide provides valuable insights into why trenchless pipe repair is becoming the preferred choice for pipe rehabilitation. Stay informed about the latest advancements and best practices in the field.
Student information management system project report ii.pdfKamal Acharya
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Immunizing Image Classifiers Against Localized Adversary Attacksgerogepatton
This paper addresses the vulnerability of deep learning models, particularly convolutional neural networks
(CNN)s, to adversarial attacks and presents a proactive training technique designed to counter them. We
introduce a novel volumization algorithm, which transforms 2D images into 3D volumetric representations.
When combined with 3D convolution and deep curriculum learning optimization (CLO), itsignificantly improves
the immunity of models against localized universal attacks by up to 40%. We evaluate our proposed approach
using contemporary CNN architectures and the modified Canadian Institute for Advanced Research (CIFAR-10
and CIFAR-100) and ImageNet Large Scale Visual Recognition Challenge (ILSVRC12) datasets, showcasing
accuracy improvements over previous techniques. The results indicate that the combination of the volumetric
input and curriculum learning holds significant promise for mitigating adversarial attacks without necessitating
adversary training.
Final project report on grocery store management system..pdfKamal Acharya
In today’s fast-changing business environment, it’s extremely important to be able to respond to client needs in the most effective and timely manner. If your customers wish to see your business online and have instant access to your products or services.
Online Grocery Store is an e-commerce website, which retails various grocery products. This project allows viewing various products available enables registered users to purchase desired products instantly using Paytm, UPI payment processor (Instant Pay) and also can place order by using Cash on Delivery (Pay Later) option. This project provides an easy access to Administrators and Managers to view orders placed using Pay Later and Instant Pay options.
In order to develop an e-commerce website, a number of Technologies must be studied and understood. These include multi-tiered architecture, server and client-side scripting techniques, implementation technologies, programming language (such as PHP, HTML, CSS, JavaScript) and MySQL relational databases. This is a project with the objective to develop a basic website where a consumer is provided with a shopping cart website and also to know about the technologies used to develop such a website.
This document will discuss each of the underlying technologies to create and implement an e- commerce website.
Sachpazis:Terzaghi Bearing Capacity Estimation in simple terms with Calculati...Dr.Costas Sachpazis
Terzaghi's soil bearing capacity theory, developed by Karl Terzaghi, is a fundamental principle in geotechnical engineering used to determine the bearing capacity of shallow foundations. This theory provides a method to calculate the ultimate bearing capacity of soil, which is the maximum load per unit area that the soil can support without undergoing shear failure. The Calculation HTML Code included.
Cosmetic shop management system project report.pdfKamal Acharya
Buying new cosmetic products is difficult. It can even be scary for those who have sensitive skin and are prone to skin trouble. The information needed to alleviate this problem is on the back of each product, but it's thought to interpret those ingredient lists unless you have a background in chemistry.
Instead of buying and hoping for the best, we can use data science to help us predict which products may be good fits for us. It includes various function programs to do the above mentioned tasks.
Data file handling has been effectively used in the program.
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Low power and high performance detff using common feedback inverter logic
1. IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308
_______________________________________________________________________________________
Volume: 02 Issue: 10 | Oct-2013, Available @ http://www.ijret.org 317
LOW POWER AND HIGH PERFORMANCE DETFF USING COMMON
FEEDBACK INVERTER LOGIC
Y.Yaswanth Kumar1
, A.Varalakshmi2
1
II M. Tech VLSI System Design, SITAMS, JNTU Anantapur, Andhra Pradesh, India, yaswanth.yadalam@gmail.com
2
Asst. Professor, Department of ECE, SITAMS, JNTU Anantapur, Andhra Pradesh, India, varalakshmi.a@gmail.com
Abstract
The power consumption of a system is crucial parameter in modern VLSI circuits especially for low power applications. In this
project, a low power Double Edge Triggered D-Flip Flop (DETFF) design is proposed in 65nm CMOS technology. The proposed
DETFF is having less number of transistors than earlier designs. Simulations are carried out using HSPICE tool with different
clock frequencies ranging from 400MHz to 2GHz and with different supply voltages ranging from 0.8V to 1.2V. In general, a
power delay product (PDP)-based comparison is appropriate for low power portable systems. At nominal condition, the PDP of
the proposed DETFF is improved by 65.48% and 44.85% over earlier designs DETFF1 and DETFF2 respectively. Simulation
results show lowest power dissipation and least delay than existing designs, which claims that the proposed DETFF is suitable for
low power and high speed applications.
Keywords: CMOS, flip-flops, Double-edge triggered, power dissipation, delay and PDP.
--------------------------------------------------------------------***----------------------------------------------------------------------
1. INTRODUCTION
In recent years, consumer's attitudes are gearing towards
better accessibility and mobility that caused a demand for an
ever-increasing number of portable applications, requiring
low-power dissipation and high throughput. For example,
notebook, hand-held, palm-top computers are portable
versions of microprocessors which require low power
dissipation designs. In these applications, not only voice, but
data as well as video are transmitted via wireless links. The
weight and size of these portable devices is determined by
the amount of power required. Low power design is very
important to support these devices, particularly with respect
to the integrated circuits, in which excessive power
consumption will make the chip over heat and cause error or
even permanent damage. The seriousness of this problem
increases with the level of integration and thus we need to
consider the power consumption of the chips for every
component in the device. Hence, the major concerns of the
VLSI circuit designer were low power dissipation, high
speed, small silicon area, low cost and reliability. The
battery lifetime for these products is crucial; hence, a well-
planned low-energy consumption design strategy must be
necessary.
The design for low power issues can’t be overcome without
précised power prediction and optimization tools. Therefore,
there is a critical need for certain tools to calculate power
dissipation during the design to meet the power constraints
to ignore the costly redesign effort. Power dissipation is
given by the equation, P = α CV2
f. Voltage scaling is the
most effective way to decrease power consumption, since
power is proportional to the square of the voltage. However,
voltage scaling is associated with threshold voltage scaling
which can cause the leakage power to increase
exponentially. In order to reduce the complexity of circuit
design, a large proportion of digital circuits are designed to
be synchronous circuits. The power dissipation in
synchronous VLSI circuits is contributed by several factors:
i.e. I/O, logic and clock power dissipation. Clock power
dissipation is divided into three major contributions: clock
wires, clock buffers and flip-flops. Studies show that 40-
45% of total power dissipated in integrated system is due to
clock distribution network and 90% of which is consumed
by the flip-flops and the last branches of the clock
distribution network. D-type flip-flop’s (DFF’s) are one of
the most fundamental building blocks in modern VLSI
systems and it contributes a significant part of the total
power dissipation of the system.
The most popular synchronous digital circuits are edge
triggered flip-flops. Single-edge triggered (SET) flip-flops
and Double-edge triggered (DET) are edge-sensitive
devices, that is, data storage in these flip-flops occurs at
specific edges of the clock signal. During each clock period,
single-edge triggered flip-flops latch data at only one edge,
either rising or falling edge of the clock signal. Double-edge
triggered flip-flops latch data at both rising and falling edges
of the clock signal during each period of the clock signal.
Hence by using double-edge triggered flip-flops (DETFFs),
the clock frequency can be significantly reduced - ideally, to
half while preserving the rate of data processing. Using
lower clock frequency may translate into considerable
power savings for the clocked portions of a circuit.
The DETFF design aims at saving energy both on the clock
distribution network (by halving the clock frequency) and
flip-flops. It is preferable to reduce circuits’ clock loads by
minimizing the number of clocked transistors. A simple
DETFF is implemented with about 50% extra transistors
than the traditional SET flip flop, however, this issue is
2. IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308
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Volume: 02 Issue: 10 | Oct-2013, Available @ http://www.ijret.org 318
being resolved in recent intensive researches. It motivates to
use DETFF for larger and complicated designs, especially
for application specific integrated circuits (ASIC) design.
Several DET flop-flops have been proposed in the literature.
The main attention has been in improving the performance
of the circuits.
This paper is organized as follows: Section II explains the
DETFF structures consist of conventional and proposed
DETFF circuits. The nominal simulation conditions along
with transient analysis and optimization performed during
simulation are discussed in Section III. Section IV consists
of Results and performance of proposed design and
conventional designs comparisons in terms of average
power dissipation, delay and PDP. Paper ends with the
conclusion.
2. DOUBLE EDGE TRIGGERED FLIP FLOP
STRUCTURES
There are several ways to implement a DETFF; In general
they can be categorized into two ways. The first idea is to
insert additional circuitry to generate internal pulse signals
on each clock edge. The second idea is to duplicate the
pathway to enable the flip-flop to sample data on every
clock edge. The same data throughput can be achieved with
half of the clock frequency by using DETFF. In other words
double edge clocking can be used to save half of the power
on the clock distribution network.
2.1 Conventional Double-Edge Triggered Flip-Flops
The DET flip flop given in [1] is shown in figure 1. This
flip- flop is basically a Master Slave flip-flop structure and
has two data paths. The upper data path consists of a Single
Edge Triggered flip-flop (SETFF) implemented using
transmission gates. It employs positive edge. The lower data
path consists of a negative edge triggered flip-flop
implemented using transmission gates. Both the data paths
have feedback loops connected such that whenever the clock
is stopped, the logic level at the output is retained. This flip-
flop has 22 transistors excluding clock driver. In these 22
transistors, 12 transistors are clocked transistors.
Fig -1: DETFF1 given in [1]
The figure 1 shows a pair of parallel loops. When the clock
pulse changes from low to high, the upper loop holds data
and the down loop samples data. But when the clock pulse
changes from high to low, the top loop switches to sample
data and then the down loop switches to hold data.
The DET flip flop given in [2] is shown in figure 2. This
flip-flop is also basically a Master Slave flip-flop structure
and consists of two data paths. The transmission gates (TG)
in both the data path are clocked such that the upper data
path works as positive edge triggered flip flop and lower
data path works as negative edge triggered flip flop. The
upper data path consists of transmission gates TG1, TG2
and inverter I1. The lower data path consists of transmission
gates TG3, TG4 and inverter I3.
The input data is connected to TG1 and TG3 and the output
is taken from inverter I5 whose input is connected with TG2
and TG4. Both the data paths have feedback loops
connected such that whenever the clock is stopped, the logic
level at the output is retained so as to maintain the static
functionality. The feedback in upper data path consists of an
inverter I2 and a pass transistor P1. The feedback in lower
data path consists of an inverter I4 and a pass transistor P2.
This design is identical to figure 1 except feedback path.
The feedback transmission gates of figure 1 are not on
critical paths and replaced with pass transistors. This flip-
flop has 20 transistors excluding clock driver. In these 20
transistors, 10 transistors are clocked transistors.
Fig -2: DETFF2 given in [2]
2.2 Proposed Double-Edge Triggered Flip-Flop
The proposed DET Flip-Flop design is shown in figure 3.
This flip-flop is also basically Master Slave flip-flop
structure and it consists of two data paths. The upper data
path consists of transmission gate TG1, pass transistors (P1,
P2) and an inverter I1. The lower data path consists of
transmission gate TG2, pass transistors (P3, P4) and an
inverter I2. The transmission gate and pass transistors in
both the data paths are clocked such that the upper data path
works as positive edge triggered flip flop and lower data
path works as negative edge triggered flip flop. The inverter
3. IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308
_______________________________________________________________________________________
Volume: 02 Issue: 10 | Oct-2013, Available @ http://www.ijret.org 319
I3 serves as a common feedback inverter and the output of
the inverter I4 forms the output of the present invention.
This design is identical to figure 1 except feedback path has
been changed and the number of clocked transistors is
reduced by using n-type pass transistors instead of
transmission gates. The transmission gates TG2, TG3, TG5,
and TG6 of figure 1 are replaced with pass transistors P1,
P2, P3 and P4 respectively. Basically n-type pass transistors
give weak high but in figure 3, the n-type pass transistors
are followed by an inverter, which results in strong high.
Thus the proposed DETFF in figure 3 is free from threshold
voltage loss problem of pass transistors. The feedback
network of figure 2 is altered by placing the n-type pass
transistor instead of p-type pass transistor. Since, the area
incurred by NMOS is less than that of PMOS transistor in
order to compensate the mobility constraint of NMOS and
PMOS transistors.
According to the DETFF1 and/or DETFF2, one of two loops
always samples the data and the other loop always holds the
data. Therefore, only a single feedback loop is required to
hold the data. The proposed DETFF design eliminates one
feedback loop and reduces the number of transistors
compared to the existing designs. The two inverters I2 and
I4 of figure 1 are used for two feedback paths, but here a
single feedback inverter I3 is used as a common feedback
inverter for two feedback paths as shown in figure 3.
The input data is supplied to one end each of two
transmission gates (TG1, TG2). The other ends of the two
transmission gates (TG1, TG2) are separately connected to
the input of two inverters (I1, I2). The outputs of the two
inverters (I1, I2) are separately connected to the inputs of
another two inverters (I3, I4) via the pass transistors (P1,
P3). The output of inverter I3 goes through two pass
transistors (P2, P4) to connect to one end of the above
mentioned two transmission gates (TG1, TG2) separately,
and the output of the inverter I4 forms the output of the
present invention. Both the data paths have feedback loops
connected such that whenever the clock is stopped, the logic
level at the output is retained so as to maintain the static
functionality.
Fig -3: Proposed DETFF
The novelty of the proposed flip flop lies in the feedback
strategy using common feedback inverter and pass
transistors to make the design static. This improves the
power efficiency of the proposed flip flop. This flip flop has
16 transistors excluding clock driver. In these 16 transistors,
8 transistors are clocked transistors. It is preferred to reduce
number of clocked transistors to achieve low power
dissipation. So, the main advantages of the proposed design
are low power dissipation and increased performance with
low transistor count. Thus the proposed Double Edge
Triggered Flip-Flop (DETFF) has become more efficient in
terms of area, power and speed which claim for better
performance than conventional designs.
3. SIMULATIONS AND TRANSIENT ANALYSIS
Simulation parameters used for comparison are shown in
Table 1. For a fair comparison we simulated all flip-flops on
same simulation parameters.
Table -1: CMOS Simulation parameters
Technology 65nm CMOS
MOSFET Model BSIM 4
Nominal Conditions Vdd =1V, T=25° C
Duty Cycle 50 %
Nominal Clock Frequency 400MHz
Data Rate at Nominal
Clock Frequency
800Mbps
All simulations are carried out using HSPICE simulation
tool at nominal condition with different range of frequencies
from 400MHz to 2GHz and with different range of supply
voltages from 0.8V to 1.2V. The simulated waveform for
the proposed DET flip-flop at nominal condition is shown in
figure 4. This waveform shows that the DETFF is storing
the data in both rising edge and falling edge of the clock
signal.
Fig -4: Output waveform for proposed DETFF
We have optimized the transistor sizes. The transistors, that
are not located on critical path, are implemented with
minimum size. We have improved the feedback path in our
design. We simulated the design to achieve minimum
power- delay (clk-q) product (PDP). Transistor count is also
4. IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308
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Volume: 02 Issue: 10 | Oct-2013, Available @ http://www.ijret.org 320
included to maintain a fair level of comparisons. In DETFF1
there are 12 clocked transistors, in DETFF2 there are 10
clocked transistors while in our design there are only 8
clocked transistors. We have reduced the number of clocked
transistors. Thus we have reduced the power dissipation.
The switching power, which is dominant power, is
proportional to the square of the supply voltage. We have
reduced supply voltage to 1V or even less voltages for the
reduction of the power.
4. PERFORMANCE COMPARISON
The performance of the proposed DETFF is evaluated by
comparing the average power dissipation, delay and PDP
with DETFF 1 and DETFF 2. Comparison of simulation
results at nominal condition for the three FFs is summarized
in Table 2.
Table -2: Comparison of simulation results for the three FFs
at nominal condition
Specification DETFF 1 DETFF 2 Proposed
DETFF
Average Power
Dissipation (µW)
1.471 1.066 0.881
Clk-Q Delay (ps) 26.47 22.86 15.26
PDP (10-18
J) 38.94 24.37 13.44
PDP
Improvement %
over 1
---- 37.42 65.48
No. of Transistors
(excluding clock
driver)
22 20 16
Since D to Q delay depends on when the data transition
occurs, here we measured clock to Q delay. The clock-to-Q
delay is the delay from the active clock input to the new
value of the output. We simulated all DETFFs with different
clock frequencies ranging from 400MHz to 2GHz and with
different supply voltages ranging from 0.8V to 1.2V. Each
flip-flop is optimized for power delay product. In general, a
PDP-based comparison is appropriate for low power
portable systems in which the battery life is the primary
index of energy efficiency.
Table 3 shows the PDP of all three flip flops at different
supply voltages, this indicates that the proposed design has
an average improvement of 65.28% and 45.98% in terms of
PDP as compared to DETFF1 and DETFF2 respectively.
Table -3: PDP of 3 FFs with the variation of supply voltage
VDD
(V)
DET
FF 1
(10-
18
J)
DET
FF 2
(10-
18
J)
Proposed
DETFF
(10-18
J)
Improv
ement
% Over
1
Improv
ement
% Over
2
0.8 37.84 20.81 11.06 70.77 46.85
0.9 36.8 22.09 12.04 67.28 45.5
1.0 38.94 24.37 13.44 65.48 44.85
1.1 41.3 27.85 15.25 63.07 45.24
1.2 43.54 33.32 17.51 59.78 47.45
Table 4 shows the PDP of all three flip flops at different
clock frequencies, this indicates that the proposed design has
an average improvement of 70.82% and 44.25% in terms of
PDP as compared to DETFF1 and DETFF2 respectively.
Chart 1 and chart 2 show the statistical variation of PDP for
all the 3 flip-flops on varying supply voltage and clock
frequency respectively. This shows our design is suitable for
low power dissipation and high performance applications.
Table-4: PDP of 3 FFs with the variation of clock frequency
Clk
Freq
(GH
z)
DET
FF 1
(10-
18
J)
DET
FF 2
(10-
18
J)
Proposed
DETFF
(10-18
J)
Improv
ement
% Over
1
Improv
ement
% Over
2
0.4 38.94 24.37 13.44 65.48 44.85
0.5 43.84 26.92 15.52 64.6 43.46
1.0 67.47 33.89 19.2 71.54 43.35
1.5 95.09 41.54 22.94 75.87 44.78
2.0 114.69 48.55 26.8 76.63 44.8
Chart -1: Statistical variation of PDP for the 3 FFs on
varying supply voltage
5. IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308
_______________________________________________________________________________________
Volume: 02 Issue: 10 | Oct-2013, Available @ http://www.ijret.org 321
Chart -2: Statistical variation of PDP for the 3 FFs on
varying clock frequency
CONCLUSION
The proposed Double-edge-triggered D flip-flop is a low
power, low voltage, high speed and low transistor count flip-
flop designed in 65nm CMOS technology. This is static in
nature. The proposed DETFF design eliminates one
feedback loop by using common feedback inverter logic
thereby reducing the number of transistors and also by using
pass transistors the number of clocked transistors is reduced
compared to the existing DET flip flops. This improves the
power efficiency of the proposed DETFF. The three DET
flip-flops are simulated with different supply voltages
ranging from 0.8V to 1.2V and with different clock
frequencies ranging from 400MHz to 2GHz. At nominal
condition, the PDP of the proposed DETFF is improved by
65.48% and 44.85% over earlier designs DETFF1 and
DETFF2 respectively. Simulation results show that the
proposed design has lowest power dissipation and least
delay thereby it has lowest PDP than existing designs.
Therefore the proposed design is very well suited for low
power and high speed applications operating at low
voltages.
REFERENCES
[1] M. Pedram, Q. Wu, and X. Wu, “A New Design of
Double Edge Triggered Flip-Flops,” Proceedings
of the Asia and South Pacific Design Automation
Conference (ASP-DAC), pp. 417–421, 1998.
[2] Imran Ahmed Khan, Danish Shaikh and Mirza
Tariq Beg,“ 2 GHz Low Power Double Edge
Triggered flip-flop in 65nm CMOS Technology”
IEEE Conference, pp 978-1-4673-1318-6/12, 2012.
[3] Xiaowen Wang, and William H. Robinson, “A
Low-Power Double Edge-Triggered Flip-Flop with
Transmission Gates and Clock Gating” IEEE
Conference , pp 205-208, 2010.
[4] Hossein Karimiyan Alidash, Sayed Masoud Sayedi
and Hossein Saidi, “Low-Power State-Retention
Dual Edge-Triggered Pulsed Latch,” Proceedings
of ICEE 2010, May 11-13, IEEE 2010.
[5] Peiyi Zhao, Jason McNeely, Pradeep Golconda and
Jianping Hu, ”Low Power Design of Double-Edge
Triggered Flip-Flop by Reducing the Number of
Clocked Transistors,” IEEE Conference, 2008.
[6] Yu Chien-Cheng ,“Design of Low-Power Double
Edge-Triggered Flip- Flop Circuit", Second IEEE
Conference on Industrial Electronics and
Applications, pp 2054-2057, 2007.
[7] Ahmed Sayed and Hussain Al-Asaad,“A New Low
Power High Performance Flip-Flop” IEEE
Conference, pp 723-726, 2006.
[8] Nikola Nedovic, Mark Aleksic and Vojin G.
Oklobdzija, “Comparative Analysis of Double-
Edge Versus Single-Edge Triggered Clocked
Storage Elements” IEEE Conference, pp V-105 to
V-108, 2002.
[9] Chandrakasan, W.Bowhill, and F. Fox, “Design of
High-Performance Microprocessor Circuits”, 1st
ed. Piscataway, NJ: IEEE, 2001.
[10]G. E. Tellez, A. Farrahi, and M. Sarafzadeh,
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BIOGRAPHIES
A.Varalakshmi, received her Bachelor
Degree in Electronics &
Communication Engeering from
Jawaharlal Nehru Technological
University Hyderabad in the year 2004,
Master’s Degree in VLSI System
Design from Jawaharlal Nehru
Technological University Hyderabad in
the year 2008. Presently working as an Assistant Professor
in ECE Department In SITAMS at Chittoor. Her interested
areas of research are Nano Electronics, VLSI System Design
and Low Power VLSI Design
6. IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308
_______________________________________________________________________________________
Volume: 02 Issue: 10 | Oct-2013, Available @ http://www.ijret.org 322
Y.Yaswanth Kumar, received his
Bachelor Degree in Electronics and
Commuication Engineering from
Jawaharlal Nehru Technological
University Anantapur in the year 2011.
Currently he is doing his Master’s
Degree in VLSI System Design in
Jawaharlal Nehru Technological University Anantapur. His
interested areas are Low Power VLSI Design, Digital
Circuits Design and VLSI Technology