In circuits, clocks usually play a very important role. Whenever data needs to be sampled, it is done with respect to clock signals. It uses the edges of the clock to sample the data. So, it becomes very much necessary to see to it that the clock signals are properly received specially in receiver circuits where data sampling is done, mainly in Double data rate(DDR) circuits. Due to effects such as jitter, skew, interference, device mismatches etc., duty cycle gets affected. We come up with duty cycle correctors that ensure 50% duty cycle of the clock signals. A duty cycle corrector (DCC) with analog feedback is proposed and simulated in 45nm process technology node. The duty cycle corrector operates for MHz frequency range covering the duty cycle from 35%-65%, with +/- 1.5% accuracy. The design is simple and the power consumption is 1.01mW.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
This work compacts with the modeling, simulation, and application of a Fractional Order Proportional Integral Differential (FOP-I-D) controlled Cascaded Flyback Switched Mode Power Supply (CFSMPS) system. It recommends Parallel cascaded flyback converter for the production of essential DC voltage from the input supply voltage. The output from CFSMPS is regulated by using closed loop configuration. The simulation of Closed-loop Proportional-Integral (PI) and FOP-I-D controlled CFSMPS system has been done and the results of the systems are related. The outcomes signify that the FOP-I-D based system has presented an enhanced response to represent as similar to the PI controlled CFSMPS system. The FOP-I-D controlled CFSMPS system has benefits like decreased steady-state error and enhanced time-domain response.
The study on the effect of voltage ripple on multiphase buck converters with ...journalBEEI
Voltage regulator modules (VRM) need to have low output voltage ripple and tight efficiency to power advanced microprocessors. This paper explains a phase shedding technique to enhance efficiency and its impact on output voltage ripple. In this study, analysis was done on a 4-phase buck converter which is having an input voltage of 45-65 V and delivers an output of 9 V, 12A with a switching frequency of 200Khz. The phase shedding control scheme is suitable for applications such as power sources for programmable logic controllers, which is a part of SCADA systems, which requires a low voltage and high current power supply. Working of a multiphase buck converter with phase shedding is modelled and verified using Matlab/Simulink software. The simulation results show the effect of the phase shedding technique on efficiency in varying load conditions and the effect of an increase of the voltage ripple at the output.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
This work compacts with the modeling, simulation, and application of a Fractional Order Proportional Integral Differential (FOP-I-D) controlled Cascaded Flyback Switched Mode Power Supply (CFSMPS) system. It recommends Parallel cascaded flyback converter for the production of essential DC voltage from the input supply voltage. The output from CFSMPS is regulated by using closed loop configuration. The simulation of Closed-loop Proportional-Integral (PI) and FOP-I-D controlled CFSMPS system has been done and the results of the systems are related. The outcomes signify that the FOP-I-D based system has presented an enhanced response to represent as similar to the PI controlled CFSMPS system. The FOP-I-D controlled CFSMPS system has benefits like decreased steady-state error and enhanced time-domain response.
The study on the effect of voltage ripple on multiphase buck converters with ...journalBEEI
Voltage regulator modules (VRM) need to have low output voltage ripple and tight efficiency to power advanced microprocessors. This paper explains a phase shedding technique to enhance efficiency and its impact on output voltage ripple. In this study, analysis was done on a 4-phase buck converter which is having an input voltage of 45-65 V and delivers an output of 9 V, 12A with a switching frequency of 200Khz. The phase shedding control scheme is suitable for applications such as power sources for programmable logic controllers, which is a part of SCADA systems, which requires a low voltage and high current power supply. Working of a multiphase buck converter with phase shedding is modelled and verified using Matlab/Simulink software. The simulation results show the effect of the phase shedding technique on efficiency in varying load conditions and the effect of an increase of the voltage ripple at the output.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is a team of researchers not publication services or private publications running the journals for monetary benefits, we are association of scientists and academia who focus only on supporting authors who want to publish their work. The articles published in our journal can be accessed online, all the articles will be archived for real time access.
Our journal system primarily aims to bring out the research talent and the works done by sciaentists, academia, engineers, practitioners, scholars, post graduate students of engineering and science. This journal aims to cover the scientific research in a broader sense and not publishing a niche area of research facilitating researchers from various verticals to publish their papers. It is also aimed to provide a platform for the researchers to publish in a shorter of time, enabling them to continue further All articles published are freely available to scientific researchers in the Government agencies,educators and the general public. We are taking serious efforts to promote our journal across the globe in various ways, we are sure that our journal will act as a scientific platform for all researchers to publish their works online.
This slide presents about the basic and importance about load shedding in smart microgrid distribution systems. Later of the class i will discuss about in detail on the process of executing the load shedding.
This paper aims to use a three-phase quasi-Z-source indirect matrix converter (QZSIMC) to expand the voltage gain for application in a Permanent Magnet Synchronous Motor (PMSM) drives. In this converter, a unique quasi-Z-source network (QZSN) connects the three-phase input voltage to conventional indirect matrix converter (IMC) in order to boost the supply voltage for PMSM because of limited voltage gain of IMC. Dual space vector modulation (SVM) is utilized to control the QZSIMC. The amplitude of output voltage for quasi-Z-source network is raised by the shoot-through of the rectifier stage, so the system voltage gain becomes greater. Through selecting the optimized value of shoot through duty ratio (D) and modulation index of the rectifier stage (), the drive system can automatically regulate the output voltage of QZSIMC during conditions of voltage sag , step change in load torque and reference speed change when the required voltage gain of QZSIMC is more than 0.866 depending on input voltage and required output voltage.The vector control technique based on closed loop speed control is proposed to control speed of the motor from zero to rated speed which is combined with the proposed converter to obtain the motor drive. The simulation results with MATLAB /Simulink 2015 are obtained to validate performance of PMSM drive.
An improved closed loop hybrid phase shift controller for dual active bridge ...IJECEIAES
In this paper, a new closed loop hybrid phase shift control is proposed for dual active bridge (DAB) converter with variable input voltage. The extended phase shift (EPS) control is applied when load gets heavy enough and the secondary side phase shift angle decreases to zero. When this modified DAB converter operates at light loads, the triple phase shift (TPS) modulation method is applied, and the added control freedom is the secondary phase shift angle between the two-secondary side switching legs. The hybrid phase shift control (HPS) scheme is a combination of EPS and TPS modulations, and it provides a very simple closed form implementation for the primary and secondary side phase shift angles. Depending on the application by changing the phase shift angles we can achieve Buck or Boost operation. A characteristic table feedback control method has been used for closed loop operation. By using 1D look up table the proposed DAB converter provides constant 400V for any given input voltage.
Investigation of TTMC-SVPWM Strategies for Diode Clamped and Cascaded H-bridg...ijeei-iaes
This paper presents a concept of two types multilevel inverters such as diode clamped and cascaded H-bridge for harmonic reduction on high power applications. Normally, multilevel inverters can be used to reduce the harmonic problems in electrical distribution systems. This paer focused on the performance and analysis of a three phase seven level inverter including diode clamped and cascaded H-bridge based on new tripizodal triangular space vector PWM technique approaches. TTMC based modified Space vector Pulse width modulation technique so called tripizodal triangular Space vector Pulse width modulation (TTMC-SVPWM) technique. In this paper the reference sine wave generated as in case of conventional off set injected SVPWM technique. It is observed that the TTMC-Space vector pulse width modulation ensures excellent, close to optimized pulse distribution results and THD is compared to seven level, diode clamped and cascaded multi level inverters. Theoretical investigations were confirmed by the digital simulations using MATLAB/SIMULINK software.
A Review of Matrix Converter and Novel Control Method of DC-AC Matrix Converteridescitation
For the past three decades, research work in matrix
converter has increased much. This paper presents a new
topology of DC-AC matrix converter, starting with a brief
historical review of different modulation and control strategies
which was developed recently. The purpose of the Paper is to
generate a multilevel output voltage equal to multilevel
inverter with reduced switches. An important part of the paper
is to design a dedicated DC-AC matrix converter and some
new arrays of bidirectional switches in a single module are
also presented. To find the performance of the module the
entire module is designed with MATLAB simulation and tested
with three phase induction motor.
International Journal of Engineering Research and Development (IJERD)IJERD Editor
journal publishing, how to publish research paper, Call For research paper, international journal, publishing a paper, IJERD, journal of science and technology, how to get a research paper published, publishing a paper, publishing of journal, publishing of research paper, reserach and review articles, IJERD Journal, How to publish your research paper, publish research paper, open access engineering journal, Engineering journal, Mathemetics journal, Physics journal, Chemistry journal, Computer Engineering, Computer Science journal, how to submit your paper, peer reviw journal, indexed journal, reserach and review articles, engineering journal, www.ijerd.com, research journals,
yahoo journals, bing journals, International Journal of Engineering Research and Development, google journals, hard copy of journal
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
STATCOM is one of the shunt type FACTS controllers which can supply reactive power and improve bus voltage. STATCOM, a controlling device used on alternating current transmission networks, has advantages like transient free switching and smooth variation of reactive power. This paper proposes a cascaded multilevel inverter type DSTATCOM and DVR to compensate voltage sag in utilities in power distribution network. The proposed DSTATCOM is implemented using multilevel topology with isolated dc energy storage and reduced number of switches. A DVR injects a voltage in series with the system voltage and a D-STATCOM implant a current into the system to correct the voltage sag, swell and interruption. The phase shifter PWM technique is described to generate firing pulse to cascaded inverter. The proposed neuro-fuzzy controller follow itself to the sag and provides effective means of mitigation. The voltage sag with the minimum harmonic at the efficacy end. The proposed technique is simulated using MATLAB/Simulink.
This paper presents a real-time emulator of a dual permanent magnet synchronous motor (PMSM) drive implemented on a field-programmable gate array (FPGA) board for supervision and observation purposes. In order to increase the reliability of the drive, a sensorless speed control method is proposed. This method allows replacing the physical sensor while guaranteeing a satisfactory operation even in faulty conditions. The novelty of the proposed approach consists of an FPGA implementation of an emulator to control the actual system. Hence, this emulator operates in real-time with actual system control in healthy or faulty mode. It gives an observation of the speed rotation in case of fault for the sake of continuity of service. The observation of the rotor position and the speed are achieved using the dSPACE DS52030D digital platform with a digital signal processor (DSP) associated with a Xilinx FPGA.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Analysis and Implementation of Unipolar PWM Strategies for Three Phase Cascad...IJAAS Team
This paper presents unipolar pulse width modulation technique with sinusoidal sampling pulse width modulation are analyzed for three-phase five-level, seven-level, nine-level and eleven-level cascaded multi-level inverter. The unipolar PWM method offers a good opportunity for the realization of the Three-phase inverter control, it is better to use the unipolar PWM method with single carrier wave compared to two reference waves. In such case the motor harmonic losses will be considerably lower.The necessary calculations for generation of unipolar pulse width modulation strategies have presented in detail. The unipolar SPWM voltage switching scheme is selected in this paper because this method offers the advantages of effectively doubling the switching frequency of the inverter voltage. The cascaded multi level inverter fed induction motor is simulated and compared the total harmonic distroction for all level (five-level, seven-level, nine-level and elevel-level)of the inverter. Theoretical investigations were confirmed by the digital simulations using MATLAB/SIMULINK software.
Optimal Body Biasing Technique for CMOS Tapered Buffer IJEEE
This paper represents Fixed Body Biased CMOS Tapered Buffer which is designed to minimize the average power dissipation across large capacitive load. The implementation of Reverse Body Bias (RBB) in the proposed Buffer chain is to vary Vth value of NMOS in the first stage. And with the increase in Vth /sub-threshold leakage current and power has been reduced. The technology constraints on the threshold voltage does not allow designer to set high threshold voltage for MOS devices. Hence, this was found that in proposed circuit that when optimal Reverse Body Bias value is set within (0.2 VDD to 0.4 VDD) range, the average power dissipation across capacitive load reduces to 82.2 % at very less penalty in delay. Thus CMOS buffer designers can use the proposed method to vary Vth while keeping VDD constant, which could improve the performance parameters of Tapered Buffer. The proposed analysis is verified by simulating the 3-stage tapered buffer schematics using standard 180nm CMOS technology in Cadence environment.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
The pulse generator which has been implemented in the pulse electric field (PEF) treatment system for food processing is worth to be highlighted and improved. It is parallel with the advancement in semiconductor technology, which offers robust and accurate devices. This research is an effort to produce a low cost, compact and reliable pulse generator as well as equipped with a pulse width modulation (PWM) method for wide selection of frequency and duty cycle. The result shows that the simulation process has proven the theoretical concept to be right and yields the desired outcome based on the designed values. Then, the actual printed circuit board (PCB) has been fabricated to obtain practical results which intended to be compared with the simulation outcomes. Concerning the frequency and its duty cycle, both parameters can be altered without affecting each other. It means by changing the frequency, duty cycle remains the same and vice versa. Thus, this proposed pulse generator achieves its objective and fits to be implemented in PEF treatment technology. It also can replace the conventional pulse forming network (PFN) which is bulky and costly.
International Journal of Engineering Research and Applications (IJERA) is a team of researchers not publication services or private publications running the journals for monetary benefits, we are association of scientists and academia who focus only on supporting authors who want to publish their work. The articles published in our journal can be accessed online, all the articles will be archived for real time access.
Our journal system primarily aims to bring out the research talent and the works done by sciaentists, academia, engineers, practitioners, scholars, post graduate students of engineering and science. This journal aims to cover the scientific research in a broader sense and not publishing a niche area of research facilitating researchers from various verticals to publish their papers. It is also aimed to provide a platform for the researchers to publish in a shorter of time, enabling them to continue further All articles published are freely available to scientific researchers in the Government agencies,educators and the general public. We are taking serious efforts to promote our journal across the globe in various ways, we are sure that our journal will act as a scientific platform for all researchers to publish their works online.
This slide presents about the basic and importance about load shedding in smart microgrid distribution systems. Later of the class i will discuss about in detail on the process of executing the load shedding.
This paper aims to use a three-phase quasi-Z-source indirect matrix converter (QZSIMC) to expand the voltage gain for application in a Permanent Magnet Synchronous Motor (PMSM) drives. In this converter, a unique quasi-Z-source network (QZSN) connects the three-phase input voltage to conventional indirect matrix converter (IMC) in order to boost the supply voltage for PMSM because of limited voltage gain of IMC. Dual space vector modulation (SVM) is utilized to control the QZSIMC. The amplitude of output voltage for quasi-Z-source network is raised by the shoot-through of the rectifier stage, so the system voltage gain becomes greater. Through selecting the optimized value of shoot through duty ratio (D) and modulation index of the rectifier stage (), the drive system can automatically regulate the output voltage of QZSIMC during conditions of voltage sag , step change in load torque and reference speed change when the required voltage gain of QZSIMC is more than 0.866 depending on input voltage and required output voltage.The vector control technique based on closed loop speed control is proposed to control speed of the motor from zero to rated speed which is combined with the proposed converter to obtain the motor drive. The simulation results with MATLAB /Simulink 2015 are obtained to validate performance of PMSM drive.
An improved closed loop hybrid phase shift controller for dual active bridge ...IJECEIAES
In this paper, a new closed loop hybrid phase shift control is proposed for dual active bridge (DAB) converter with variable input voltage. The extended phase shift (EPS) control is applied when load gets heavy enough and the secondary side phase shift angle decreases to zero. When this modified DAB converter operates at light loads, the triple phase shift (TPS) modulation method is applied, and the added control freedom is the secondary phase shift angle between the two-secondary side switching legs. The hybrid phase shift control (HPS) scheme is a combination of EPS and TPS modulations, and it provides a very simple closed form implementation for the primary and secondary side phase shift angles. Depending on the application by changing the phase shift angles we can achieve Buck or Boost operation. A characteristic table feedback control method has been used for closed loop operation. By using 1D look up table the proposed DAB converter provides constant 400V for any given input voltage.
Investigation of TTMC-SVPWM Strategies for Diode Clamped and Cascaded H-bridg...ijeei-iaes
This paper presents a concept of two types multilevel inverters such as diode clamped and cascaded H-bridge for harmonic reduction on high power applications. Normally, multilevel inverters can be used to reduce the harmonic problems in electrical distribution systems. This paer focused on the performance and analysis of a three phase seven level inverter including diode clamped and cascaded H-bridge based on new tripizodal triangular space vector PWM technique approaches. TTMC based modified Space vector Pulse width modulation technique so called tripizodal triangular Space vector Pulse width modulation (TTMC-SVPWM) technique. In this paper the reference sine wave generated as in case of conventional off set injected SVPWM technique. It is observed that the TTMC-Space vector pulse width modulation ensures excellent, close to optimized pulse distribution results and THD is compared to seven level, diode clamped and cascaded multi level inverters. Theoretical investigations were confirmed by the digital simulations using MATLAB/SIMULINK software.
A Review of Matrix Converter and Novel Control Method of DC-AC Matrix Converteridescitation
For the past three decades, research work in matrix
converter has increased much. This paper presents a new
topology of DC-AC matrix converter, starting with a brief
historical review of different modulation and control strategies
which was developed recently. The purpose of the Paper is to
generate a multilevel output voltage equal to multilevel
inverter with reduced switches. An important part of the paper
is to design a dedicated DC-AC matrix converter and some
new arrays of bidirectional switches in a single module are
also presented. To find the performance of the module the
entire module is designed with MATLAB simulation and tested
with three phase induction motor.
International Journal of Engineering Research and Development (IJERD)IJERD Editor
journal publishing, how to publish research paper, Call For research paper, international journal, publishing a paper, IJERD, journal of science and technology, how to get a research paper published, publishing a paper, publishing of journal, publishing of research paper, reserach and review articles, IJERD Journal, How to publish your research paper, publish research paper, open access engineering journal, Engineering journal, Mathemetics journal, Physics journal, Chemistry journal, Computer Engineering, Computer Science journal, how to submit your paper, peer reviw journal, indexed journal, reserach and review articles, engineering journal, www.ijerd.com, research journals,
yahoo journals, bing journals, International Journal of Engineering Research and Development, google journals, hard copy of journal
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
STATCOM is one of the shunt type FACTS controllers which can supply reactive power and improve bus voltage. STATCOM, a controlling device used on alternating current transmission networks, has advantages like transient free switching and smooth variation of reactive power. This paper proposes a cascaded multilevel inverter type DSTATCOM and DVR to compensate voltage sag in utilities in power distribution network. The proposed DSTATCOM is implemented using multilevel topology with isolated dc energy storage and reduced number of switches. A DVR injects a voltage in series with the system voltage and a D-STATCOM implant a current into the system to correct the voltage sag, swell and interruption. The phase shifter PWM technique is described to generate firing pulse to cascaded inverter. The proposed neuro-fuzzy controller follow itself to the sag and provides effective means of mitigation. The voltage sag with the minimum harmonic at the efficacy end. The proposed technique is simulated using MATLAB/Simulink.
This paper presents a real-time emulator of a dual permanent magnet synchronous motor (PMSM) drive implemented on a field-programmable gate array (FPGA) board for supervision and observation purposes. In order to increase the reliability of the drive, a sensorless speed control method is proposed. This method allows replacing the physical sensor while guaranteeing a satisfactory operation even in faulty conditions. The novelty of the proposed approach consists of an FPGA implementation of an emulator to control the actual system. Hence, this emulator operates in real-time with actual system control in healthy or faulty mode. It gives an observation of the speed rotation in case of fault for the sake of continuity of service. The observation of the rotor position and the speed are achieved using the dSPACE DS52030D digital platform with a digital signal processor (DSP) associated with a Xilinx FPGA.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Analysis and Implementation of Unipolar PWM Strategies for Three Phase Cascad...IJAAS Team
This paper presents unipolar pulse width modulation technique with sinusoidal sampling pulse width modulation are analyzed for three-phase five-level, seven-level, nine-level and eleven-level cascaded multi-level inverter. The unipolar PWM method offers a good opportunity for the realization of the Three-phase inverter control, it is better to use the unipolar PWM method with single carrier wave compared to two reference waves. In such case the motor harmonic losses will be considerably lower.The necessary calculations for generation of unipolar pulse width modulation strategies have presented in detail. The unipolar SPWM voltage switching scheme is selected in this paper because this method offers the advantages of effectively doubling the switching frequency of the inverter voltage. The cascaded multi level inverter fed induction motor is simulated and compared the total harmonic distroction for all level (five-level, seven-level, nine-level and elevel-level)of the inverter. Theoretical investigations were confirmed by the digital simulations using MATLAB/SIMULINK software.
Optimal Body Biasing Technique for CMOS Tapered Buffer IJEEE
This paper represents Fixed Body Biased CMOS Tapered Buffer which is designed to minimize the average power dissipation across large capacitive load. The implementation of Reverse Body Bias (RBB) in the proposed Buffer chain is to vary Vth value of NMOS in the first stage. And with the increase in Vth /sub-threshold leakage current and power has been reduced. The technology constraints on the threshold voltage does not allow designer to set high threshold voltage for MOS devices. Hence, this was found that in proposed circuit that when optimal Reverse Body Bias value is set within (0.2 VDD to 0.4 VDD) range, the average power dissipation across capacitive load reduces to 82.2 % at very less penalty in delay. Thus CMOS buffer designers can use the proposed method to vary Vth while keeping VDD constant, which could improve the performance parameters of Tapered Buffer. The proposed analysis is verified by simulating the 3-stage tapered buffer schematics using standard 180nm CMOS technology in Cadence environment.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
The pulse generator which has been implemented in the pulse electric field (PEF) treatment system for food processing is worth to be highlighted and improved. It is parallel with the advancement in semiconductor technology, which offers robust and accurate devices. This research is an effort to produce a low cost, compact and reliable pulse generator as well as equipped with a pulse width modulation (PWM) method for wide selection of frequency and duty cycle. The result shows that the simulation process has proven the theoretical concept to be right and yields the desired outcome based on the designed values. Then, the actual printed circuit board (PCB) has been fabricated to obtain practical results which intended to be compared with the simulation outcomes. Concerning the frequency and its duty cycle, both parameters can be altered without affecting each other. It means by changing the frequency, duty cycle remains the same and vice versa. Thus, this proposed pulse generator achieves its objective and fits to be implemented in PEF treatment technology. It also can replace the conventional pulse forming network (PFN) which is bulky and costly.
Limitations of DC injection into the AC network is an important operational requirement for grid connected photovoltaic systems. There is one way to ensure that this issue needs a power transformer as a connection to the AC network. However, this solution adds cost, volume, mass, and power losses. Ideally there shouldn't be any DC at the output of the inverter, but practically, a small amount of DC current is present. Therefore, in this paper there are techniques for the DC offset elimination are proposed. Some have drawbacks which was treated by another technique. Also there are best solutions for eliminating DC offset as in section 17, and 18 as it explains how to reduce the DC offset in a transformerless operation with reducing the power losses, mass and the cost effect.
Development of Digital Controller for DC-DC Buck ConverterIJPEDS-IAES
This paper presents a design & implementation of 3P3Z (3-pole 3-zero)
digital controller based on DSC (Digital Signal Controller) for low voltage
synchronous Buck Converter. The proposed control involves one voltage
control loop. Analog Type-3 controller is designed for Buck Converter using
standard frequency response techniques.Type-3 analog controller transforms
to 3P3Z controller in discrete domain.Matlab/Simulink model of the Buck
Converter with digital controller is developed. Simualtion results for steady
Keyword: state response and load transient response is tested using the model.
An improved design of CMOS dynamic latch comparator with dual input dual output with a simple
design of three stages is represented. The basic disadvantages of latch type comparators are overcome by
producing an edge triggered comparison. The circuit is designed for a resolution of 300nV and the power
consumption is reduced to 450uW. It is designed for 1.8V DC supply voltage and 1 MHz clock frequency for
PVT variations. The simulation of the comparator is done in Cadence® Virtuoso Analog Design Environment
using 180nm technology. The error quotient is reduced less than 5% by adding a buffer stage. The delay is
brought down to 5nS. The active area appreciably is reduced. Layout of the proposed comparator has been
simulated in Cadence® Virtuoso Layout XL Design Environment. DRC and LVS have been verified.
In this paper, a new topology of Adaptive Hysteresis Band controller for Boost & Buck converter has been proposed, modeled and analyzed. The difficulties caused in Hysteresis Band (HB) controlled dc-dc converter have been eliminated using Adaptive Hysteresis Band (AHB) controller. This novel control topology can be able to maintain the switching frequency constant unlike HB controller. Thus the filter design for the converters will become easier with this controller. Again this control methodology is a robust one as it depends upon the system parameters where there was no possibility with HB controller. The Mathematical modeling of the controller is shown in this paper, further this has been simulated using Matlab /SIMULINK to generate pulse. The steady state analysis to find the parameters and the stability condition of the converter using the dynamic behavior is also portrayed in this paper. The simulation for a Boost and a Buck converter is also shown separately using AHB controller.
A 20 gbs injection locked clock and data recovery circuitVLSICS Design
This paper presents a 20 Gb/s injection-locked clock and data recovery (CDR) circuit for burst mode
applications. Utilizing a half rate injection-locked oscillator (ILO) in the proposed CDR circuit leads to
higher speed operation and lower power consumption. In addition, to accommodate process, voltage, and
temperature (PVT) variations and to increase the lock range, a frequency locked loop is proposed to use in
this circuit. The circuit is designed in 0.18 μm CMOS and the simulations for 27-1 pseudo random bit
sequence (PRBS) show that the circuit consumes 55.3 mW at 20 Gb/s, while the recovered clock rms jitter
is 1.1 ps
A DAPTIVE S UPPLY V OLTAGE M ANAGEMENT F OR L OW P OWER L OGIC C IRCU...VLSICS Design
With the rise in demand of portable hand held devic
es and with the rise in application of wireless sen
sor
networks and RFID reduction of total power consumpt
ion has become a necessity. To save power we
operate the logic circuitry of our devices at sub-t
hreshold. In sub-threshold the drain current is
exponentially dependent on the threshold voltage he
nce the threshold variation causes profound variati
on
of I
ON
and I
OFF
the ratio of which affect the speed of a circuit d
rastically. So to mitigate this problem we
present a adaptive power management circuit which w
ill determine the minimum required supply voltage
to meet the timing requirement. Also to reduce the
power overhead and avoid bulky coil and EMI noise
we used the switch capacitor power regulator to reg
ulate and manage power instead of linear dropout
(LDO) and Inductor base switch mode power converter
ADAPTIVE BANDWIDTH APPROACH ON DTC CONTROLLED INDUCTION MOTORijcisjournal
Induction motors are most commonly used motor type in industrial applications because of its well-known advantages like robust structure, cheaper prices etc. Today, field oriented control (FOC) and direct torque control (DTC) methods, also called vector control, are most famous control methods in high-performance applications. The main structural and behavioural differences between the both methods can be summarized as: the FOC has parameter dependence while the DTC has high torque ripples. In this study, a new adaptive bandwidth approach was presented to reduce torque ripples in DTC controlled induction motor drives. With the proposed method, instead of fixed bandwidth, adaptive bandwidth approach was investigated in hysteresis controllers on the DTC method. Both the conventional DTC(C-DTC) method and adaptive bandwidth DTC (AB-DTC) for induction motor were simulated in MATLAB/SIMULINK and the results were presented and discussed to verify the proposed control. The comparisons shown that, torque ripples were reduced remarkably with the proposed AB-DTC method.
ADAPTIVE BANDWIDTH APPROACH ON DTC CONTROLLED INDUCTION MOTORijics
Induction motors are most commonly used motor type in industrial applications because of its well-known
advantages like robust structure, cheaper prices etc. Today, field oriented control (FOC) and direct torque
control (DTC) methods, also called vector control, are most famous control methods in high-performance
applications. The main structural and behavioural differences between the both methods can be
summarized as: the FOC has parameter dependence while the DTC has high torque ripples. In this study, a
new adaptive bandwidth approach was presented to reduce torque ripples in DTC controlled induction
motor drives. With the proposed method, instead of fixed bandwidth, adaptive bandwidth approach was
investigated in hysteresis controllers on the DTC method. Both the conventional DTC(C-DTC) method and
adaptive bandwidth DTC (AB-DTC) for induction motor were simulated in MATLAB/SIMULINK and the
results were presented and discussed to verify the proposed control. The comparisons shown that, torque
ripples were reduced remarkably with the proposed AB-DTC method.
T ORQUE R IPPLES M INIMIZATION ON DTC C ONTROLLED I NDUCTION M OTOR WITH A DA...csandit
Field oriented control (FOC) and direct torque cont
rol (DTC), also called vector control, are
most famous control methods in high-performance mot
or applications. If we want to specify the
basic handicaps of both methods: the FOC has parame
ter dependence while the DTC has high
torque ripples. This paper proposes a new adaptive
bandwidth approach to reduce torque
ripples in DTC controlled induction motor drives. W
ith the proposed method, instead of fixed
bandwidth, adaptive bandwidth approach is investiga
ted in hysteresis controllers on the DTC
method. Both the conventional DTC(C-DTC) method and
adaptive bandwidth DTC (AB-DTC)
for induction motor are simulated in MATLAB/SIMULIN
K and the results are presented and
discussed to verify the proposed control. The compa
risons have shown that, torque ripples have
been reduced remarkably with the proposed AB-DTC me
thod.
The aim of this paper is to control the speed of DC motor. The main advantage in using a DC
motor is that the Speed-Torque relationship can be varied to almost any useful form. To achieve the
speed control an electronic technique called Pulse Width Modulation is used which generates High and
Low pulses. These pulses vary the speed in the motor. For the generation of these pulses a
microcontroller (AT89c51) is used. As a microcontroller is used to set the speed ranges which is done by
changing the duty cycles time period in the program. This is practical and highly feasible in economic
point of view, and has an advantage of running motors of higher ratings. This paper gives a reliable,
durable, accurate and efficient way of speed control of a DC motor.
A power efficient delta-sigma ADC with series-bilinear switch capacitor volta...TELKOMNIKA JOURNAL
In low-power VLSI design applications non-linearity and harmonics are a major dominant factor which affects the performance of the ADC. To avoid this, the new architecture of voltage-controlled oscillator (VCO) was required to solve the non-linearity issues and harmonic distortion. In this work, a 12-bit, 200MS/s low power delta-sigma analog to digital converter (ADC) VCO based quantizer was designed using switched capacitor technique. The proposed technique uses frequency to current conversion technique as a linearization method to reduce the non-linearity issue. Simulation result show that the proposed 12-bit delta-sigma ADC consumes the power of 2.68 mW and a total area of 0.09 mm² in 90 nm CMOS process.
OPTIMAL TORQUE RIPPLE CONTROL OF ASYNCHRONOUS DRIVE USING INTELLIGENT CONTROL...elelijjournal
The dynamic performance of an asynchronous machine when operated with cascaded Voltage Source Inverter using Space Vector Modulation (SVM) technique is presented in this paper. A classical model of Induction Motor Drive based on Direct Torque Control (DTC) method is considered which displays
appreciable run-time operation with very simple hysteresis control scheme. Direct control of the torque and flux variables is achieved by choosing suitable inverter voltage space vector from a lookup table. Under varying torque conditions the performance of the drive system is verified using MATLAB/Simulink software tool. The ripple content in the torque parameter is significant when traditional PI controller and Fuzzy approach are configured in the proposed system. Finally, by replacing the PI-Fuzzy controller with Hybrid Controller the torque ripple minimization can be achieved during no-load and loaded conditions.
This paper proposes a single-bit ADC system based Proportional and Integral (PI) controller to maintain a desired level of power transfer efficiency in Capacitive Power Transfer (CPT) systems. In this paper, a simple single-bit ADC system i.e., Single-Bit Modulator (SBM) is considered as an alternative to the commonly used multi-bit ADC systems. Unique features of employing SBM are 1) its ability to convert analog signals into single-bit signals and 2) its easy integrability in digital chips with linear variable differential transformers (LVDTs) such as FPGAs. A SBM based PI (SBM-PI) controller is designed to judicially interface with the single-bit output of SBM. The proposed (SBM-PI) controller guarantees less hardware resources, latency and regulates the output voltage to provide the desired power transfer efficiency. The behavior of SBM-PI controller is compared to that of a conventional multi-bit controller, with the results of both controllers being identical. The effectiveness of the proposed controller with SBM is further demonstrated using the experimental prototype of CPT by implementing a SBM-PI controller using $16$ MHz ATmega8 microcontroller. The experimental results from a laboratory prototype illustrate that SBM-PI controller successfully regulates the output voltage of CPT to control the power flow.
The French Revolution, which began in 1789, was a period of radical social and political upheaval in France. It marked the decline of absolute monarchies, the rise of secular and democratic republics, and the eventual rise of Napoleon Bonaparte. This revolutionary period is crucial in understanding the transition from feudalism to modernity in Europe.
For more information, visit-www.vavaclasses.com
Synthetic Fiber Construction in lab .pptxPavel ( NSTU)
Synthetic fiber production is a fascinating and complex field that blends chemistry, engineering, and environmental science. By understanding these aspects, students can gain a comprehensive view of synthetic fiber production, its impact on society and the environment, and the potential for future innovations. Synthetic fibers play a crucial role in modern society, impacting various aspects of daily life, industry, and the environment. ynthetic fibers are integral to modern life, offering a range of benefits from cost-effectiveness and versatility to innovative applications and performance characteristics. While they pose environmental challenges, ongoing research and development aim to create more sustainable and eco-friendly alternatives. Understanding the importance of synthetic fibers helps in appreciating their role in the economy, industry, and daily life, while also emphasizing the need for sustainable practices and innovation.
Read| The latest issue of The Challenger is here! We are thrilled to announce that our school paper has qualified for the NATIONAL SCHOOLS PRESS CONFERENCE (NSPC) 2024. Thank you for your unwavering support and trust. Dive into the stories that made us stand out!
2024.06.01 Introducing a competency framework for languag learning materials ...Sandy Millin
http://sandymillin.wordpress.com/iateflwebinar2024
Published classroom materials form the basis of syllabuses, drive teacher professional development, and have a potentially huge influence on learners, teachers and education systems. All teachers also create their own materials, whether a few sentences on a blackboard, a highly-structured fully-realised online course, or anything in between. Despite this, the knowledge and skills needed to create effective language learning materials are rarely part of teacher training, and are mostly learnt by trial and error.
Knowledge and skills frameworks, generally called competency frameworks, for ELT teachers, trainers and managers have existed for a few years now. However, until I created one for my MA dissertation, there wasn’t one drawing together what we need to know and do to be able to effectively produce language learning materials.
This webinar will introduce you to my framework, highlighting the key competencies I identified from my research. It will also show how anybody involved in language teaching (any language, not just English!), teacher training, managing schools or developing language learning materials can benefit from using the framework.
June 3, 2024 Anti-Semitism Letter Sent to MIT President Kornbluth and MIT Cor...Levi Shapiro
Letter from the Congress of the United States regarding Anti-Semitism sent June 3rd to MIT President Sally Kornbluth, MIT Corp Chair, Mark Gorenberg
Dear Dr. Kornbluth and Mr. Gorenberg,
The US House of Representatives is deeply concerned by ongoing and pervasive acts of antisemitic
harassment and intimidation at the Massachusetts Institute of Technology (MIT). Failing to act decisively to ensure a safe learning environment for all students would be a grave dereliction of your responsibilities as President of MIT and Chair of the MIT Corporation.
This Congress will not stand idly by and allow an environment hostile to Jewish students to persist. The House believes that your institution is in violation of Title VI of the Civil Rights Act, and the inability or
unwillingness to rectify this violation through action requires accountability.
Postsecondary education is a unique opportunity for students to learn and have their ideas and beliefs challenged. However, universities receiving hundreds of millions of federal funds annually have denied
students that opportunity and have been hijacked to become venues for the promotion of terrorism, antisemitic harassment and intimidation, unlawful encampments, and in some cases, assaults and riots.
The House of Representatives will not countenance the use of federal funds to indoctrinate students into hateful, antisemitic, anti-American supporters of terrorism. Investigations into campus antisemitism by the Committee on Education and the Workforce and the Committee on Ways and Means have been expanded into a Congress-wide probe across all relevant jurisdictions to address this national crisis. The undersigned Committees will conduct oversight into the use of federal funds at MIT and its learning environment under authorities granted to each Committee.
• The Committee on Education and the Workforce has been investigating your institution since December 7, 2023. The Committee has broad jurisdiction over postsecondary education, including its compliance with Title VI of the Civil Rights Act, campus safety concerns over disruptions to the learning environment, and the awarding of federal student aid under the Higher Education Act.
• The Committee on Oversight and Accountability is investigating the sources of funding and other support flowing to groups espousing pro-Hamas propaganda and engaged in antisemitic harassment and intimidation of students. The Committee on Oversight and Accountability is the principal oversight committee of the US House of Representatives and has broad authority to investigate “any matter” at “any time” under House Rule X.
• The Committee on Ways and Means has been investigating several universities since November 15, 2023, when the Committee held a hearing entitled From Ivory Towers to Dark Corners: Investigating the Nexus Between Antisemitism, Tax-Exempt Universities, and Terror Financing. The Committee followed the hearing with letters to those institutions on January 10, 202
Biological screening of herbal drugs: Introduction and Need for
Phyto-Pharmacological Screening, New Strategies for evaluating
Natural Products, In vitro evaluation techniques for Antioxidants, Antimicrobial and Anticancer drugs. In vivo evaluation techniques
for Anti-inflammatory, Antiulcer, Anticancer, Wound healing, Antidiabetic, Hepatoprotective, Cardio protective, Diuretics and
Antifertility, Toxicity studies as per OECD guidelines
International Journal of VLSI design & Communication Systems (VLSICS)
1. International Journal of VLSI design & Communication Systems (VLSICS) Vol.10, No.3, June 2019
DOI : 10.5121/vlsic.2019.10301 1
DUTY CYCLE CORRECTOR USING PULSE WIDTH
MODULATION
Meghana Patil1
, Dr. Kiran Bailey2
and Rajanikanth Anuvanahally3
1
Department of Electronics and Communication, BMSCE, Bengaluru, Karnataka, India
2
Department of Electronics and Communication, BMSCE, Bengaluru, Karnataka, India
3
Senior Member IEEE, Bengaluru, Karnataka, India
ABSTRACT
In circuits, clocks usually play a very important role. Whenever data needs to be sampled, it is done with
respect to clock signals. It uses the edges of the clock to sample the data. So, it becomes very much
necessary to see to it that the clock signals are properly received specially in receiver circuits where data
sampling is done, mainly in Double data rate(DDR) circuits. Due to effects such as jitter, skew,
interference, device mismatches etc., duty cycle gets affected. We come up with duty cycle correctors that
ensure 50% duty cycle of the clock signals. A duty cycle corrector (DCC) with analog feedback is proposed
and simulated in 45nm process technology node. The duty cycle corrector operates for MHz frequency
range covering the duty cycle from 35%-65%, with +/- 1.5% accuracy. The design is simple and the power
consumption is 1.01mW.
KEYWORDS
DCC, Integrator, Control voltage generator, frequency range
1. INTRODUCTION
Double data rate synchronous dynamic random access memory (DDR SDRAM), makes higher
data rate possible making strict control of timing on electrical data and clock signals. Duty cycle
distortion is an important specification to be considered when there is minimum and maximum
constraint on pulse width. One such situation is when the signal has to be sampled by clock at the
receiver, during the valid data window. In such a situation, it has to be ensured that the data signal
is wide enough to be sampled in the valid data window range to avoid distortions. Hence Duty
Cycle Correctors (DCCs) come into picture for the purpose to correct the distorted clock signal
and adjust the pulsewidth to 50%. These are of many types.
2. RELATED WORK
In [1], the paper is the combination of both analog and digital circuits, i.e it’s a mixed mode
technique for duty cycle correction. It uses a dual feedback loop. This design works at very high
frequencies with clock jitter of around 1.62ps. It also has an accuracy rate of +/- 1%. It works on
the principle of adjusting the rise and fall time of the input clock which is dependent on pull up
and pull down strength of the inverter. It includes two types of correction, the first is course
correction which is controlled by binary code finite state machine (FSM) which corrects the duty
cycle to maximum extent by incrementing or decrementing the code that enable the inverter
ladder leading to increase or decrease in the rise or fall time. Second is fine correction done by
thermal code which starts working after binary duty cycle adjuster has stopped working. The
advantage of this work is its good accuracy but has minimum duty cycle correction range i.e from
40-60%.Power consumption is also huge which is around 5.87mW due to its complex structure.
2. International Journal of VLSI design & Communication Systems (VLSICS) Vol.10, No.3, June 2019
2
In [2], duty cycle corrector is being designed for applications such as software defined radios,
cognitive radios etc. it uses a technique called pulsewidth modification to make the circuit to
operate over a wide frequency range of 100Mhz-3.5Ghz. It makes use of an inverter whose drive
strength is varied by current sources that are connected to the output. This leads to variation in the
rise and fall times that are rectified by the comparator and then fed back in the loop leading to
variation in the pulsewidth. This work is proved useful in terms of wide correction range of 30-
70% but has huge power consumption of 20mW(including load). In [3], the paper investigates
different implementation of DCC. This paper mainly highlights the pros and cons of different
architectures. It claims that an analog DCC can provide wide correction range and shows little
sensitivity to power supply variation in comparison to digital DCC. It also gives some key points
on implementation of DCC with and without Delay locked loop(DLL). In [4], the proposed
circuit calibrates the duty cycle to reduce the introduced jitter. It is an all analog feedback DCC
that includes an differential amplifier to detect the duty cycle and corrects it in the loop till it
nears 50%. The design scheme is robust to the process and temperature variations.1-5 GHz of
correctionrange is achieved using 1.2V of supply and 3.5 mW of power consumption and very
less die area. In [5], successive approximation register (SAR) based DCC is being proposed that
uses a binary search algorithm to achieve fast correction of duty cycle and to support the power
down mode. 6 bit SAR controller is being used along with an amplifier used for detection. The
proposed architecture is prone to PVT variations and may suffer from noise etc. Power
consumption is 3.2mW. In [6], an all digital duty cycle corrector is being presented. This
architecture uses a time to digital converter, that acts as a duty cycle detector. It needs a DLL to
align the phase skew between input and output clock. It consumes 5.6mW of power which is its
drawback. In [7], an analog feedback DCC is being designed for 1-660Mhz. They have made
used of pulse shrinking and stretching mechanism. In [8], an analog feedback DCC is proposed
that works at 1.8V supply and corrects duty cycle from 1M -900Mhz. [9] focuses at DCC that
works only at 1-2Ghz, not making it reliable for applications that work at MHz frequencies. It has
two stages, where the first stage consists of two amplifiers restricted to correct the duty cycle in
between 47-53% by intentionally skewing their references to 47 and 53% of VDD(supply). The
second stage has an amplifier that does fine tuning to 50%. The motivation behind this work was,
usage of single stage amplifier requires large gain making it sensitive to VDD, hence the author
proposed this two stage structure. In [11], a synchronous all digital DCC is presented. It uses dual
loop feedback, one corrects the duty cycle and other corrects the skew between input and output
clock. It is limited to work between 300-600MHz with duty cycle correction range of 40-60%
with huge power consumption of 18mW. In [12], proposed DCC attains the duty cycle of near to
50% for single ended signal. It uses an inverter where input clock is given to the gate of pmos and
error voltage that comes from comparator is given to gate of nmos, as duty cycle corrector. But it
works only at 500MHz signal. In [13], DLL is proposed along with DCC using feedback edge
combiner. Here the main focus is on architectures used on SDRAMs that has DLL included to
increase the data rate of the channel. It has 7.2mW of power consumption. In [14], a ring
oscillator is used as duty cycle detector, that measures the average frequency by counting the
number of oscillations in fixed time period. If upcount is less than downcount, duty cycle is less
than 50 and vice-versa. Hence the control bits in duty cycle adjuster are incremented or
decremented to achieve 50%. Thus, from all these papers it can be summarised that majority of
architectures use inverter stages for duty cycle correction and amplifiers to detect the duty cycle
and compare them, the difference in architecture depends on what kind of configuration or
method is used to correct the duty cycle in loop, where digital DCCs use FSM, SAR, or TDC that
increment or decrement the code and feed it to the inverter ladder to change the rise/fall time and
analog DCCs make use of amplifiers that generate the control voltage given to the gate of nmos
and pmos to vary the charging and discharging current which in turn affects the dutycycle.
3. International Journal of VLSI design & Communication Systems (VLSICS) Vol.10, No.3, June 2019
3
3. CIRCUIT IMPLEMENTATION
The proposed DCC is an analog feedback duty cycle corrector. In the top level, there are three
blocks namely duty cycle corrector that corrects the pulsewidth, duty cycle detector which detects
the duty cycle error and the third block is the control voltage generator that generates the control
voltage based on the error till pulsewidth reaches 50% . Figure 1 shows the top level block
diagram, the input distorted clock is fed to the duty cycle corrector, and it travels through the duty
cycle detector and feedback control voltage generator till it gives out the corrected output clock
that is close to 50%.
Figure 1 : DCC top level block diagram
3.1. DUTY CYCLE CORRECTOR
The first part in the top level circuit consists of a duty cycle corrector, which is nothing but the
series of modified inverters that act as pulsewidth modification cells. One way to control the
pulsewidth is by adding the extra two transistors to an inverter as shown in the Figure 2. This
method is known as “current starving” [7]. The main purpose here is to increase or decrease the
pulse width of a clock. This can be achieved by varying the rise / fall time and then using a
regular inverter to sharpen the edge so that the clock edges are shifted, hence changing the pulse
width.
When the control voltage (refer to first stage of Figure 2) decreases (below the midpoint, ~vdd/2),
the fall time increases – since VGS of nmos transistor is lowered and risetime reduces as VGS of
pmos increases (refer to Figure 7 for rise time and fall time curves) [7]. The increase in fall time
(Tf) moves the vdd/2 transition point of the falling edge to delayed time and decrease in rise time
(Tr) moves the vdd/2 transition point of the rising edge the left. The second stage is an inverter,
designed with Voltage threshold equal to vdd/2. Since we varied the midpoint of rising and
falling edges from the first stage (Figure 2) the mid point appears at different point of time and
since the second inverter switches at this new point of time moving the falling edge to right and
rising edge slightly to left. This in effect decrease the pulsewidth of the clock coming out of this
block. In the similar way the pulsewidth gets expanded when the Vctrl increases. The gate
voltages of nmos and pmos are being generated by control voltage generator discussed later.
Change in width ΔW = thigh_low - tlow_high as shown in the Figure 3.
Modelling of delay cell:
The sizes of the mosfets MPS and MNS are chosen to provide equal rise and fall time at the mid
value (~vdd/2) of the control voltage to balance the pulse shrink and stretch mechanism. The
4. International Journal of VLSI design & Communication Systems (VLSICS) Vol.10, No.3, June 2019
4
sizing for these is such that at this control voltage, inverter made of MP1 and MP2 should starve
i.e carry lesser current than they are capable of for their sizes.
Figure 2: Schematic for delay cell/DCC
Figure 3. Change in pulse width ΔW = thigh_low - tlow_high
Figure 4 shows the shift in edges of the clock as the control voltage changes from 0.7V to 1.1V
leading to change in rise and fall times and hence the pulsewidth as explained before and from
Figure 5 it can be observed that the proposed duty cycle inverter works well between 0.7-1.2 V of
5. International Journal of VLSI design & Communication Systems (VLSICS) Vol.10, No.3, June 2019
5
Vctrl changing the duty cycle from 31.51% to 83.6%. Figure 5 is plot on how much duty cycle is
achieved corresponding to the applied Vctrl when no load is considered.
Figure 4. Shift in the edges of clock
Figure 5. Variation in duty cycle with respect to control voltage.
6. International Journal of VLSI design & Communication Systems (VLSICS) Vol.10, No.3, June 2019
6
Figure 6. Vctrl Vs. Duty cycle
Figure 7. Rise and Fall time with respect to Vctrl
Figure 6 shows the graph for Vctrl Vs. Duty cycle. With increase in Vctrl, the current in MPS (
and MP1) decreases leading to increase in charging time and increase the rise time at node ‘S’.
This leads to falling edge (looking at vout, the output node of second stage) moving to the right
and thereby increasing the pulse width and hence increases the duty cycle. Figure 7 shows the rise
7. International Journal of VLSI design & Communication Systems (VLSICS) Vol.10, No.3, June 2019
7
and fall time variation with respect to Vctrl. As can be seen from the Figure 7, they vary in
opposite direction.
3.2. DUTY CYCLE DETECTOR
The passive integrator is one made of resistors and capacitors. The resistors consume very large
area compared to transistors, active integrator can be much faster specially for high speed pulse
inputs, whereas passive integrator that is made only of RC filter might become huge load and
high speed circuits may not be able to drive it. Passive integrators also take longer time to settle.
Hence we used an active integrator in our design. This configuration (Figure 8) below uses non-
feedback way of controlling the output common mode. Figure 9 shows the averaged output
waveforms of the integrator when the input clocks with duty cycle of 35-65% are being fed.
Figure 8. Integrator schematic
Figure 9. Output of integrator for different input duty cycles
8. International Journal of VLSI design & Communication Systems (VLSICS) Vol.10, No.3, June 2019
8
Figure 10. Pivot for integrator Output
The figure 10 shows outputs of the active integrator which are the averaged out values for
corresponding two clocks. The plot shows how the average value changes as the input duty cycle
changes.
3.3. CONTROL VOLTAGE GENERATOR
Finally, the analog differential voltage given by integrator is given as input to an amplifier where
it gets amplified to generate a control voltage which varies the pulse width of the clock by
increasing and decreasing the rise and fall times of the clock. The feedback going out from this
stage to the corrector stage needs to be DC and should be within the voltage range for which DCC
works. We need common mode feedback stage to stabilise the output common mode of this
amplifier. We also need to have sufficient capacitance at its output node since the voltage we are
feeding back to first stage is DC for abrupt changes in these feedback voltages. Here Common
mode feedback based differential amplifier is used as shown in Figure 11. [2] [8]
Figure 11. Circuit of CMFB
9. International Journal of VLSI design & Communication Systems (VLSICS) Vol.10, No.3, June 2019
9
Design of differential amplifier:
ID=Drain current, μnCox=51.7u, μpCox=34.7u, Supply Voltage=1.8V
Vgs= Gate-source voltage, Vth=Threshold voltage=0.4V, Overdrive voltage= 0.2V
ID = ½ μnCox(W/L)(Vgs-Vth)2
100u=1/2 (51.7u)(W/L)5,6(0.2)2
(W/L)5,6=5
Vgs-Vth= 0.2V, Vgs
=0.2+0.4=0.6V
Vg=1.4V
Av=gm (ro2||ro4)
10=gm(62.5K||62.5K)
gm=0.32m
gm=(2ID μnCox(W/L) )1/2
(W/L)1,2=4
ID = ½ μpCox(W/L)(Vgs-Vth
)2
(W/L)3,4=1
Figure 12. Implemented Schematic
Working of the circuit.
• The integrator produces two signals corresponding to the average of the two complementary
input clocks. These signals are fed to the amplifier.
• This stage produces the output proportional to the difference of input voltages.
• The output of the amplifier are the control voltages that are fed back to duty cycle corrector
to change the pulse width of the clock till it reaches close to 50%.
10. International Journal of VLSI design & Communication Systems (VLSICS) Vol.10, No.3, June 2019
10
Figure 13. Transient response of the amplifier
Figure 12 shows the implemented schematic and Figure 13 shows the transient response, initially
the circuit was designed to have 20dB of gain, and when it was implemented in the top level
where the load and other things come into picture, the designed was modified accordingly with
respect to the size of mos devices. At final stage the amplifier was able to provide gain of 31.2dB
as shown in the figure 14. All these circuits till now were simulated independently by giving the
ideal inputs. In the next section all these are combined to get the top level architecture where the
circuit works in a loop and behaviour of this structure is discussed in the next section.
Figure 14. Gain of the amplifier in dB.
3.4. TOP LEVEL IMPLEMENTATION
This section covers the top level implementation of the duty cycle corrector, where all the above
three blocks are brought together, the two complementary clocks are fed as input to corrector
stage. The number of corrector stages required depends on the frequency of the clock (and the
gain of the corrector stage) and we used four such stages in our design. Output of delay stages are
fed to the integrator that averages the two values from two clocks and fed to differential amplifier
that generates the control voltage which is fed back to the delay stages and process continues till
the voltages became same and loop is stabilised as shown in Figure 15. This circuit works at
frequency range of 1Mhz to 900Mhz, correcting duty cycle in the range of 35%-65%. The
11. International Journal of VLSI design & Communication Systems (VLSICS) Vol.10, No.3, June 2019
11
correction accuracy is dependent on the gain of the amplifier, the correction frequency range is
dependent on the settling time of the integrator.
Figure 15. Top level schematic
The circuit is simulated from 35%-65% of duty cycle at 250Mhz, and the output variation can be
seen in the Figure 16 below. Ip and In indicate the averaged out values of the two clocks at the
integrator output. Vp and Vn denote the control voltage value generated by the last stage that is
the amplifier. The loop works until the two values at the integrator output becomes equal, there
the value gets settled as can be seen in the Figure 16 below. As you can see in the figure below
the integrator value is settled to 1.19V and loop continues to be stable. We can observe how the
control voltage is changing in order to vary the pulsewidth of the clock. The Figure 16 shows the
variation in the duty cycle for 35% and 65% input respectively where we can see the 35% settles
to 50.16% and 65% settles to 48.65%. In Figure 17, dc_p denotes output for 35% input dc_n
denotes output for 65% input. Figure 18-20 shows the output duty cycle variation when input is
40%,45%,50%,55%,60% and it is observed that the corrected duty cycle is 50.22, 49.84, 49.4,
49.57 and 48.65 respectively and it is also observed that at the beginning the duty cycle fluctuates
up and down during the process of correcting and once it reaches the maximum extent to which it
can correct, it becomes stable and constant later.
12. International Journal of VLSI design & Communication Systems (VLSICS) Vol.10, No.3, June 2019
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Figure 16. Output waveforms
Figure 17. Duty cycle output variation for input of 35% and 65%
13. International Journal of VLSI design & Communication Systems (VLSICS) Vol.10, No.3, June 2019
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Figure 18. Duty cycle output variation for input of 40% and 60%
Figure 19. Duty cycle output variation for input of 45% and 55%
14. International Journal of VLSI design & Communication Systems (VLSICS) Vol.10, No.3, June 2019
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Figure 20. Duty cycle output variation for input of 50%
Figure 21. Input Vs. Output duty cycle variation
Above graph in Figure 21 shows the output duty cycle Vs input duty cycle for inputs varying
from 35%-65% simulated at 250Mhz, and as it is observed accuracy is within 1.5%. Table 1
contains the summary of the output values at each stage at the end of simulation for different
input duty cycles.
15. International Journal of VLSI design & Communication Systems (VLSICS) Vol.10, No.3, June 2019
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Input duty
cycle(%)
Integrator
Output(V)
Control
voltage(v)
Output duty
cycle(%)
Rise time
(ps)
Fall time
(ps)
35 1.19 828.5m 50.16 150.74 177.75
40 1.192 852m 50.22 157.76 171.38
45 1.194 875.7m 49.84 171.68 145.57
50 1.194 906m 49.4 178.4 144.9
55 1.194 936.2m 49.57 194.26 137.6
60 1.192 958.2m 48.65 201.65 124.92
65 1.19 982.7m 48.6 226.6 115.92
Table 1. Parameter analysis
Power of the circuit is calculated by supply voltage * supply current and it is 1.01mW with
supply voltage of 1.8V. The circuit is simulated for different frequencies, from 1MHz to 900
MHz. And the duty cycle is corrected in the range of +/- 1.5% of accuracy as shown below in
Figure 22. The circuit can be still optimized by increasing the gain of an active integrator, so that
it can support even Gigahertz frequencies.
Figure 22. Frequency Vs output duty cycle
4. CONCLUSIONS
From above work it can be summarized that duty cycle corrector is one essential block in high
speed circuits. The analog feedback duty cycle corrector is being proposed. It corrects the
distorted input clock to achieve approximately 50% of duty cycle. It is able to correct input range
of 35% to 65% with Megahertz frequency range. Analog feedback has an advantage of better
accuracy and sometimes reduces the complexity. The limitation of this work is the circuit fails to
operate at GHz frequencies.
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As a scope for future work, the circuit can be still optimized by increasing the gain of an active
integrator, so that it can support even Gigahertz frequencies and accuracy can be increased by
increasing the gain of amplifier part of control voltage generator.
REFERENCES
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[8] Behzad Razavi, :Design of analog CMOS integrated circuits”, McGraw Hill International Edition.
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AUTHORS
Meghana Patil is a MTech student in VLSI and embedded systems at BMS college
of engineering, Bengaluru, Karnataka. She has done one year of internship in
Analog domain.
Dr Kiran Bailey is working in the Dept. of ECE, BMSCE, for the past 21 years
and has completed her doctorate in the field of VLSI devices. Her areas of interest
include novel device structures such as FinFETs, vertical MOSFETs and Tunnel
FETs.
Mr. Rajanikanth Anuvanahally is a IEEE Senior member. He has over 11 years of
experience in Analog and Mixed signal design with specialisation in Data
converters and clock circuits. In addition. he carries 4+ years of experience in
Learning and Development, built and deployed many E learning courses in the
Semiconductor domain.