This paper presents a highly adaptive operational amplifier with high gain, high bandwidth, high speed
and low power consumption. By adopting the recycling folded cascode topology along with an adaptivebiasing
circuit, this design achieves high performance in terms of gain-bandwidth product (GBW) and slew
rate (SR). This single stage op-amp has been designed in 0.18μm technology with a power supply of 1.8V
and a 5pF load. The simulation results show that the amplifier achieved a GBW of 335.5MHz, Unity Gain
Bandwidth of 247.1MHz and a slew rate of 92.8V/μs.
A RAIL-TO-RAIL HIGH SPEED CLASS-AB CMOS BUFFER WITH LOW POWER AND ENHANCED SL...VLSICS Design
A rail-to-rail class-AB CMOS buffer is proposed in this paper to drive large capacitive loads. A new
technique is used to reduce the leakage power of class-AB CMOS buffer circuits without affecting dynamic
power dissipation .The name of applied technique is LECTOR, which gives the high speed buffer with the
reduced low power dissipation (1.05%) and reduced area (2.8%). The proposed buffer is simulated at
45nm CMOS technology and the circuit is operated at 3V supply with cadence software. This analog circuit
is performed with extremely low leakage current as well as high current driving capability for the large
input voltages. The proposed paper is achieved very high speed with very low propagation delay range
i.e.(292×10-12). So the delay of the circuit is reduced to 10%. The settling time of this circuit is reduced by
24% (in ns) at 3V square wave input. The measured quiescent current is 41μA
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
LOW POWER LOW VOLTAGE BULK DRIVEN BALANCED OTAVLSICS Design
The last few decades, a great deal of attention has been paid to low-voltage (LV) low-power (LP) integrated circuits design since the power consumption has become a critical issue. Among many techniques used for the design of LV LP analog circuits, the Bulk-driven principle offers a promising route towards this design for many aspects mainly the simplicity and using the conventional MOS technology to implement these designs. This paper is devoted to the Bulk-driven (BD) principle and utilizing this principle to design LV LP building block of Operational Transconductance Amplifier (OTA) in standard CMOS processes and supply voltage 0.9V. The simulation results have been carried out by the Spice simulator using the 130nm CMOS technology from TSMC.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Open Loop Control Of Series Parallel Resonant ConverterIDES Editor
Resonant converters are desirable for power
conversion due to their comparatively smaller size and
lower power losses resulting from high-frequency
operation and inherent soft switching. Among all the
topologies of the resonant converters, the series–parallel
resonant converter (SPRC) is known to have the
combined merits of the series resonant converter and
parallel resonant converter. The converter can regulate
the output voltage at a constant switching frequency even
for a change in load resistance from full load resistance to
infinity while maintaining good part load efficiency. The
purpose of this project is to design a closed loop
controller for the phase-controlled series parallel
resonant converter (PC SPRC). The open loop analysis
and closed loop control has been provided in this paper.
A RAIL-TO-RAIL HIGH SPEED CLASS-AB CMOS BUFFER WITH LOW POWER AND ENHANCED SL...VLSICS Design
A rail-to-rail class-AB CMOS buffer is proposed in this paper to drive large capacitive loads. A new
technique is used to reduce the leakage power of class-AB CMOS buffer circuits without affecting dynamic
power dissipation .The name of applied technique is LECTOR, which gives the high speed buffer with the
reduced low power dissipation (1.05%) and reduced area (2.8%). The proposed buffer is simulated at
45nm CMOS technology and the circuit is operated at 3V supply with cadence software. This analog circuit
is performed with extremely low leakage current as well as high current driving capability for the large
input voltages. The proposed paper is achieved very high speed with very low propagation delay range
i.e.(292×10-12). So the delay of the circuit is reduced to 10%. The settling time of this circuit is reduced by
24% (in ns) at 3V square wave input. The measured quiescent current is 41μA
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
LOW POWER LOW VOLTAGE BULK DRIVEN BALANCED OTAVLSICS Design
The last few decades, a great deal of attention has been paid to low-voltage (LV) low-power (LP) integrated circuits design since the power consumption has become a critical issue. Among many techniques used for the design of LV LP analog circuits, the Bulk-driven principle offers a promising route towards this design for many aspects mainly the simplicity and using the conventional MOS technology to implement these designs. This paper is devoted to the Bulk-driven (BD) principle and utilizing this principle to design LV LP building block of Operational Transconductance Amplifier (OTA) in standard CMOS processes and supply voltage 0.9V. The simulation results have been carried out by the Spice simulator using the 130nm CMOS technology from TSMC.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Open Loop Control Of Series Parallel Resonant ConverterIDES Editor
Resonant converters are desirable for power
conversion due to their comparatively smaller size and
lower power losses resulting from high-frequency
operation and inherent soft switching. Among all the
topologies of the resonant converters, the series–parallel
resonant converter (SPRC) is known to have the
combined merits of the series resonant converter and
parallel resonant converter. The converter can regulate
the output voltage at a constant switching frequency even
for a change in load resistance from full load resistance to
infinity while maintaining good part load efficiency. The
purpose of this project is to design a closed loop
controller for the phase-controlled series parallel
resonant converter (PC SPRC). The open loop analysis
and closed loop control has been provided in this paper.
26 GHz phase shifters for multi-beam nolen matrix towards fifth generation (5...journalBEEI
This paper presents the designs of phase shifters for multi-beam Nolen matrix towards the fifth generation (5G) technology at 26 GHz. The low-cost, lightweight and compact size 0° and 45° loaded stubs and chamfered 90°, 135° and 180° Schiffman phase shifters are proposed at 26 GHz. An edge at a corner of the 50 Ω microstrip line Schiffman phase shifter is chamfered to reduce the excess capacitance and unwanted reflection. However, the Schiffman phase shifter topology is not relevant to be applied for the phase shifter less than 45° as it needs very small arc bending at 26 GHz. The stubs are loaded to the phase shifter in order to obtain electrical lengths, which are less than 45°. The proposed phase shifters provide return loss better than 10 dB, insertion loss of -0.97 dB and phase difference imbalance of ± 4.04° between 25.75GHz and 26.25 GHz. The Rogers RT/duroid 5880 substrate with dielectric constant of 2.2 and substrate thickness of 0.254 mm is implemented in the designs.
Investigation of TTMC-SVPWM Strategies for Diode Clamped and Cascaded H-bridg...ijeei-iaes
This paper presents a concept of two types multilevel inverters such as diode clamped and cascaded H-bridge for harmonic reduction on high power applications. Normally, multilevel inverters can be used to reduce the harmonic problems in electrical distribution systems. This paer focused on the performance and analysis of a three phase seven level inverter including diode clamped and cascaded H-bridge based on new tripizodal triangular space vector PWM technique approaches. TTMC based modified Space vector Pulse width modulation technique so called tripizodal triangular Space vector Pulse width modulation (TTMC-SVPWM) technique. In this paper the reference sine wave generated as in case of conventional off set injected SVPWM technique. It is observed that the TTMC-Space vector pulse width modulation ensures excellent, close to optimized pulse distribution results and THD is compared to seven level, diode clamped and cascaded multi level inverters. Theoretical investigations were confirmed by the digital simulations using MATLAB/SIMULINK software.
Design and Realization of 2.4GHz Branch-line CouplerQuang Binh Pham
In the scope of this paper, a branch-line coupler working at 2.4GHz is designed and realized. The experiment results are consequently compared to the simulation results.
A New CMOS Fully Differential Low Noise Amplifier for Wideband ApplicationsTELKOMNIKA JOURNAL
In this paper, a multi-stage fully differential low noise amplifier (LNA) has been presented for
wideband applications. A common-gate input stage is used to improve the input impedance matching and
linearity. A common-source stage is also used as the second stage to enhance gain and reduce noise. A
shunt-shunt feedback is employed to extend bandwidth and enhance linearity. The proposed low noise
amplifier has been designed and simulated using RF-TSMC 0.18 μm CMOS process technology. In
frequency band of 3.5-7.5 GHz, this amplifier has a flat power gain (S21) of 16.5 ± 1.5 dB, low noise figure
(NF) of 3dB, input (S11) and output (S22) return losses less than -10 dB and high linearity with input thirdorder
intercept point (IIP3) of -3dBm. It’s power consumption is also less than 10 mw with low power supply
voltage of 0.8v.
Electrical, Electronics and Computer Engineering,
Information Engineering and Technology,
Mechanical, Industrial and Manufacturing Engineering,
Automation and Mechatronics Engineering,
Material and Chemical Engineering,
Civil and Architecture Engineering,
Biotechnology and Bio Engineering,
Environmental Engineering,
Petroleum and Mining Engineering,
Marine and Agriculture engineering,
Aerospace Engineering.
A Simulation Based Analysis of Lowering Dynamic Power in a CMOS Inverteridescitation
With the increase in demand of high fidelity
portable devices, there is more and more emphasis laying
down on the development of low power and high performance
systems. In the next generation processors, the low power
design has to be incorporated into fundamental computation
units, such as adder. CMOS circuit design plays a crucial role
in designing of these computation units (like adder and
multiplier) so if there is any optimal way to reduce the power
dissipation in CMOS circuits then it will directly lower down
the power dissipation of other circuits and logic gates as well.
In this paper we have studied and analyzed different
techniques to reduce the dynamic power of CMOS circuit
with the help of performing simulation on some significant
factors (i.e device characteristics) of respective circuitry
designs by using Cadence-Virtuoso tool.
Optimal Body Biasing Technique for CMOS Tapered Buffer IJEEE
This paper represents Fixed Body Biased CMOS Tapered Buffer which is designed to minimize the average power dissipation across large capacitive load. The implementation of Reverse Body Bias (RBB) in the proposed Buffer chain is to vary Vth value of NMOS in the first stage. And with the increase in Vth /sub-threshold leakage current and power has been reduced. The technology constraints on the threshold voltage does not allow designer to set high threshold voltage for MOS devices. Hence, this was found that in proposed circuit that when optimal Reverse Body Bias value is set within (0.2 VDD to 0.4 VDD) range, the average power dissipation across capacitive load reduces to 82.2 % at very less penalty in delay. Thus CMOS buffer designers can use the proposed method to vary Vth while keeping VDD constant, which could improve the performance parameters of Tapered Buffer. The proposed analysis is verified by simulating the 3-stage tapered buffer schematics using standard 180nm CMOS technology in Cadence environment.
Gain improvement of two stage opamp through body bias in 45nm cmos technologyeSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
There are many ways in attracting visitors in organic ways. Some of the listed methods may be more appealing to you and some may be the one which can work best.
Although some of the strategies listed aren't easy and fast to perform, you have to look at thing positively - and that is to gain more visitors, make them come back for more and even convert them into leads.
What has been the best traffic source for you?
DESIGN AND PERFORMANCE ANALYSIS OF ZBT SRAM CONTROLLERVLSICS Design
Memory is an essential part of electronic industry. Since, the processors used in various high performance
PCs, network applications and communication equipment require high speed memories. The type of
memory used depends on system architecture, and its applications. This paper presents an SRAM
architecture known as Zero Bus Turnaround (ZBT). This ZBT SRAM is mainly developed for networking
applications where frequent READ/WRITE transitions are required. The other single data rate SRAMs are
inefficient as they require idle cycles when they frequently switch between reading and writing to the
memory. This controller is simulated on the Spartan 3 device. And the performance analysis is done on the
basis of area, speed and power.
SEO has plenty to teach us about life, work, relationships, and everything in between. For newly graduates out there, check out these words of wisdom from a veteran SEO expert.
Vlsics040307DESIGN AND IMPLEMENTATION OF CAR PARKING SYSTEM ON FPGAVLSICS Design
As, the number of vehicles are increased day by day in rapid manner. It causes the problem of traffic
congestion, pollution (noise and air). To overcome this problem A FPGA based parking system has been
proposed. In this paper, parking system is implemented using Finite State Machine modelling. The system
has two main modules i.e. identification module and slot checking module. Identification module
identifies the visitor. Slot checking module checks the slot status. These modules are modelled in HDL
and implemented on FPGA. A prototype of parking system is designed with various interfaces like sensor
interfacing, stepper motor and LCD.
Tracking cancer patients medical history using wireless emerging technology ...VLSICS Design
The principal objective of this paper is to present an effective solution for storing and retrieving a cancer
patient’s medical history in hospitals, clinics and wherever else need be. We have used latest technologies like Near Field Communication (NFC) as a medium for communication, MySQL server for storing the database i.e. EHR (Electronic Health Record) of patients and lastly an Android application which will provide the interface for the same.
A DAPTIVE S UPPLY V OLTAGE M ANAGEMENT F OR L OW P OWER L OGIC C IRCU...VLSICS Design
With the rise in demand of portable hand held devic
es and with the rise in application of wireless sen
sor
networks and RFID reduction of total power consumpt
ion has become a necessity. To save power we
operate the logic circuitry of our devices at sub-t
hreshold. In sub-threshold the drain current is
exponentially dependent on the threshold voltage he
nce the threshold variation causes profound variati
on
of I
ON
and I
OFF
the ratio of which affect the speed of a circuit d
rastically. So to mitigate this problem we
present a adaptive power management circuit which w
ill determine the minimum required supply voltage
to meet the timing requirement. Also to reduce the
power overhead and avoid bulky coil and EMI noise
we used the switch capacitor power regulator to reg
ulate and manage power instead of linear dropout
(LDO) and Inductor base switch mode power converter
26 GHz phase shifters for multi-beam nolen matrix towards fifth generation (5...journalBEEI
This paper presents the designs of phase shifters for multi-beam Nolen matrix towards the fifth generation (5G) technology at 26 GHz. The low-cost, lightweight and compact size 0° and 45° loaded stubs and chamfered 90°, 135° and 180° Schiffman phase shifters are proposed at 26 GHz. An edge at a corner of the 50 Ω microstrip line Schiffman phase shifter is chamfered to reduce the excess capacitance and unwanted reflection. However, the Schiffman phase shifter topology is not relevant to be applied for the phase shifter less than 45° as it needs very small arc bending at 26 GHz. The stubs are loaded to the phase shifter in order to obtain electrical lengths, which are less than 45°. The proposed phase shifters provide return loss better than 10 dB, insertion loss of -0.97 dB and phase difference imbalance of ± 4.04° between 25.75GHz and 26.25 GHz. The Rogers RT/duroid 5880 substrate with dielectric constant of 2.2 and substrate thickness of 0.254 mm is implemented in the designs.
Investigation of TTMC-SVPWM Strategies for Diode Clamped and Cascaded H-bridg...ijeei-iaes
This paper presents a concept of two types multilevel inverters such as diode clamped and cascaded H-bridge for harmonic reduction on high power applications. Normally, multilevel inverters can be used to reduce the harmonic problems in electrical distribution systems. This paer focused on the performance and analysis of a three phase seven level inverter including diode clamped and cascaded H-bridge based on new tripizodal triangular space vector PWM technique approaches. TTMC based modified Space vector Pulse width modulation technique so called tripizodal triangular Space vector Pulse width modulation (TTMC-SVPWM) technique. In this paper the reference sine wave generated as in case of conventional off set injected SVPWM technique. It is observed that the TTMC-Space vector pulse width modulation ensures excellent, close to optimized pulse distribution results and THD is compared to seven level, diode clamped and cascaded multi level inverters. Theoretical investigations were confirmed by the digital simulations using MATLAB/SIMULINK software.
Design and Realization of 2.4GHz Branch-line CouplerQuang Binh Pham
In the scope of this paper, a branch-line coupler working at 2.4GHz is designed and realized. The experiment results are consequently compared to the simulation results.
A New CMOS Fully Differential Low Noise Amplifier for Wideband ApplicationsTELKOMNIKA JOURNAL
In this paper, a multi-stage fully differential low noise amplifier (LNA) has been presented for
wideband applications. A common-gate input stage is used to improve the input impedance matching and
linearity. A common-source stage is also used as the second stage to enhance gain and reduce noise. A
shunt-shunt feedback is employed to extend bandwidth and enhance linearity. The proposed low noise
amplifier has been designed and simulated using RF-TSMC 0.18 μm CMOS process technology. In
frequency band of 3.5-7.5 GHz, this amplifier has a flat power gain (S21) of 16.5 ± 1.5 dB, low noise figure
(NF) of 3dB, input (S11) and output (S22) return losses less than -10 dB and high linearity with input thirdorder
intercept point (IIP3) of -3dBm. It’s power consumption is also less than 10 mw with low power supply
voltage of 0.8v.
Electrical, Electronics and Computer Engineering,
Information Engineering and Technology,
Mechanical, Industrial and Manufacturing Engineering,
Automation and Mechatronics Engineering,
Material and Chemical Engineering,
Civil and Architecture Engineering,
Biotechnology and Bio Engineering,
Environmental Engineering,
Petroleum and Mining Engineering,
Marine and Agriculture engineering,
Aerospace Engineering.
A Simulation Based Analysis of Lowering Dynamic Power in a CMOS Inverteridescitation
With the increase in demand of high fidelity
portable devices, there is more and more emphasis laying
down on the development of low power and high performance
systems. In the next generation processors, the low power
design has to be incorporated into fundamental computation
units, such as adder. CMOS circuit design plays a crucial role
in designing of these computation units (like adder and
multiplier) so if there is any optimal way to reduce the power
dissipation in CMOS circuits then it will directly lower down
the power dissipation of other circuits and logic gates as well.
In this paper we have studied and analyzed different
techniques to reduce the dynamic power of CMOS circuit
with the help of performing simulation on some significant
factors (i.e device characteristics) of respective circuitry
designs by using Cadence-Virtuoso tool.
Optimal Body Biasing Technique for CMOS Tapered Buffer IJEEE
This paper represents Fixed Body Biased CMOS Tapered Buffer which is designed to minimize the average power dissipation across large capacitive load. The implementation of Reverse Body Bias (RBB) in the proposed Buffer chain is to vary Vth value of NMOS in the first stage. And with the increase in Vth /sub-threshold leakage current and power has been reduced. The technology constraints on the threshold voltage does not allow designer to set high threshold voltage for MOS devices. Hence, this was found that in proposed circuit that when optimal Reverse Body Bias value is set within (0.2 VDD to 0.4 VDD) range, the average power dissipation across capacitive load reduces to 82.2 % at very less penalty in delay. Thus CMOS buffer designers can use the proposed method to vary Vth while keeping VDD constant, which could improve the performance parameters of Tapered Buffer. The proposed analysis is verified by simulating the 3-stage tapered buffer schematics using standard 180nm CMOS technology in Cadence environment.
Gain improvement of two stage opamp through body bias in 45nm cmos technologyeSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
There are many ways in attracting visitors in organic ways. Some of the listed methods may be more appealing to you and some may be the one which can work best.
Although some of the strategies listed aren't easy and fast to perform, you have to look at thing positively - and that is to gain more visitors, make them come back for more and even convert them into leads.
What has been the best traffic source for you?
DESIGN AND PERFORMANCE ANALYSIS OF ZBT SRAM CONTROLLERVLSICS Design
Memory is an essential part of electronic industry. Since, the processors used in various high performance
PCs, network applications and communication equipment require high speed memories. The type of
memory used depends on system architecture, and its applications. This paper presents an SRAM
architecture known as Zero Bus Turnaround (ZBT). This ZBT SRAM is mainly developed for networking
applications where frequent READ/WRITE transitions are required. The other single data rate SRAMs are
inefficient as they require idle cycles when they frequently switch between reading and writing to the
memory. This controller is simulated on the Spartan 3 device. And the performance analysis is done on the
basis of area, speed and power.
SEO has plenty to teach us about life, work, relationships, and everything in between. For newly graduates out there, check out these words of wisdom from a veteran SEO expert.
Vlsics040307DESIGN AND IMPLEMENTATION OF CAR PARKING SYSTEM ON FPGAVLSICS Design
As, the number of vehicles are increased day by day in rapid manner. It causes the problem of traffic
congestion, pollution (noise and air). To overcome this problem A FPGA based parking system has been
proposed. In this paper, parking system is implemented using Finite State Machine modelling. The system
has two main modules i.e. identification module and slot checking module. Identification module
identifies the visitor. Slot checking module checks the slot status. These modules are modelled in HDL
and implemented on FPGA. A prototype of parking system is designed with various interfaces like sensor
interfacing, stepper motor and LCD.
Tracking cancer patients medical history using wireless emerging technology ...VLSICS Design
The principal objective of this paper is to present an effective solution for storing and retrieving a cancer
patient’s medical history in hospitals, clinics and wherever else need be. We have used latest technologies like Near Field Communication (NFC) as a medium for communication, MySQL server for storing the database i.e. EHR (Electronic Health Record) of patients and lastly an Android application which will provide the interface for the same.
A DAPTIVE S UPPLY V OLTAGE M ANAGEMENT F OR L OW P OWER L OGIC C IRCU...VLSICS Design
With the rise in demand of portable hand held devic
es and with the rise in application of wireless sen
sor
networks and RFID reduction of total power consumpt
ion has become a necessity. To save power we
operate the logic circuitry of our devices at sub-t
hreshold. In sub-threshold the drain current is
exponentially dependent on the threshold voltage he
nce the threshold variation causes profound variati
on
of I
ON
and I
OFF
the ratio of which affect the speed of a circuit d
rastically. So to mitigate this problem we
present a adaptive power management circuit which w
ill determine the minimum required supply voltage
to meet the timing requirement. Also to reduce the
power overhead and avoid bulky coil and EMI noise
we used the switch capacitor power regulator to reg
ulate and manage power instead of linear dropout
(LDO) and Inductor base switch mode power converter
Dynamic floating output stage for low power buffer amplifier for lcd applicationVLSICS Design
This topic proposes low-power buffer means low quiescent current buffer amplifier. A dynamic floating current node is used at the output of two-stage amplifier to increase the charging and discharging of output capacitor as well as settling time of buffer. It is designed for 10 bit digital analog converter to support for LCD column driver it is implemented in 180 nm CMOS technology with the quiescent current of 5 μA for 30 pF capacitance, the settling time calculated as 4.5μs, the slew rate obtained as 5V/μs and area on chip is 30×72μ.
Design of a novel current balanced voltage controlled delay elementVLSICS Design
This paper presents a design of fast voltage controlled delay element based on modified version of low
noise Current Balanced Logic (CBL). This delay element provides identical rising and falling edge delays
controlled by the single control voltage. The post layout tunable delay range is from 140 ps to 800 ps over
control voltage range of 0 to 2.1 V. An analysis for the delay element is also presented, which is in
agreement with the simulated delays. A Delay Lock Loop (DLL) is designed using this delay element to
verify its performance.
An efficient multi resolution filter bank based on da based multiplicationVLSICS Design
Multi-resolution filter bank (MRFB)-based on the fast filter bank design can be used for multiple resolution
spectrum sensing. MRFB overcomes the constraint of fixed sensing resolution in spectrum sensors based
on conventional discrete Fourier transform filter banks (DFTFB) without hardware re-implementation.
Multipliers have a greater impact on complexity and performance of the design because a large number of
constant multiplications are required in the multiplication of filter coefficients with the filter input.
Modified multiplier architecture Distributed Arithmetic(DA) is used to improve the efficiency
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ANALYSIS OF SMALL-SIGNAL PARAMETERS OF 2-D MODFET WITH POLARIZATION EFFECTS F...VLSICS Design
An improved analytical two dimensional (2-D) model for AlGaN/GaN modulation doped field effect
transistor (MODFET) has been developed. The model is based on the solution of 2-D Poisson’s equation.
The model includes the spontaneous and piezoelectric polarization effects. The effects of field dependent
mobility, velocity saturation and parasitic resistances are included in the current voltage characteristics of
the developed two dimensional electron gas (2-DEG) model. The small-signal microwave parameters have
been evaluated to determine the output characteristics, device transconductance and cut-off frequency for
50 nm gate length. The peak transconductance of 165mS/mm and a cut-off frequency of 120 GHz have been
obtained. The results so obtained are in close agreement with experimental data, thereby proving the
validity of the model.
DESIGN OF PARITY PRESERVING LOGIC BASED FAULT TOLERANT REVERSIBLE ARITHMETIC ...VLSICS Design
Reversible Logic is gaining significant consideration as the potential logic design style for implementation
in modern nanotechnology and quantum computing with minimal impact on physical entropy .Fault
Tolerant reversible logic is one class of reversible logic that maintain the parity of the input and the
outputs. Significant contributions have been made in the literature towards the design of fault tolerant
reversible logic gate structures and arithmetic units, however, there are not many efforts directed towards
the design of fault tolerant reversible ALUs. Arithmetic Logic Unit (ALU) is the prime performing unit in
any computing device and it has to be made fault tolerant. In this paper we aim to design one such fault
tolerant reversible ALU that is constructed using parity preserving reversible logic gates. The designed
ALU can generate up to seven Arithmetic operations and four logical operations.
EVALUATION OF OPTICALLY ILLUMINATED MOSFET CHARACTERISTICS BY TCAD SIMULATIONVLSICS Design
In this paper we report effect of optical illumination on Silicon MOSFET. The MOSFET has been studied in
respect of current voltage, transconductance admittance and scattering parameters. Gain analysis of the
Silicon MOSFET is done in dark and under optical illumination. The device is fabricated using ATHENA™
process simulator and the device simulation is performed using ATLAS™ from SILVACO international.
The simulation results indicate potential of MOSFET as optically sensitive structure which can be used
for increase in data transmission/reception rates, reduction of interconnect delays, elimination of clock
skew, or as a photodetector for optoelectronic applications at low and radio frequency.
Energy Efficient Full Adder Cell Design with Using Carbon Nanotube Field Effe...VLSICS Design
Full Adder is one of the critical parts of logical and arithmetic units. So, presenting a low power full adder
cell reduces the power consumption of the entire circuit. Also, using Nano-scale transistors, because of
their unique characteristics will save energy consumption and decrease the chip area. In this paper we
presented a low power full adder cell by using carbon nanotube field effect transistors (CNTFETs).
Simulation results were carried out using HSPICE based on the CNTFET model in 32 nanometer
technology in Different values of temperature and VDD.
AN OPERATIONAL AMPLIFIER WITH RECYCLING FOLDED CASCODE TOPOLOGY AND ADAPTIVE ...VLSICS Design
This paper presents a highly adaptive operational amplifier with high gain, high bandwidth, high speed and low power consumption. By adopting the recycling folded cascode topology along with an adaptivebiasing circuit, this design achieves high performance in terms of gain-bandwidth product (GBW) and slew rate (SR). This single stage op-amp has been designed in 0.18µm technology with a power supply of 1.8V and a 5pF load. The simulation results show that the amplifier achieved a GBW of 335.5MHz, Unity Gain Bandwidth of 247.1MHz and a slew rate of 92.8V/µs.
Compact low power high slew-rate cmos buffer amplifier with power gating tech...VLSICS Design
A qualitative analysis of different parameters such as Phase noise, Slew rate and tranconductance by using
power gating reduction technique is presented. The circuit achieves the large driving capability by
employing simple comparators to sense the transients of the input to turn on the output stages, which are
statically off in the stable state. The effect of the different number of transistors and their topologies on the
phase noise and Slew rate is analyzed. Good agreement between qualitative and quantitative measurements
is observed. Scope of reducing of Noise and avoidance of Leakage due to various sources is discussed.
A 10 d bm 25 dbm, 0.363 mm2 two stage 130 nm rf cmos power amplifierVLSICS Design
This paper proposes a 2.4 GHz RF CMOS Power amplifi
er and variation in its main performance
parameters i.e, output power, S-parameters and powe
r added efficiency with respect to change in supply
voltage and size of the power stage transistor. The
supply voltage was varied form 1 V to 5 V and the
range
of output power at 1dB compression point was found
to be from 10.684 dBm to 25.08 dBm respectively.
The range of PAE is 16.65 % to 48.46 %. The width o
f the power stage transistor was varied from 150 μm
to 500 μm to achieve output power of range 15.47 dB
m to 20.338 dBm. The range of PAE obtained here is
29.085 % to 45.439 %. The total dimension of the la
yout comes out to be 0.714 * 0.508 mm
2
.
Design of Low Voltage Low Power CMOS OP-AMPIJERA Editor
Operational amplifiers are an integral part of many analog and mixed signal systems. As the demand for mixed
mode integrated circuits increases, the design of analog circuits such as operational amplifiers in CMOS
technology becomes more critical. This paper presents a two stage CMOS operational amplifier, which operates
at ±1.8V power supply using TSMC 0.18um CMOS technology. The OP-AMP designed exhibit unity gain
frequency of 12.6 MHz, and gain of 55.5db with 300uw power dissipation. The gain margin and phase margin
of OP-AMP is 45˚ and 60˚ respectively. Design and simulation has been carried out in P Spice tool.
Low Power Low Voltage Bulk Driven Balanced OTA VLSICS Design
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A LOW POWER, LOW PHASE NOISE CMOS LC OSCILLATORIJEEE
In this paper a Double Cross Coupled Inductor capacitor based Voltage Control Oscillator (LC-VCO) is designed. In the proposed circuit the phase noise, tuning range with respect to control voltage, output power and the power dissipation of the circuit is analysed. Phase noise of approximate -96 dBc/Hz at frequency of 1MHz, frequency tuning range of 4.8 to 8.3 GHz (corresponding to 53.0% tuning range) obtained by varying the control voltage from 0 to 2.0 V, Output power of circuit -8.92 dBm at 50 Ohm resistance terminal and the power consumption of Circuit is 3.8 mW. This VCO are designed for 5.5 GHz. The circuit is designed on the UMC 180nm CMOS technology and all the simulation results are obtained using cadence SPECTRE Simulator.
A High-Swing OTA with wide Linearity for design of self-tunable linear resistorVLSICS Design
Low power consumption, long battery life and portability are essential requirements of modern health monitoring products. Operational Transconductance Amplifier (OTA) operating in subthreshold region is an basic building block for low power health monitoring products design. An modified design of OTA which incorporates better linearity and increased output impedance has been discussed in this paper. The proposed OTA uses High-swing improved-Wilson current mirror for low power and low-frequency applications. The achieved linearity is about ± 1.9 volt and unity gain bandwidth (UGB) of 342.30 KHz at power supply of 0.9 volt which makes OTA to consume power in range of nanowatts. The proposed low voltage OTA implementation in design of self- tunable linear resistor has been presented in this paper. The circuit implementation has been done using standard 0.18 micron technology provided by TSMC on BSIM 3v3 level-53 model parameter and verified results through use of ELDO Simulator.
Distortion Analysis of Differential AmplifierIOSR Journals
Abstract: The linearity of the CMOS is of major concern in the design of many analog circuits. In this paper the nonlinearity behavior of CMOS analog integrated circuits is investigated.The basic building block of analog integrated circuits such as differential amplifier with current mirror load have been chosen for harmonic distortion analysis.A mechanism to analyze the distortion of CMOS circuits in deep submicron technology that can be easily used to detect the distortion is built.The MOSFET model used for simulation is TSMC BSIM3 SPICE model from 0.13-μm CMOS process technology. HSPICE circuit simulator tool is used for distortion analysis of CMOS circuits. The MOS model used in this paper includes short-channel effects and gate-source capacitance, gate-drain capacitance, output resistance of MOS transistor. Analytical results are compared with simulation results and the influences of circuit parameters on circuit linearity are discussed.
Keywords: Analog Integrated Circuits, CMOSanalog integrated circuits, harmonic distortion, HSPICE, Short-channel effects, small signal analysis, transient analysis.
A High-Swing OTA with wide Linearity for design of self-tunable linear resistorVLSICS Design
Low power consumption, long battery life and portability are essential requirements of modern health monitoring products. Operational Transconductance Amplifier (OTA) operating in subthreshold region is an basic building block for low power health monitoring products design. An modified design of OTA which incorporates better linearity and increased output impedance has been discussed in this paper. The proposed OTA uses High-swing improved-Wilson current mirror for low power and low-frequency applications. The achieved linearity is about ± 1.9 volt and unity gain bandwidth (UGB) of 342.30 KHz at power supply of 0.9 volt which makes OTA to consume power in range of nanowatts. The proposed low voltage OTA implementation in design of self- tunable linear resistor has been presented in this paper. The circuit implementation has been done using standard 0.18 micron technology provided by TSMC on BSIM 3v3 level-53 model parameter and verified results through use of ELDO Simulator.
A 80Ms/sec 10bit PIPELINED ADC Using 1.5Bit Stages And Built-in Digital Error...VLSICS Design
Use of pipelined ADCs is becoming increasingly popular both as stand alone parts and as embedded functional units in SOC design. They have acceptable resolution and high speed of operation and can be placed in relatively small area. The design is implemented in 0.18uM CMOS process. The design includes a folded cascode op-amp with a unity gain frequency of 200MHz at 88 deg. Phase margin and a dc gain of 75dB. The circuit employs a built in sample and hold circuit and a three phase non-overlapping clock.
A 80Ms/sec 10bit PIPELINED ADC Using 1.5Bit Stages And Built-in Digital Error...VLSICS Design
Use of pipelined ADCs is becoming increasingly popular both as stand alone parts and as embedded functional units in SOC design. They have acceptable resolution and high speed of operation and can be placed in relatively small area. The design is implemented in 0.18uM CMOS process. The design includes a folded cascode op-amp with a unity gain frequency of 200MHz at 88 deg. Phase margin and a dc gain of 75dB. The circuit employs a built in sample and hold circuit and a three phase non-overlapping clock.
INPUT REFERRED NOISE REDUCTION TECHNIQUE FOR TRANSCONDUCTANCE AMPLIFIERSecij
In this paper, a useful procedure to design folded cascode (FC) and recycling folded cascode (RFC) OTAs is presented. The proposed procedure is based on a simplified equation of input voltage noise in strong and weak inversion regions. The presented method considerably decreases the input referred noise of amplifiers in weak, moderate and strong inversion. The proposed amplifiers were simulated in 0.18µm CMOS
technology, achieving 36% and 25% reduction of input voltage noise @ 1Hz in strong and weak inversion, respectively, compared to the conventional FC, without increasing power consumption and silicon area.
Enhancing phase margin of ota using self biasingelelijjournal
In this paper, a new adaptive biased low voltage cascode current mirror with high input/output swing is presented. This advantage is achieved using a self-biasing transistor and compensation resistor. The new structure profits from better input dynamic range and lower supply voltage without frequency response limitation and increasing input impedance. Also, the proposed current mirror is incorporated in folded cascode amplifier in order to enhance its phase-margin. The simulation results in 0.18 μm CMOS technology confirm the theoretical analysis and exhibits 478μA linear input/output current swing and a
phase-margin enhancement of 12o for the proposed current mirror and amplifier compared to the conventional circuits, respectively
Design of a high frequency low voltage CMOS operational amplifierVLSICS Design
A method is presented in this paper for the design of a high frequency CMOS operational amplifier (OpAmp) which operates at 3V power supply using tsmc 0.18 micron CMOS technology. The OPAMP designed is a two-stage CMOS OPAMP followed by an output buffer. This Operational Transconductance Amplifier (OTA) employs a Miller capacitor and is compensated with a current buffer compensation technique. The unique behaviour of the MOS transistors in saturation region not only allows a designer to work at a low voltage, but also at a high frequency. Designing of two-stage op-amps is a multi-dimensional-optimization problem where optimization of one or more parameters may easily result into degradation of others. The OPAMP is designed to exhibit a unity gain frequency of 2.02GHz and exhibits a gain of 49.02dB with a 60.50 phase margin. As compared to the conventional approach, the proposed compensation method results in a higher unity gain frequency under the same load condition. Design has been carried out in Tanner tools. Simulation results are verified using S-edit and W-edit.
DESIGN AND ANALYSIS OF 2 GHz 130nm CMOS CASCODE LOW NOISE AMPLIFIER WITH INTE...csijjournal
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An operational amplifier with recycling folded cascode topology and adaptive biasing
1. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.4, August 2014
AN OPERATIONAL AMPLIFIER WITH
RECYCLING FOLDED CASCODE TOPOLOGY
AND ADAPTIVE BIAISNG
Saumya Vij1, Anu Gupta2 and Alok Mittal3
1,2Electrical and Electronics Engineering, BITS-Pilani, Pilani, Rajasthan, India
3High Speed Links, STMicroelectronics, Greater Noida
ABSTRACT
This paper presents a highly adaptive operational amplifier with high gain, high bandwidth, high speed
and low power consumption. By adopting the recycling folded cascode topology along with an adaptive-biasing
circuit, this design achieves high performance in terms of gain-bandwidth product (GBW) and slew
rate (SR). This single stage op-amp has been designed in 0.18μm technology with a power supply of 1.8V
and a 5pF load. The simulation results show that the amplifier achieved a GBW of 335.5MHz, Unity Gain
Bandwidth of 247.1MHz and a slew rate of 92.8V/μs.
KEYWORDS
Recycling Folded Cascode, Operational Amplifier, slew rate, Adaptive biasing, Transconductance
1. INTRODUCTION
In high performance analog integrated circuits, such as switch-capacitor filters, delta-sigma
modulators and pipeline A/D converters, op amps with very high dc gain and high unity-gain
frequency are needed to meet both accuracy and fast settling requirements of the systems.
However, as CMOS design scales into low-power, low-voltage and short-channel CMOS process
regime, satisfying both of these aspects leads to contradictory demands, and becomes more and
more difficult, since the intrinsic gain of the devices is limited. [1]
In order to achieve high-gain, the folded cascode amplifier is often adopted as the first-stage of
two-stage amplifiers. Actually, in the deep-submicron CMOS technology, high-gain amplifiers
are difficult to be implemented because of the inherent low intrinsic gain of the standard threshold
voltage MOS transistors. At the same time, because of the reliability reasons in the deep-submicron
processes, the output swing of amplifier is severally restricted with the lower power
supply voltage. [2]
To efficiently increase operational amplifier’s gain and output swing, multi-stage fully-differential
operational amplifier topology is appreciated. The operational amplifier with three or
even more stages equipped with the Nested-Miller compensation or the Reversed Nested-Miller
compensation shows high efficiency in the gain enhancement, while they require additional large
compensation capacitors compared to the traditional two-stage operational amplifier, which will
lead to a larger die area and the limited slew rate. Besides, additional common mode feedback
(CMFB) circuits would consume additional power. [3]
DOI : 10.5121/vlsic.2014.5403 33
2. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.4, August 2014
This paper presents a novel idea of implementing recycling folded cascode [4] along with an
adaptive-biasing circuit[5] to achieve high gain, high bandwidth and high slew rate specifications.
Section 2 describes the proposed design. Section 3 analyzes the design and working of the circuit.
Implementation is discussed in section 4, simulations in section 5, followed by conclusion in
section 6.
34
2. PROPOSED STRUCTURE
The proposed design presented in this paper employees the recycling folded cascode along with
an adaptive bias current circuit. This single stage operational amplifier is capable of providing
high gain of around 70dB along with a high bandwidth of 250 MHz and a slew rate of around
100V/μs which is approximately twice as that of the recycling folded cascode without the
additional adaptive-biasing circuit.
Recycling folded cascode is basically a modified folded cascode where the load transistor also
acts as a driving transistor, hence, enhancing the current carrying capability of the circuit.
Recycling folded cascode is obtained by splitting the input transistors and the load transistors as
given in figure 1. The cross-over connections of these current mirrors ensure that the small signal
currents are added at the sources of M1, M2, M3 and M4 and are in phase.
This is called as recycling folded cascode (RFC), as it reuses/recycles the existing devices and
currents to perform an additional task of increasing the current driving capability of the circuit.
The proposed modification in the recycling folded cascode topology involves replacing the
transistor M0 with an adaptive-biasing circuit (figure 1) [5] which further enhances the current
driving capability of this circuit and hence the speed.
2.1 Adaptive Biasing Design
Adaptive biasing circuit consists of two level shifters and a current sources IB. They have a very
low output resistance (typically in the range of 20 – 100 ohms). Quiescent current in M1 and M2
is the well-controlled bias current IB of the level-shifter transistors assuming M1, M2, M1a and
M1b are matched.
Since the ac input signal is applied to both the gate and the source terminals of M1 and M2, the
transconductance of this input stage is twice as that of a conventional differential pair.
It is clear that for large Vin,d the output current increases with it, enhancing quadratically the
current boosting. The minimum supply voltage of this circuit is |VTH| + 3|VDS,sat| where |VDS,sat| is
the minimum |VDS| for operation in saturation region. For |VTH| = 0.7V and |VDS,sat| = 0.2 V, it
yields 1.3V. Hence, the circuit is suitable for low voltage operations.
3. ANALYSIS AND DESIGN OF THE PROPOSED STRUCTURE
3.1 Low Frequency Gain
The open loop gain of an operational amplifier determines the precision of the feedback systems
employing it. A high open loop gain is a necessity to suppress linearity [6]. The low frequency
gain of OTAs is frequently expressed as the product of the small signal transconductance, Gm
and the low frequency output impedance, Ro. The low frequency gain of the adaptive recycling
folded cascode is almost the same as that of the recycling folded cascode topology, i.e.
3. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.4, August 2014
35
RoARFC gm16r016 (ro4||ro10) || gm14ro14ro12 (1)
GmARFC GmRFC (=gm1(1+K) ) where K=3 (2)
Both the RFC and adaptive RFC (ARFC) have similar noise injection gains from either supply.
Although there is no discernable change in low frequency gain but extended bandwidth of the
adaptive RFC ensures high GBW. Moreover, the extended GBW of the adaptive RFC extends the
improved PSRR performance to higher frequencies than the RFC.
3.2 Phase Margin
The phase margin is often viewed as a good indicator to the transient response of an amplifier,
and is determined by the poles and zeros of the amplifier transfer function. The adaptive RFC
shares a dominant pole p1, determined by the output impedance and capacitive load and a non-dominant
pole p2, determined by the parasitic at the source of M15/M16. It has a pole-zero pair,
p3 and pz (= (K+1) p3), associated with the current mirrors M7:M8 and M9:M10. However,
this pole-zero pair is associated with NMOS devices, which puts it at a high frequency. In
addition, adaptive RFC also have a pole due to adaptive current source, p4. Due to low
Impedence at that node it is pushed to a high frequency.
Figure1. Schematic of the proposed design
The pole-zero values from the PZ analysis in cadence virtuoso have been tabulated in Table 1 and
Table 2. Also, their positioning with respect to each other is shown in figure 2.
4. International Journal of VLSI design Communication Systems (VLSICS) Vol.5, No.4, August 2014
36
Table1. Pole Analysis
Pole Real Value
p1 -1.267e+05
p2 -3.551e+08
p3 -5.324e+08
p4 -9.908e+08
z -21.296e+08
Table 2. Zero Analysis
Pole Real Value
z -21.296e+08
Figure 2. Pole-zero analysis of the proposed design
3.3 Slew Rate
Slew rate is one of the most critical design aspects especially for the kind of circuits where high
speed is necessity. To achieve a high slew rate, adaptive biasing circuit plays a vital role. The
upper part of the proposed design [5] that is the adaptive biasing circuit consists of four matched
transistors M1, M2, M3 and M4 cross-coupled by two dc level shifters. Each level shifter is built
using two transistors (M1a, M2a and M1b, M2b) and a current source. These level shifters are called
Flipped Voltage Followers (FVFs). The dc level shifters must be able to source large currents
when the circuit is charging or discharging a large load capacitance. Moreover, they should be
simple due to noise, speed, and supply constraints.
Analysis of the proposed design shows that there is a significant improvement in its slew rate
over the RFC topology. Suppose Vin+ goes high, it follows that M1 and M2 turn off, which forces
M9 and M10 to turn off. Consequently, the drain voltage of M9 rises and M16 is turned off whereas
M3 is driven into deep triode. This directs current Id into M4 and in turn is mirrored by a factor of
3(K) (M7, M8) into M15, and again by a factor of 1 into (M11, M12). For simplicity, if we ignore
any parasitic capacitance at the sources of M1,2,3,4 and follow the similar derivation steps but
assuming Vin+ goes low, the result is symmetric slew rate expressed in (3)
SR (adaptive) RFC = 6Id/CL [4] (3)
We know that, Id = ID + id (4)
5. International Journal of VLSI design Communication Systems (VLSICS) Vol.5, No.4, August 2014
Due to presence of the adaptive biasing circuit, this circuit changes current according to the input
voltage and hence remains self-biased. It also causes minimal increase in power dissipation as the
current only increase proportional to the voltage in one branch and correspondingly decreases in
the other one.
Since the ac input signal is applied to both the gate and the source terminals of M1,2 and M3,4, the
transconductance of this input stage is twice as that of a conventional differential pair.
37
The ac small-signal differential current of the input stage is
Id = i1-i2 (1 + ( gm2A.B roA,B -1)/(gm2A,B roA,B+1)) (5)
Clearly ac small signal current is twice as that in the case of RFC without adaptive biasing circuit.
Hence, Slew rate has improved in the proposed circuit.
Figure 3. Snapshot from Virtuoso of Proposed Design Schematic
4. IMPLEMENTATION
To validate the theoretical results, we first implemented the recycling folded cascode topology as
a benchmark for comparison with our proposed design. And then we simulated our own design
and compared the results with our implementation of the RFC. Table 3 details the transistor sizes
used in the implementation of the proposed structure as well as of our RFC implementation.
6. International Journal of VLSI design Communication Systems (VLSICS) Vol.5, No.4, August 2014
38
Table 3. Device sizes in implementation
Device Proposed design RFC
Mo[4] - 60μm/500nm
M1a, M1b 100μm/500nm -
M2a, M2b 128μm/360nm -
M1, M2, M3, M4 64μm/360nm 64μm/360nm
M11, M12 64μm/360nm 70μm/500nm
M13, M14 64μm/360nm 84μm/500nm
M5, M6 8μm/180nm 8μm/180nm
M15, M16 10μm/180nm 10μm/180nm
M7, M10 24μm/500nm 24μm/500nm
M8, M9 8μm/500nm 8μm/500nm
5. SIMULATION RESULTS
All the simulations were done on cadence virtuoso with 0.18 μm technology using a VDD of
1.8V. The load capacitance was taken to be 5.6pF for all the simulations.
Here is the procedure for all the simulations. First of all DC analysis was done to ensure
saturation for all transistors. After that, the AC analysis with differential input signal as 1VPP was
done to measure the gain, GBW, UGB and Phase margin. After the AC analysis, a transient
analysis was done to measure the slew rate and settling time (1%). For the transient analysis, the
input signal was given as a square pulse (as shown in figure 12) of amplitude 1V at 5MHz. The
results of the simulations are tabulated in Table 4 and Table 5. Table 6 details the bias currents in
all the transistors of the proposed structure implementation.
Table 4. Results comparison with RFC Implementation
Parameters
Proposed
structure (tt)
RFC simulation
DC Gain(dB) 68.48 71
UGB(MHz) 247.1 153
GBW(MHz) 335.5 172.26
Slew rate(V/μs) 92.8 67.4
Settling time (1%)(ns) 12.39 21.93
Phase Margin 26.3o 58.1o
Power Dissipation(mW) 2.493 2.18
I(total) (mA) 1.385 1.215
Capacitive load 5.6 pF 5.6 pF
Technology 0.18μm 0.18μm
7. International Journal of VLSI design Communication Systems (VLSICS) Vol.5, No.4, August 2014
39
Table 5. Result of proposed design at extreme corners
Parameters tt ff ss
DC Gain(dB) 68.48 63.83 66.3
UGB(MHz) 247.1 267.6 203.9
GBW(MHz) 335.5 352 280.27
Slew rate(V/μs) 92.8 134.4 71.4
Settling time
12.39 8.9 17.25
(1%)(ns)
Phase Margin 26.3o 34.9o 25.2o
Power
Dissipation(mW)
2.493 3.334 2.049
I(total) (mA) 1.385 1.684 1.265
Capacitive load 5.6 pF 5.6 pF 5.6pF
Technology 0.18μm 0.18μm 0.18μm
Table 6. Bias Current in Proposed Structure
Device Ibias(μA) (tt)
M1a, M2a 181.1
M1b, M2b 86
M1, M4 48.79
M2, M3 46.29
M11, M12, M13, M14, M15, M16 90.63
M5, M6 46.29
M7, M10 139.4
M8, M9 46.29
The UGB of the proposed design is 247.1MHz while for RFC it is 153MHz showing a significant
increase in bandwidth as expected. The GBW has also increased from 172.26 MHz for RFC to
335.5 MHz for the proposed design. As proved theoretically, the slew rate has improved from
67.4V/μs to 92.8V/μs. Also, correspondingly, the settling time (1%) has decreased from 21.93 ns
to 12.39 ns showing an increase in the speed of the circuit significantly. Although the phase
margin has reduced but it can be dealt with by using a compensation capacitance when a second
stage is added to this design. Compensation capacitor will introduce a RHP zero in two stage op
Amp, which will cause serious issue. Hence RC compensation is a better choice, as it will allow
moving the zero away or forcing it in LHP. The most impressive aspect of this design is the fact
the increased speed and bandwidth is achieved with nearly the same power dissipation as the
RFC. The circuit has been implemented on all corners with all transistors in the saturation state.
Table III demonstrates the simulation results of the circuit in all corners i.e. tt, ss and ff.
Figure 4 shows the linear settling time response plotted during the transient analysis which was
used for the slew rate and settling time calculations. The open loop AC response of the amplifier
8. International Journal of VLSI design Communication Systems (VLSICS) Vol.5, No.4, August 2014
in tt, ff and ss corners is shown in figures 5, 6 and 7 respectively. Simulation graphs of settling
time calculation are shown in figure 8, 9 and 10.
40
Figure 4. Graph for calculating rate slew
Figure 5. Gain Phase plot for tt case
9. International Journal of VLSI design Communication Systems (VLSICS) Vol.5, No.4, August 2014
41
Figure 6. Gain Phase plot for ff corner
Figure 7. Gain Phase plot for ss corner
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Figure 8. Settling time calculation at ff corner
Figure 9. Settling time calculation at tt
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Figure 10. Settling time calculation at ss corner
5.1 Operational Amplifier as a Voltage Follower
The proposed design was implemented with a negative feedback in a voltage follower
configuration (shown in figure 11) to test the stability of the design. An input pulse of 1V was
given at 5MHz to check its response and functioning. Figure 9 below shows the input and output
pulses in a voltage follower configuration. It is evident from the output graph that the delay
introduced by the voltage follower is very small. Also, a distortion less and non-sluggish output is
achieved as a result of high slew rate and bandwidth provided by the ARFC.
Due to high slew rate and bandwidth characteristics, ARFC finds application in various other
speed critical circuits such as switched capacitor circuits, comparators etc.
Figure 11. Voltage follower
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Figure 12. Transient Response in a voltage follower
7. FUTURE WORK
Figure 13. Preliminary layout of the proposed design
Figure 13 shows the preliminary layout that has been implemented for the proposed design. The
future work for this research includes the optimization of the layout. Once an efficient layout is
achieved with better routing and placement, the target will be to achieve a robust design. In the
final stage, the design will be implemented on silicon.
13. International Journal of VLSI design Communication Systems (VLSICS) Vol.5, No.4, August 2014
From the design perspective, this design can be improved in terms of GBW by introducing a
second stage. We can also implement compensation technique (in this case RC compensation) to
improve the phase margin.
Other than focusing on solving the previous challenges, we aim to implement and test this
topology for other technology such as 40nm etc. as this design is scaling independent (up to some
extent).
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8. CONCLUSION
It has been demonstrated that the proposed design shows a significant improvement over the
conventional RFC in terms of UGB, GBW and slew rate with nearly the same power
consumption. The additional adaptive biasing circuit added to the RFC, not only improves its
speed and frequency response but also makes the circuit very adaptive to the changes in input
voltage and noise fluctuations. With the RFC itself having an adaptive load, this addition of a
self-adjusting current source makes it a very flexible, adaptive and self-biased circuit. This feature
of the circuit also helps reducing the power consumption by changing currents corresponding to
the changes in the input voltage. The theoretical results were confirmed with good agreement
with the simulation data.
ACKNOWLEDGEMENT
The authors would like to take this opportunity to thank BITS Pilani, Pilani Campus
Administration for providing them with the facilities and resources, which were required to
conduct the research for this paper.
REFERENCES
[1] SU Li QIU Yulin, “Design of a Fully Differential Gain-Boosted Folded-Cascode Op Amp with
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[2] Zhou Qianneng' , Li Hongjuan2, Duan Xiaozhong', and Yang Chong’, “A Two-Stage Amplifier with
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Science and Wireless Technology Conference (CSQRWC), vol. 2, , pp. 1557 – 1560, July 2011.
[3] Hong Chen, Vladimir Milovanovic, Horst Zimmermann “A High Speed Two-Stage Dual-Path
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[4] Rida S. Assaad, Student Member, IEEE, and Jose Silva-Martinez, Senior Member, IEEE “The
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[6] B. Razavi,Design of Analog CMOS Integerated Circuit.New York: McGraw-Hill, pp. 291-333, 2001.
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AUTHORS
Saumya Vij
2014 Graduate in B.E.(Hons.) Electrical and Electronics Engineering and MSc(Hons.)
Economics, BITS Pilani. Currently working as an ASIC Design Engineer at NVidia Pvt.
Ltd., Bangalore
Anu gupta
Presently working as Associate Professor in the Electrical and Electronics Engineering
department of BITS, Pilani. Holds a post graduate degree in Physics from Delhi University,
which was followed up with M.E in Microelectronics from BITS, Pilani. In March 2003,
she obtained her PhD from BITS, Pilani, Rajasthan.
Alok Mittal
2013 Graduate in B.E(Hons.) Electrical and Electronics from BITS, Pilani. Currently
working as Analog Front End design engineer at ST Microelectronics in High speed Links,
NOIDA.