In Very Large Scale Integration (VLSI), interconnect design has become a supreme issue in high speed ICs. With the decreased feature size of CMOS circuits, on-chip interconnect now dominates both circuit delay and power consumption. An eminent technique known as repeater/buffer insertion is used in long interconnections to reduce delay in VLSI circuits. This paper deals with some distinct low power alternative circuits in buffer insertion technique and it proposes two new techniques: Dynamic Threshold Swing Limited (DTSL) and High Dynamic Threshold Swing Limited (HDTSL). The DTSL uses Dynamic Threshold MOSFET configuration. In this gate is tied to the body and it limits the output swing. High Dynamic Threshold Swing Limited (HDTSL) also uses the same configuration along with a high threshold voltage(high-Vth). The simulation results are performed in Cadence virtuoso environment tool using 45nm technology. By simulating and comparing these various repeater circuits along with the proposed circuits it is analyzed that there is trade off among power, delay and Power Delay Product and the 34.66% of power is reduced by using the high- Vth in HDTSL when compared to DTSL.
Application of soft switching in DC-DC converter has achieved a remarkable success in power electronics technology in terms of reduction in switching losses, improve in power density, minimization of electromagnetic interference (EMI) and reduction in the volume of DC-DC converters. Quite a number of soft switching techniques had been reported in the past four decades. This paper aims at providing a review of various soft switching techniques, based on topology, the location of the resonant network, performance characteristics, and principles of operation. In addition, converters area of application, advantages as well as limitations are also highlighted.
STAND-BY LEAKAGE POWER REDUCTION IN NANOSCALE STATIC CMOS VLSI MULTIPLIER CIR...VLSICS Design
In this paper, we performed the comparative analysis of stand-by leakage (when the circuit is idle), delay and dynamic power (when the circuit switches) of the three different parallel digital multiplier circuits implemented with two adder modules and Self Adjustable Voltage level circuit (SVL). The adder modules chosen were 28 transistor-conventional CMOS adder and 10 transistor- Static Energy Recovery CMOS adder (SERF) circuits. The multiplier modules chosen were 4Bits Array, 4bits Carry Save and 4Bits Baugh Wooley multipliers. At first, the circuits were simulated with adder modules without applying the SVL circuit. And secondly, SVL circuit was incorporated in the adder modules for simulation. In all the multiplier architectures chosen, less standby leakage power was observed being consumed by the SERF adder based multipliers applied with SVL circuit. The stand-by leakage power dissipation is 1.16µwatts in Bits array multiplier with SERF Adder applied with SVL vs. 1.39µwatts in the same multiplier with CMOS 28T Adder applied with SVL circuit. It is 1.16µwatts in Carry Save multiplier with SERF Adder applied with
SVL vs. 1.4µwatts in the same multiplier with CMOS 28T Adder applied with SVL circuit. It is 1.67µwatts in Baugh Wooley multiplier with SERF Adder applied with SVl circuit vs. 2.74µwatts in the same multiplier with CMOS 28T Adder applied with SVL circuit.
A novel approach for leakage power reduction techniques in 65nm technologiesVLSICS Design
The rapid progress in semiconductor technology have led the feature sizes of transistor to be shrunk there
by evolution of Deep Sub-Micron (DSM) technology; there by the extremely complex functionality is
enabled to be integrated on a single chip. In the growing market of mobile hand-held devices used all over
the world today, the battery-powered electronic system forms the backbone. To maximize the battery life,
the tremendous computational capacity of portable devices such as notebook computers, personal
communication devices (mobile phones, pocket PCs, PDAs), hearing aids and implantable pacemakers has
to be realized with very low power requirements. Leakage power consumption is one of the major technical
problem in DSM in CMOS circuit design. A comprehensive study and analysis of various leakage power
minimization techniques have been presented in this paper a novel Leakage reduction technique is
developed in Cadence virtuoso in 65nm regim with the combination of stack with sleepy keeper approach
with Low Vth & High Vth which reduces the Average Power with respect Basic Nand Gate 29.43%, 39.88%,
Force Stack 56.98, 63.01%, sleep transistor with Low Vth & High Vth 13.90, 26.61% & 33.03%, 75.24%
with respect to sleepy Keeper 93.70, 56.01% of Average Power is saved.
HIPDN: A POWER DISTRIBUTION NETWORK FOR EFFICIENT ON-CHIP POWER DELIVERY AND ...csijjournal
While the semiconductor roadmap is about to locate in 16nm-FinFET (or Tri-Gate) era, power budget is being entitled major concern to contemporary electronics and future nanometer devices. In this work, a new Power
Distribution Network (PDN), referred to as HiPDN, is disclosed for further fine-grain power saving and higher power integrity for supplies in multi-voltage domains. The proposed PDN employs two types of Integrated
Voltage Regulators (IVR) with large difference in voltage regulation range. By combining the proposed PDN with the Adaptive Voltage Scaling (AVS) technique, voltage guard-bands can be mitigated to lower the safety
margin for voltage variation, i.e., reducing DC set points, thereby effectively decreasing the overhead of power dissipation. In comparison to existing PDNs, theoretical results with a simple equivalent circuit model
demonstrate an increase of power saving achieved by HiPDN, thus, allowing longer battery life. Finally, this work provides an on-chip power delivery methodology to improve power efficiency and a simple model to
evaluate a PDN and its IVRs.
Design of 64 bit SRAM using Lector Technique for Low Leakage Power with Read ...IOSRJVSP
: In complementary metal oxide semiconductor (CMOS) the power dissipation predominantly comprises of dynamic as well as static power. Prior to introduction of “Deep submicron technologies” it is observed that in case of technology process with feature size larger than 1micro meter, the consumption of dynamic power out of the overall power consumption of any circuit is more than 90%,while that of static power is negligible. But in the present deep submicron technologies in order to, reduce the dynamic power consumption in VLSI circuits, the power supply is being scaled down, keeping in view the principle that the dynamic power dissipated is directly proportional to the square of the supply voltage (Vdd).The threshold voltage also needs to be reduced since the supply voltage is scaled down. Overcoming the inherent limitations in the existing method for leakage power reduction, The Lector (Leakage controlled transistor) technique which works efficiently both in active and idle states of the circuit and results in better leakage power reduction is now proposed. The proposed system presents the analysis of power on “64-bit SRAM array using leakage controlled transistor technique
Sub-Threshold Leakage Current Reduction Techniques In VLSI Circuits -A SurveyIJERA Editor
There is an increasing demand for portable devices powered up by battery, this led the manufacturers of
semiconductor technology to scale down the feature size which results in reduction in threshold voltage and
enables the complex functionality on a single chip. By scaling down the feature size the dynamic power
dissipation has no effect but the static power dissipation has become equal or more than that of Dynamic power
dissipation. So in recent CMOS technologies static power dissipation i.e. power dissipation due to leakage
current has become a challenging area for VLSI chip designers. In order to prolong the battery life and maintain
reliability of circuit, leakage current reduction is the primary goal. A basic overview of techniques used for
reduction of sub-threshold leakages is discussed in this paper. Based on the surveyed techniques, one would be
able to choose required and apt leakage reduction technique.
Application of soft switching in DC-DC converter has achieved a remarkable success in power electronics technology in terms of reduction in switching losses, improve in power density, minimization of electromagnetic interference (EMI) and reduction in the volume of DC-DC converters. Quite a number of soft switching techniques had been reported in the past four decades. This paper aims at providing a review of various soft switching techniques, based on topology, the location of the resonant network, performance characteristics, and principles of operation. In addition, converters area of application, advantages as well as limitations are also highlighted.
STAND-BY LEAKAGE POWER REDUCTION IN NANOSCALE STATIC CMOS VLSI MULTIPLIER CIR...VLSICS Design
In this paper, we performed the comparative analysis of stand-by leakage (when the circuit is idle), delay and dynamic power (when the circuit switches) of the three different parallel digital multiplier circuits implemented with two adder modules and Self Adjustable Voltage level circuit (SVL). The adder modules chosen were 28 transistor-conventional CMOS adder and 10 transistor- Static Energy Recovery CMOS adder (SERF) circuits. The multiplier modules chosen were 4Bits Array, 4bits Carry Save and 4Bits Baugh Wooley multipliers. At first, the circuits were simulated with adder modules without applying the SVL circuit. And secondly, SVL circuit was incorporated in the adder modules for simulation. In all the multiplier architectures chosen, less standby leakage power was observed being consumed by the SERF adder based multipliers applied with SVL circuit. The stand-by leakage power dissipation is 1.16µwatts in Bits array multiplier with SERF Adder applied with SVL vs. 1.39µwatts in the same multiplier with CMOS 28T Adder applied with SVL circuit. It is 1.16µwatts in Carry Save multiplier with SERF Adder applied with
SVL vs. 1.4µwatts in the same multiplier with CMOS 28T Adder applied with SVL circuit. It is 1.67µwatts in Baugh Wooley multiplier with SERF Adder applied with SVl circuit vs. 2.74µwatts in the same multiplier with CMOS 28T Adder applied with SVL circuit.
A novel approach for leakage power reduction techniques in 65nm technologiesVLSICS Design
The rapid progress in semiconductor technology have led the feature sizes of transistor to be shrunk there
by evolution of Deep Sub-Micron (DSM) technology; there by the extremely complex functionality is
enabled to be integrated on a single chip. In the growing market of mobile hand-held devices used all over
the world today, the battery-powered electronic system forms the backbone. To maximize the battery life,
the tremendous computational capacity of portable devices such as notebook computers, personal
communication devices (mobile phones, pocket PCs, PDAs), hearing aids and implantable pacemakers has
to be realized with very low power requirements. Leakage power consumption is one of the major technical
problem in DSM in CMOS circuit design. A comprehensive study and analysis of various leakage power
minimization techniques have been presented in this paper a novel Leakage reduction technique is
developed in Cadence virtuoso in 65nm regim with the combination of stack with sleepy keeper approach
with Low Vth & High Vth which reduces the Average Power with respect Basic Nand Gate 29.43%, 39.88%,
Force Stack 56.98, 63.01%, sleep transistor with Low Vth & High Vth 13.90, 26.61% & 33.03%, 75.24%
with respect to sleepy Keeper 93.70, 56.01% of Average Power is saved.
HIPDN: A POWER DISTRIBUTION NETWORK FOR EFFICIENT ON-CHIP POWER DELIVERY AND ...csijjournal
While the semiconductor roadmap is about to locate in 16nm-FinFET (or Tri-Gate) era, power budget is being entitled major concern to contemporary electronics and future nanometer devices. In this work, a new Power
Distribution Network (PDN), referred to as HiPDN, is disclosed for further fine-grain power saving and higher power integrity for supplies in multi-voltage domains. The proposed PDN employs two types of Integrated
Voltage Regulators (IVR) with large difference in voltage regulation range. By combining the proposed PDN with the Adaptive Voltage Scaling (AVS) technique, voltage guard-bands can be mitigated to lower the safety
margin for voltage variation, i.e., reducing DC set points, thereby effectively decreasing the overhead of power dissipation. In comparison to existing PDNs, theoretical results with a simple equivalent circuit model
demonstrate an increase of power saving achieved by HiPDN, thus, allowing longer battery life. Finally, this work provides an on-chip power delivery methodology to improve power efficiency and a simple model to
evaluate a PDN and its IVRs.
Design of 64 bit SRAM using Lector Technique for Low Leakage Power with Read ...IOSRJVSP
: In complementary metal oxide semiconductor (CMOS) the power dissipation predominantly comprises of dynamic as well as static power. Prior to introduction of “Deep submicron technologies” it is observed that in case of technology process with feature size larger than 1micro meter, the consumption of dynamic power out of the overall power consumption of any circuit is more than 90%,while that of static power is negligible. But in the present deep submicron technologies in order to, reduce the dynamic power consumption in VLSI circuits, the power supply is being scaled down, keeping in view the principle that the dynamic power dissipated is directly proportional to the square of the supply voltage (Vdd).The threshold voltage also needs to be reduced since the supply voltage is scaled down. Overcoming the inherent limitations in the existing method for leakage power reduction, The Lector (Leakage controlled transistor) technique which works efficiently both in active and idle states of the circuit and results in better leakage power reduction is now proposed. The proposed system presents the analysis of power on “64-bit SRAM array using leakage controlled transistor technique
Sub-Threshold Leakage Current Reduction Techniques In VLSI Circuits -A SurveyIJERA Editor
There is an increasing demand for portable devices powered up by battery, this led the manufacturers of
semiconductor technology to scale down the feature size which results in reduction in threshold voltage and
enables the complex functionality on a single chip. By scaling down the feature size the dynamic power
dissipation has no effect but the static power dissipation has become equal or more than that of Dynamic power
dissipation. So in recent CMOS technologies static power dissipation i.e. power dissipation due to leakage
current has become a challenging area for VLSI chip designers. In order to prolong the battery life and maintain
reliability of circuit, leakage current reduction is the primary goal. A basic overview of techniques used for
reduction of sub-threshold leakages is discussed in this paper. Based on the surveyed techniques, one would be
able to choose required and apt leakage reduction technique.
LEAKAGE POWER REDUCTION AND ANALYSIS OF CMOS SEQUENTIAL CIRCUITSVLSICS Design
A significant portion of the total power consumption in high performance digital circuits in deep submicron regime is mainly due to leakage power. Leakage is the only source of power consumption in an idle circuit. Therefore it is important to reduce leakage power in portable systems. In this paper two techniques such as transistor stacking and self-adjustable voltage level circuit for reducing leakage power in sequential circuits are proposed. This work analyses the power and delay of three different types of D flip-flops using pass transistors, transmission gates and gate diffusion input gates. . All the circuits are simulated with and without the application of leakage reduction techniques. Simulation results show that the proposed pass transistor based D flip-flop using self-adjustable voltage level circuit has the least leakage power dissipation of 9.13nW with a delay of 77 nS. The circuits are simulated with MOSFET models of level 54 using HSPICE in 90 nm process technology.
A low quiescent current low dropout voltage regulator with self-compensationjournalBEEI
This paper proposed a low quiescent current low-dropout voltage regulator (LDO) with self-compensation loop stability. This LDO is designed for Silicon-on-Chip (SoC) application without off-chip compensation capacitor. Worst case loop stability phenomenon happen when LDO output load current (Iload) is zero. The second pole frequency decreased tremendously towards unity-gain frequency (UGF) and compromise loop stability. To prevent this, additional current is needed to keep the output in low impedance in order to maintain second pole frequency. As Iload slowly increases, the unneeded additional current can be further reduced. This paper presents a circuit which performed self-reduction on this current by sensing the Iload. On top of that, a self-compensation circuit technique is proposed where loop stability is selfattained when Iload reduced below 100μA. In this technique, unity-gain frequency (UGF) will be decreaed and move away from second pole in order to attain loop stability. The decreased of UGF is done by reducing the total gain while maintaining the dominant pole frequency. This technique has also further reduced the total quiescent current and improved the LDO’s efficiency. The proposed LDO exhibits low quiescent current 9.4μA and 17.7μA, at Iload zero and full load 100mA respectively. The supply voltage for this LDO is 1.2V with 200mV drop-out voltage. The design is validated using 0.13μm CMOS process technology.
Design of vco using current mode logic with low supply sensitivityeSAT Journals
Abstract The function of an oscillator is to convert dc energy into RF. Voltage Controlled Oscillator (VCO) is a type of oscillator whose output frequency can be varied by a control voltage. Here the VCO is designed using 0.18μm CMOS-RF technology using current mode logic. The Current mode logic is the fastest logic and is mainly used in Clock and Data Recovery applications. Current mode logic (CML) is a differential logic and provides noise immunity. Using the proposed design the current mode logic VCO operates with a supply voltage of 1.8 V and frequency varies from 2 MHz to 2.5 MHz. Its normalized supply sensitivity is 0.976 and optimum sensitivity is 0.966. Keywords: VCO, Supply sensitivity, CML, Ring oscillator.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
NOVEL SLEEP TRANSISTOR TECHNIQUES FOR LOW LEAKAGE POWER PERIPHERAL CIRCUITSVLSICS Design
Static power consumption is a major concern in nanometre technologies. Along with technology scaling down and higher operating speeds of CMOS VLSI circuits, the leakage power is getting enhanced. As process geometries are becoming smaller, device density increases and threshold voltage as well as oxide thickness decrease to keep pace with performance. Two novel circuit techniques for leakage current reduction in inverters with and without state retention property are presented in this work. The power dissipation during inactive (standby) mode of operation can be significantly reduced compared to traditional power gating methods by these circuit techniques. The proposed circuit techniques are applied to inverters and the results are compared with earlier inverter leakage minimization techniques. Inverter
buffer chains are designed using new state retention low leakage technique and found to be dissipating lower power with state retention. All low leakage inverters are designed and simulated in cadence design environment using 90 nm technology files. The leakage power during sleep mode is found to be better by X 63 times for novel method. The total power dissipation has also reduced by a factor of X 3.5, compared to earlier sleepy keeper technique. The state retention feature is also good compared to earlier leakage power reduction methodologies.
Energy efficient and high speed domino logic circuitsIJERA Editor
Domino CMOS circuit family finds a wide variety of application in microprocessors due to low device count and high speed.In this paper, various conventional and proposed designs for low leakage and high speed wide fan-in domino circuits are reviewed. The techniques used in the paper reduces the total power dissipation and delay by 25% and 58% respectively as compared to the conventional footed domino logic circuit. Simulations are performed on tanner tool at 65nm technology for 16 input OR gate.
a report on Off-line Fault Localization Technique on HVDC Submarine Cable via Time-Frequency Domain Reflectometry.
other fault tech like TDR, FDR included.
Ground Bounce Noise Reduction in Vlsi CircuitsIJERA Editor
Scaling of devices in CMOS technology leads to increase in parameter like Ground bounce
noise, Leakage current, average power dissipation and short channel effect. FinFET are the promising substitute
to replace CMOS. Ground bounce noise is produced when power gating circuit goes from SLEEP to ACTIVE
mode transition. FinFET based designs are compared with MOSFET based designs on basis of different
parameter like Ground bounce noise, leakage current and average power dissipation. HSPICE is the software
tool used for simulation and circuit design.
Comparative Performance Analysis of XORXNOR Function Based High-Speed CMOS Fu...VLSICS Design
This paper presents comparative study of high-speed, low-power and low voltage full adder circuits. Our approach is based on XOR-XNOR design full adder circuits in a single unit. A low power and high performance 9T full adder cell using a design style called “XOR (3T)” is discussed. The designed circuit commands a high degree of regularity and symmetric higher density than the conventional CMOS design style as well as it lowers power consumption by using XOR (3T) logic circuits. Gate Diffusion Input (GDI) technique of low-power digital combinatorial circuit design is also described. This technique helps in reducing the power consumption and the area of digital circuits while maintaining low complexity of logic design. This paper analyses, evaluates and compares the performance of various adder circuits. Several simulations conducted using different voltage supplies, load capacitors and temperature variation demonstrate the superiority of the XOR (3T) based full adder designs in term of delay, power and power delay product (PDP) compared to the other full adder circuits. Simulation results illustrate the superiority of the designed adder circuits against the conventional CMOS, TG and Hybrid full adder circuits in terms of power, delay and power delay product (PDP).
A Novel Structure of a Wideband Zero-bias Power Limiter for ISM BandTELKOMNIKA JOURNAL
In this paper, a new broadband microwave microstrip power limiter is designed and realized. The
Power Limiter is based on microstrip technology integrating a Zero Bias commercial Schottky diodes
HSMS2820.The power limiter is optimized and validated in two steps. The enhanced and achieved circuit
is obtained by concatenating two basic structures. The final circuit was validated into simulation by using
ADS solver. Finally this circuit was realized and tested. Simulation and measurement results are in a good
agreement. The final circuit achieves a limiting rate of 14 dB with a threshold input power level of 0 dBm
until a maximum input power level of 30 dBm.
Static power optimization using dual sub threshold supply voltages in digital...VLSICS Design
Power dissipation in high performance systems requi
res more expensive packaging. In this situation, lo
w
power VLSI design has assumed great importance as a
n active and rapidly developing field. As the densi
ty
and operating speed of CMOS VLSI chip increases, st
atic power dissipation becomes more significant. Th
is
is due to the leakage current when the transistor i
s off this is threshold voltage dependent. This can
be
observed in the combinational and sequential circui
ts. Static power reduction techniques are achieved
by
means of operating the transistor either in Cut-off
or in Saturation region completely and avoiding th
e
clock in unnecessary circuits. In this work, “Dual
sub-threshold voltage supply” technique is used to
operate the transistor under off state or either in
on state by applying some voltage at the gate of t
he MOS
transistor. This static power reduction technique i
s to digital circuits, so that the power dissipatio
n is
reduced and the performance of the circuit is incre
ased. The designed circuits can be simulated by usi
ng
Mentor Graphics Backend Tool
Optimal Body Biasing Technique for CMOS Tapered Buffer IJEEE
This paper represents Fixed Body Biased CMOS Tapered Buffer which is designed to minimize the average power dissipation across large capacitive load. The implementation of Reverse Body Bias (RBB) in the proposed Buffer chain is to vary Vth value of NMOS in the first stage. And with the increase in Vth /sub-threshold leakage current and power has been reduced. The technology constraints on the threshold voltage does not allow designer to set high threshold voltage for MOS devices. Hence, this was found that in proposed circuit that when optimal Reverse Body Bias value is set within (0.2 VDD to 0.4 VDD) range, the average power dissipation across capacitive load reduces to 82.2 % at very less penalty in delay. Thus CMOS buffer designers can use the proposed method to vary Vth while keeping VDD constant, which could improve the performance parameters of Tapered Buffer. The proposed analysis is verified by simulating the 3-stage tapered buffer schematics using standard 180nm CMOS technology in Cadence environment.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
NOVEL SLEEP TRANSISTOR TECHNIQUES FOR LOW LEAKAGE POWER PERIPHERAL CIRCUITSVLSICS Design
Static power consumption is a major concern in nanometre technologies. Along with technology scaling down and higher operating speeds of CMOS VLSI circuits, the leakage power is getting enhanced. As process geometries are becoming smaller, device density increases and threshold voltage as well as oxide thickness decrease to keep pace with performance. Two novel circuit techniques for leakage current reduction in inverters with and without state retention property are presented in this work. The power dissipation during inactive (standby) mode of operation can be significantly reduced compared to traditional power gating methods by these circuit techniques. The proposed circuit techniques are applied to inverters and the results are compared with earlier inverter leakage minimization techniques. Inverter
buffer chains are designed using new state retention low leakage technique and found to be dissipating lower power with state retention. All low leakage inverters are designed and simulated in cadence design environment using 90 nm technology files. The leakage power during sleep mode is found to be better by X 63 times for novel method. The total power dissipation has also reduced by a factor of X 3.5, compared to earlier sleepy keeper technique. The state retention feature is also good compared to earlier leakage power reduction methodologies.
A DAPTIVE S UPPLY V OLTAGE M ANAGEMENT F OR L OW P OWER L OGIC C IRCU...VLSICS Design
With the rise in demand of portable hand held devic
es and with the rise in application of wireless sen
sor
networks and RFID reduction of total power consumpt
ion has become a necessity. To save power we
operate the logic circuitry of our devices at sub-t
hreshold. In sub-threshold the drain current is
exponentially dependent on the threshold voltage he
nce the threshold variation causes profound variati
on
of I
ON
and I
OFF
the ratio of which affect the speed of a circuit d
rastically. So to mitigate this problem we
present a adaptive power management circuit which w
ill determine the minimum required supply voltage
to meet the timing requirement. Also to reduce the
power overhead and avoid bulky coil and EMI noise
we used the switch capacitor power regulator to reg
ulate and manage power instead of linear dropout
(LDO) and Inductor base switch mode power converter
Design of ultra low power 8 channel analog multiplexer using dynamic threshol...VLSICS Design
The design of an ultra low voltage, low power high
speed 8 channel Analog multiplexer in 180nm CMOS
technology is presented. A modified transmission ga
te using a dynamic threshold voltage MOSFET
(DTMOS
)
is employed in the design. The design is optimized
with respect to critical requirements like short
switching time, low power dissipation, good lineari
ty and high dynamic range with an operating voltage
of
0.4V. The ON and OFF resistances achieved are 32 oh
ms and 10Mohms respectively with a switching
speed of 10MHz. The power dissipation obtained is a
round 2.65uW for a dynamic range of 1uV to 0.4V.
A low power front end analog multiplexing unit for 12 lead ecg signal acquisi...VLSICS Design
The design of CMOS analog circuitry for acquiring 12 lead ECG is presented. The existing methods
employ separate multiplexers and associated circuitry for signal acquisition operating at typical voltage of
± 5V. The proposed system employs dynamic threshold logic to achieve low power, wide dynamic range
good linearity with a supply voltage of 0.4V. The power dissipation obtained was 22.12μW. Utilizing the
dynamic threshold logic the proposed circuitry is implemented with 0.18μm CMOS technology. This ECG
signal processor is highly suitable for wearable applications of long term cardiac monitoring.
VOLTAGE STACKING FOR SIMPLIFYING POWER MANAGEMENT IN ASYNCHRONOUS CIRCUITSVLSICS Design
Multiple power domains on a single integrated circuit (IC) are becoming more common due to the increasing complexity of systems on chips (SoCs) as process nodes continue to get smaller. Supplying the correct voltage to each domain requires the use of multiple voltage converters that occupy substantial
space either on-chip or off-chip and introduce additional power loss in the conversions. In this paper, an asynchronous paradigm called Multi-Threshold NULL Convention Logic (MTNCL) is used to create a “stacked” architecture that reduces the number of converters needed and thereby mitigating the
aforementioned problems. In this architecture, the MTNCL circuits are stacked between a multiple of VDD
and GND, where simple control mechanisms alleviate the induced dynamic range fluctuation problem. The GLOBALFOUNDRIES 32nm Silicon-on-Insulator (SOI) CMOS process is used to evaluate and analyze the theoretical effects of parasitic extracted physical implementations in stacking different circuits running different workloads. These results show that the “stacked” architecture introduce negligible overhead
compared to the operation of the individual circuits while substantially alleviating the need for voltage converters, which in turn reduces the overall power consumption of the system.
LEAKAGE POWER REDUCTION AND ANALYSIS OF CMOS SEQUENTIAL CIRCUITSVLSICS Design
A significant portion of the total power consumption in high performance digital circuits in deep submicron regime is mainly due to leakage power. Leakage is the only source of power consumption in an idle circuit. Therefore it is important to reduce leakage power in portable systems. In this paper two techniques such as transistor stacking and self-adjustable voltage level circuit for reducing leakage power in sequential circuits are proposed. This work analyses the power and delay of three different types of D flip-flops using pass transistors, transmission gates and gate diffusion input gates. . All the circuits are simulated with and without the application of leakage reduction techniques. Simulation results show that the proposed pass transistor based D flip-flop using self-adjustable voltage level circuit has the least leakage power dissipation of 9.13nW with a delay of 77 nS. The circuits are simulated with MOSFET models of level 54 using HSPICE in 90 nm process technology.
A low quiescent current low dropout voltage regulator with self-compensationjournalBEEI
This paper proposed a low quiescent current low-dropout voltage regulator (LDO) with self-compensation loop stability. This LDO is designed for Silicon-on-Chip (SoC) application without off-chip compensation capacitor. Worst case loop stability phenomenon happen when LDO output load current (Iload) is zero. The second pole frequency decreased tremendously towards unity-gain frequency (UGF) and compromise loop stability. To prevent this, additional current is needed to keep the output in low impedance in order to maintain second pole frequency. As Iload slowly increases, the unneeded additional current can be further reduced. This paper presents a circuit which performed self-reduction on this current by sensing the Iload. On top of that, a self-compensation circuit technique is proposed where loop stability is selfattained when Iload reduced below 100μA. In this technique, unity-gain frequency (UGF) will be decreaed and move away from second pole in order to attain loop stability. The decreased of UGF is done by reducing the total gain while maintaining the dominant pole frequency. This technique has also further reduced the total quiescent current and improved the LDO’s efficiency. The proposed LDO exhibits low quiescent current 9.4μA and 17.7μA, at Iload zero and full load 100mA respectively. The supply voltage for this LDO is 1.2V with 200mV drop-out voltage. The design is validated using 0.13μm CMOS process technology.
Design of vco using current mode logic with low supply sensitivityeSAT Journals
Abstract The function of an oscillator is to convert dc energy into RF. Voltage Controlled Oscillator (VCO) is a type of oscillator whose output frequency can be varied by a control voltage. Here the VCO is designed using 0.18μm CMOS-RF technology using current mode logic. The Current mode logic is the fastest logic and is mainly used in Clock and Data Recovery applications. Current mode logic (CML) is a differential logic and provides noise immunity. Using the proposed design the current mode logic VCO operates with a supply voltage of 1.8 V and frequency varies from 2 MHz to 2.5 MHz. Its normalized supply sensitivity is 0.976 and optimum sensitivity is 0.966. Keywords: VCO, Supply sensitivity, CML, Ring oscillator.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
NOVEL SLEEP TRANSISTOR TECHNIQUES FOR LOW LEAKAGE POWER PERIPHERAL CIRCUITSVLSICS Design
Static power consumption is a major concern in nanometre technologies. Along with technology scaling down and higher operating speeds of CMOS VLSI circuits, the leakage power is getting enhanced. As process geometries are becoming smaller, device density increases and threshold voltage as well as oxide thickness decrease to keep pace with performance. Two novel circuit techniques for leakage current reduction in inverters with and without state retention property are presented in this work. The power dissipation during inactive (standby) mode of operation can be significantly reduced compared to traditional power gating methods by these circuit techniques. The proposed circuit techniques are applied to inverters and the results are compared with earlier inverter leakage minimization techniques. Inverter
buffer chains are designed using new state retention low leakage technique and found to be dissipating lower power with state retention. All low leakage inverters are designed and simulated in cadence design environment using 90 nm technology files. The leakage power during sleep mode is found to be better by X 63 times for novel method. The total power dissipation has also reduced by a factor of X 3.5, compared to earlier sleepy keeper technique. The state retention feature is also good compared to earlier leakage power reduction methodologies.
Energy efficient and high speed domino logic circuitsIJERA Editor
Domino CMOS circuit family finds a wide variety of application in microprocessors due to low device count and high speed.In this paper, various conventional and proposed designs for low leakage and high speed wide fan-in domino circuits are reviewed. The techniques used in the paper reduces the total power dissipation and delay by 25% and 58% respectively as compared to the conventional footed domino logic circuit. Simulations are performed on tanner tool at 65nm technology for 16 input OR gate.
a report on Off-line Fault Localization Technique on HVDC Submarine Cable via Time-Frequency Domain Reflectometry.
other fault tech like TDR, FDR included.
Ground Bounce Noise Reduction in Vlsi CircuitsIJERA Editor
Scaling of devices in CMOS technology leads to increase in parameter like Ground bounce
noise, Leakage current, average power dissipation and short channel effect. FinFET are the promising substitute
to replace CMOS. Ground bounce noise is produced when power gating circuit goes from SLEEP to ACTIVE
mode transition. FinFET based designs are compared with MOSFET based designs on basis of different
parameter like Ground bounce noise, leakage current and average power dissipation. HSPICE is the software
tool used for simulation and circuit design.
Comparative Performance Analysis of XORXNOR Function Based High-Speed CMOS Fu...VLSICS Design
This paper presents comparative study of high-speed, low-power and low voltage full adder circuits. Our approach is based on XOR-XNOR design full adder circuits in a single unit. A low power and high performance 9T full adder cell using a design style called “XOR (3T)” is discussed. The designed circuit commands a high degree of regularity and symmetric higher density than the conventional CMOS design style as well as it lowers power consumption by using XOR (3T) logic circuits. Gate Diffusion Input (GDI) technique of low-power digital combinatorial circuit design is also described. This technique helps in reducing the power consumption and the area of digital circuits while maintaining low complexity of logic design. This paper analyses, evaluates and compares the performance of various adder circuits. Several simulations conducted using different voltage supplies, load capacitors and temperature variation demonstrate the superiority of the XOR (3T) based full adder designs in term of delay, power and power delay product (PDP) compared to the other full adder circuits. Simulation results illustrate the superiority of the designed adder circuits against the conventional CMOS, TG and Hybrid full adder circuits in terms of power, delay and power delay product (PDP).
A Novel Structure of a Wideband Zero-bias Power Limiter for ISM BandTELKOMNIKA JOURNAL
In this paper, a new broadband microwave microstrip power limiter is designed and realized. The
Power Limiter is based on microstrip technology integrating a Zero Bias commercial Schottky diodes
HSMS2820.The power limiter is optimized and validated in two steps. The enhanced and achieved circuit
is obtained by concatenating two basic structures. The final circuit was validated into simulation by using
ADS solver. Finally this circuit was realized and tested. Simulation and measurement results are in a good
agreement. The final circuit achieves a limiting rate of 14 dB with a threshold input power level of 0 dBm
until a maximum input power level of 30 dBm.
Static power optimization using dual sub threshold supply voltages in digital...VLSICS Design
Power dissipation in high performance systems requi
res more expensive packaging. In this situation, lo
w
power VLSI design has assumed great importance as a
n active and rapidly developing field. As the densi
ty
and operating speed of CMOS VLSI chip increases, st
atic power dissipation becomes more significant. Th
is
is due to the leakage current when the transistor i
s off this is threshold voltage dependent. This can
be
observed in the combinational and sequential circui
ts. Static power reduction techniques are achieved
by
means of operating the transistor either in Cut-off
or in Saturation region completely and avoiding th
e
clock in unnecessary circuits. In this work, “Dual
sub-threshold voltage supply” technique is used to
operate the transistor under off state or either in
on state by applying some voltage at the gate of t
he MOS
transistor. This static power reduction technique i
s to digital circuits, so that the power dissipatio
n is
reduced and the performance of the circuit is incre
ased. The designed circuits can be simulated by usi
ng
Mentor Graphics Backend Tool
Optimal Body Biasing Technique for CMOS Tapered Buffer IJEEE
This paper represents Fixed Body Biased CMOS Tapered Buffer which is designed to minimize the average power dissipation across large capacitive load. The implementation of Reverse Body Bias (RBB) in the proposed Buffer chain is to vary Vth value of NMOS in the first stage. And with the increase in Vth /sub-threshold leakage current and power has been reduced. The technology constraints on the threshold voltage does not allow designer to set high threshold voltage for MOS devices. Hence, this was found that in proposed circuit that when optimal Reverse Body Bias value is set within (0.2 VDD to 0.4 VDD) range, the average power dissipation across capacitive load reduces to 82.2 % at very less penalty in delay. Thus CMOS buffer designers can use the proposed method to vary Vth while keeping VDD constant, which could improve the performance parameters of Tapered Buffer. The proposed analysis is verified by simulating the 3-stage tapered buffer schematics using standard 180nm CMOS technology in Cadence environment.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
NOVEL SLEEP TRANSISTOR TECHNIQUES FOR LOW LEAKAGE POWER PERIPHERAL CIRCUITSVLSICS Design
Static power consumption is a major concern in nanometre technologies. Along with technology scaling down and higher operating speeds of CMOS VLSI circuits, the leakage power is getting enhanced. As process geometries are becoming smaller, device density increases and threshold voltage as well as oxide thickness decrease to keep pace with performance. Two novel circuit techniques for leakage current reduction in inverters with and without state retention property are presented in this work. The power dissipation during inactive (standby) mode of operation can be significantly reduced compared to traditional power gating methods by these circuit techniques. The proposed circuit techniques are applied to inverters and the results are compared with earlier inverter leakage minimization techniques. Inverter
buffer chains are designed using new state retention low leakage technique and found to be dissipating lower power with state retention. All low leakage inverters are designed and simulated in cadence design environment using 90 nm technology files. The leakage power during sleep mode is found to be better by X 63 times for novel method. The total power dissipation has also reduced by a factor of X 3.5, compared to earlier sleepy keeper technique. The state retention feature is also good compared to earlier leakage power reduction methodologies.
A DAPTIVE S UPPLY V OLTAGE M ANAGEMENT F OR L OW P OWER L OGIC C IRCU...VLSICS Design
With the rise in demand of portable hand held devic
es and with the rise in application of wireless sen
sor
networks and RFID reduction of total power consumpt
ion has become a necessity. To save power we
operate the logic circuitry of our devices at sub-t
hreshold. In sub-threshold the drain current is
exponentially dependent on the threshold voltage he
nce the threshold variation causes profound variati
on
of I
ON
and I
OFF
the ratio of which affect the speed of a circuit d
rastically. So to mitigate this problem we
present a adaptive power management circuit which w
ill determine the minimum required supply voltage
to meet the timing requirement. Also to reduce the
power overhead and avoid bulky coil and EMI noise
we used the switch capacitor power regulator to reg
ulate and manage power instead of linear dropout
(LDO) and Inductor base switch mode power converter
Design of ultra low power 8 channel analog multiplexer using dynamic threshol...VLSICS Design
The design of an ultra low voltage, low power high
speed 8 channel Analog multiplexer in 180nm CMOS
technology is presented. A modified transmission ga
te using a dynamic threshold voltage MOSFET
(DTMOS
)
is employed in the design. The design is optimized
with respect to critical requirements like short
switching time, low power dissipation, good lineari
ty and high dynamic range with an operating voltage
of
0.4V. The ON and OFF resistances achieved are 32 oh
ms and 10Mohms respectively with a switching
speed of 10MHz. The power dissipation obtained is a
round 2.65uW for a dynamic range of 1uV to 0.4V.
A low power front end analog multiplexing unit for 12 lead ecg signal acquisi...VLSICS Design
The design of CMOS analog circuitry for acquiring 12 lead ECG is presented. The existing methods
employ separate multiplexers and associated circuitry for signal acquisition operating at typical voltage of
± 5V. The proposed system employs dynamic threshold logic to achieve low power, wide dynamic range
good linearity with a supply voltage of 0.4V. The power dissipation obtained was 22.12μW. Utilizing the
dynamic threshold logic the proposed circuitry is implemented with 0.18μm CMOS technology. This ECG
signal processor is highly suitable for wearable applications of long term cardiac monitoring.
VOLTAGE STACKING FOR SIMPLIFYING POWER MANAGEMENT IN ASYNCHRONOUS CIRCUITSVLSICS Design
Multiple power domains on a single integrated circuit (IC) are becoming more common due to the increasing complexity of systems on chips (SoCs) as process nodes continue to get smaller. Supplying the correct voltage to each domain requires the use of multiple voltage converters that occupy substantial
space either on-chip or off-chip and introduce additional power loss in the conversions. In this paper, an asynchronous paradigm called Multi-Threshold NULL Convention Logic (MTNCL) is used to create a “stacked” architecture that reduces the number of converters needed and thereby mitigating the
aforementioned problems. In this architecture, the MTNCL circuits are stacked between a multiple of VDD
and GND, where simple control mechanisms alleviate the induced dynamic range fluctuation problem. The GLOBALFOUNDRIES 32nm Silicon-on-Insulator (SOI) CMOS process is used to evaluate and analyze the theoretical effects of parasitic extracted physical implementations in stacking different circuits running different workloads. These results show that the “stacked” architecture introduce negligible overhead
compared to the operation of the individual circuits while substantially alleviating the need for voltage converters, which in turn reduces the overall power consumption of the system.
VOLTAGE STACKING FOR SIMPLIFYING POWER MANAGEMENT IN ASYNCHRONOUS CIRCUITSVLSICS Design
Multiple power domains on a single integrated circuit (IC) are becoming more common due to the increasing complexity of systems on chips (SoCs) as process nodes continue to get smaller. Supplying the correct voltage to each domain requires the use of multiple voltage converters that occupy substantial space either on-chip or off-chip and introduce additional power loss in the conversions. In this paper, an asynchronous paradigm called Multi-Threshold NULL Convention Logic (MTNCL) is used to create a “stacked” architecture that reduces the number of converters needed and thereby mitigating the aforementioned problems. In this architecture, the MTNCL circuits are stacked between a multiple of VDD and GND, where simple control mechanisms alleviate the induced dynamic range fluctuation problem. The GLOBALFOUNDRIES 32nm Silicon-on-Insulator (SOI) CMOS process is used to evaluate and analyze the theoretical effects of parasitic extracted physical implementations in stacking different circuits running different workloads. These results show that the “stacked” architecture introduce negligible overhead compared to the operation of the individual circuits while substantially alleviating the need for voltage converters, which in turn reduces the overall power consumption of the system.
VOLTAGE STACKING FOR SIMPLIFYING POWER MANAGEMENT IN ASYNCHRONOUS CIRCUITSVLSICS Design
Multiple power domains on a single integrated circuit (IC) are becoming more common due to the increasing complexity of systems on chips (SoCs) as process nodes continue to get smaller. Supplying the correct voltage to each domain requires the use of multiple voltage converters that occupy substantial
space either on-chip or off-chip and introduce additional power loss in the conversions. In this paper, an asynchronous paradigm called Multi-Threshold NULL Convention Logic (MTNCL) is used to create a “stacked” architecture that reduces the number of converters needed and thereby mitigating the
aforementioned problems. In this architecture, the MTNCL circuits are stacked between a multiple of VDD and GND, where simple control mechanisms alleviate the induced dynamic range fluctuation problem. The GLOBALFOUNDRIES 32nm Silicon-on-Insulator (SOI) CMOS process is used to evaluate and analyze the theoretical effects of parasitic extracted physical implementations in stacking different circuits running
different workloads. These results show that the “stacked” architecture introduce negligible overhead compared to the operation of the individual circuits while substantially alleviating the need for voltage converters, which in turn reduces the overall power consumption of the system.
ANALYSIS OF CMOS AND MTCMOS CIRCUITS USING 250 NANO METER TECHNOLOGYcscpconf
The low-power consumption with less delay time has become an important issue in the recent
trends of VLSI. In these days, the low power systems with high speed are highly preferable
everywhere. Designers need to understand how low-power techniques affect performance
attributes, and have to choose a set of techniques that are consistent with these attributes .The
main objective of this paper is to describe, how to achieve low power consumption with
approximately same delay time in a single circuit. In this paper, we make circuits with CMOS
and MTCMOS techniques and check out its power and delay characteristics. The circuits
designed using MTCMOS technique gives least power consumption.
All the pre-layout simulations have been performed at 250nm technology on tanner EDA tool.
Analysis of CMOS and MTCMOS Circuits Using 250 Nano Meter Technology csandit
The low-power consumption with less delay time has become an important issue in the recent
trends of VLSI. In these days, the low power systems with high speed are highly preferable
everywhere. Designers need to understand how low-power techniques affect performance
attributes, and have to choose a set of techniques that are consistent with these attributes .The
main objective of this paper is to describe, how to achieve low power consumption with
approximately same delay time in a single circuit. In this paper, we make circuits with CMOS
and MTCMOS techniques and check out its power and delay characteristics. The circuits
designed using MTCMOS technique gives least power consumption.
All the pre-layout simulations have been performed at 250nm technology on tanner EDA tool.
Compact low power high slew-rate cmos buffer amplifier with power gating tech...VLSICS Design
A qualitative analysis of different parameters such as Phase noise, Slew rate and tranconductance by using
power gating reduction technique is presented. The circuit achieves the large driving capability by
employing simple comparators to sense the transients of the input to turn on the output stages, which are
statically off in the stable state. The effect of the different number of transistors and their topologies on the
phase noise and Slew rate is analyzed. Good agreement between qualitative and quantitative measurements
is observed. Scope of reducing of Noise and avoidance of Leakage due to various sources is discussed.
SURVEY ON POWER OPTIMIZATION TECHNIQUES FOR LOW POWER VLSI CIRCUIT IN DEEP SU...VLSICS Design
CMOS technology is the key element in the development of VLSI systems since it consumes less power. Power optimization has become an overridden concern in deep submicron CMOS technologies. Due to shrink in the size of device, reduction in power consumption and over all power management on the chip are the key challenges. For many designs power optimization is important in order to reduce package cost and to extend battery life. In power optimization leakage also plays a very important role because it has significant fraction in the total power dissipation of VLSI circuits. This paper aims to elaborate the developments and advancements in the area of power optimization of CMOS circuits in deep submicron region. This survey will be useful for the designer for selecting a suitable technique depending upon the
requirement.
SURVEY ON POWER OPTIMIZATION TECHNIQUES FOR LOW POWER VLSI CIRCUIT IN DEEP SU...VLSICS Design
CMOS technology is the key element in the development of VLSI systems since it consumes less power. Power optimization has become an overridden concern in deep submicron CMOS technologies. Due to shrink in the size of device, reduction in power consumption and over all power management on the chip are the key challenges. For many designs power optimization is important in order to reduce package cost and to extend battery life. In power optimization leakage also plays a very important role because it has significant fraction in the total power dissipation of VLSI circuits. This paper aims to elaborate the developments and advancements in the area of power optimization of CMOS circuits in deep submicron region. This survey will be useful for the designer for selecting a suitable technique depending upon the requirement.
SURVEY ON POWER OPTIMIZATION TECHNIQUES FOR LOW POWER VLSI CIRCUIT IN DEEP SU...VLSICS Design
CMOS technology is the key element in the development of VLSI systems since it consumes less power.
Power optimization has become an overridden concern in deep submicron CMOS technologies. Due to
shrink in the size of device, reduction in power consumption and over all power management on the chip
are the key challenges. For many designs power optimization is important in order to reduce package cost
and to extend battery life. In power optimization leakage also plays a very important role because it has
significant fraction in the total power dissipation of VLSI circuits. This paper aims to elaborate the
developments and advancements in the area of power optimization of CMOS circuits in deep submicron
region. This survey
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
CMOS LOW POWER CELL LIBRARY FOR DIGITAL DESIGNVLSICS Design
Historically, VLSI designers have focused on increasing the speed and reducing the area of digital systems.
However, the evolution of portable systems and advanced Deep Sub-Micron fabrication technologies have
brought power dissipation as another critical design factor. Low power design reduces cooling cost and
increases reliability especially for high density systems. Moreover, it reduces the weight and size of
portable devices. The power dissipation in CMOS circuits consists of static and dynamic components. Since
dynamic power is proportional to V2
dd and static power is proportional to Vdd, lowering the supply voltage
and device dimensions, the transistor threshold voltage also has to be scaled down to achieve the required
performance.
In case of static power, the power is consumed during the steady state condition i.e when there are no
input/output transitions. Static power has two sources: DC power and Leakage power. Consecutively to
facilitate voltage scaling without disturbing the performance, threshold voltage has to be minimized.
Furthermore it leads to better noise margins and helps to avoid the hot carrier effects in short channel
devices. In this paper we have been proposed the new CMOS library for the complex digital design using
scaling the supply voltage and device dimensions and also suggest the methods to control the leakage
current to obtain the minimum power dissipation at optimum value of supply voltage and transistor
threshold. In this paper CMOS Cell library has been implemented using TSMC (0.18um) and TSMC
(90nm) technology using HEP2 tool of IC designing from Mentor Graphics for various analysis and
simulations.
Back track input vector algorithm for leakage reduction in cmos vlsi digital ...VLSICS Design
A new algorithm based on Input Vector Control (IVC) technique is proposed, which shifts logic gate of a
circuit to its minimum leakage state, when device goes into its idle state. Leakage current in CMOS VLSI
circuit has become a major constrain in a battery operated device for technology node below 90nm, as it
drains the battery even when a circuit is in standby mode. Major concern is the leakage even in run time
condition, here aim is to focus on run time leakage reduction technique of integrated Circuit. It is inherited
by stacking effect when the series transistors are maximized in OFF state condition. This method is
independent of process technology and does not require any additional power supply. This paper gives an
optimized solution of input pattern determination of some small circuit to find minimum leakage vector
considering promising and non-promising node which helps to reduce the time complexity of the algorithm.
Proposed algorithm is simulated using HSPICE simulator for 2 input NAND gate and different standard
logic cells and achieved 94.2% and 54.59 % average leakage power reduction for 2 input NAND cell and
different logics respectively.
A Sub Threshold Source Coupled Logic Based Design of Low Power CMOS Analog Mu...VLSICS Design
A novel approach for designing Ultra Low Power and wide dynamic range circuit for multiplexing analog
signals is presented. The design operates in weak inversion (Sub threshold) region and uses Source -
Coupled Logic ( SCL) circuit. The bias current of the SCL gates is varied to scale down linearly the power
consumption and the operating frequency. The multiplexer design employs CMOS transistors as
transmission gate with dynamic threshold voltage. The design exhibits low power dissipation, high
dynamic range and good linearity. The design was implemented in 180 nm technology and was operated at
a supply voltage of 400 mV with a bias current ranging in the order of few Pico-amperes. The ON and
OFF resistance of the transmission gate achieved were 27 ohms and 10 M ohms respectively. The power
dissipation achieved is around 0.79 μW for a dynamic range of 1μV to 0.4 V.
Power Comparison of CMOS and Adiabatic Full Adder Circuits VLSICS Design
Full adders are important components in applications such as digital signal processors (DSP) architectures and microprocessors. Apart from the basic addition adders also used in performing useful operations such as subtraction, multiplication, division, address calculation, etc. In most of these systems the adder lies in the critical path that determines the overall performance of the system. In this paper conventional complementary metal oxide semiconductor (CMOS) and adiabatic adder circuits are analyzed in terms of power and transistor count using 0.18UM technology.
Similar to A NOVEL LOW POWER HIGH DYNAMIC THRESHOLD SWING LIMITED REPEATER INSERTION FOR ON-CHIP INTERCONNECTS (20)
Immunizing Image Classifiers Against Localized Adversary Attacksgerogepatton
This paper addresses the vulnerability of deep learning models, particularly convolutional neural networks
(CNN)s, to adversarial attacks and presents a proactive training technique designed to counter them. We
introduce a novel volumization algorithm, which transforms 2D images into 3D volumetric representations.
When combined with 3D convolution and deep curriculum learning optimization (CLO), itsignificantly improves
the immunity of models against localized universal attacks by up to 40%. We evaluate our proposed approach
using contemporary CNN architectures and the modified Canadian Institute for Advanced Research (CIFAR-10
and CIFAR-100) and ImageNet Large Scale Visual Recognition Challenge (ILSVRC12) datasets, showcasing
accuracy improvements over previous techniques. The results indicate that the combination of the volumetric
input and curriculum learning holds significant promise for mitigating adversarial attacks without necessitating
adversary training.
Final project report on grocery store management system..pdfKamal Acharya
In today’s fast-changing business environment, it’s extremely important to be able to respond to client needs in the most effective and timely manner. If your customers wish to see your business online and have instant access to your products or services.
Online Grocery Store is an e-commerce website, which retails various grocery products. This project allows viewing various products available enables registered users to purchase desired products instantly using Paytm, UPI payment processor (Instant Pay) and also can place order by using Cash on Delivery (Pay Later) option. This project provides an easy access to Administrators and Managers to view orders placed using Pay Later and Instant Pay options.
In order to develop an e-commerce website, a number of Technologies must be studied and understood. These include multi-tiered architecture, server and client-side scripting techniques, implementation technologies, programming language (such as PHP, HTML, CSS, JavaScript) and MySQL relational databases. This is a project with the objective to develop a basic website where a consumer is provided with a shopping cart website and also to know about the technologies used to develop such a website.
This document will discuss each of the underlying technologies to create and implement an e- commerce website.
Explore the innovative world of trenchless pipe repair with our comprehensive guide, "The Benefits and Techniques of Trenchless Pipe Repair." This document delves into the modern methods of repairing underground pipes without the need for extensive excavation, highlighting the numerous advantages and the latest techniques used in the industry.
Learn about the cost savings, reduced environmental impact, and minimal disruption associated with trenchless technology. Discover detailed explanations of popular techniques such as pipe bursting, cured-in-place pipe (CIPP) lining, and directional drilling. Understand how these methods can be applied to various types of infrastructure, from residential plumbing to large-scale municipal systems.
Ideal for homeowners, contractors, engineers, and anyone interested in modern plumbing solutions, this guide provides valuable insights into why trenchless pipe repair is becoming the preferred choice for pipe rehabilitation. Stay informed about the latest advancements and best practices in the field.
Industrial Training at Shahjalal Fertilizer Company Limited (SFCL)MdTanvirMahtab2
This presentation is about the working procedure of Shahjalal Fertilizer Company Limited (SFCL). A Govt. owned Company of Bangladesh Chemical Industries Corporation under Ministry of Industries.
Student information management system project report ii.pdfKamal Acharya
Our project explains about the student management. This project mainly explains the various actions related to student details. This project shows some ease in adding, editing and deleting the student details. It also provides a less time consuming process for viewing, adding, editing and deleting the marks of the students.
A NOVEL LOW POWER HIGH DYNAMIC THRESHOLD SWING LIMITED REPEATER INSERTION FOR ON-CHIP INTERCONNECTS
1. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.6, December 2014
DOI : 10.5121/vlsic.2014.5607 63
A NOVEL LOW POWER HIGH DYNAMIC
THRESHOLD SWING LIMITED REPEATER
INSERTION FOR ON-CHIP INTERCONNECTS
S. Rajendar1
, P. Chandrasekhar2
, M. Asha Rani3
, Ambati Divya1
1
Vardhaman College of Engineering, Hyderabad, India
2
Osmania University, Hyderabad, India
3
Jawaharlal Nehru Technological University, Hyderabad, India
ABSTRACT
In Very Large Scale Integration (VLSI), interconnect design has become a supreme issue in high speed ICs.
With the decreased feature size of CMOS circuits, on-chip interconnect now dominates both circuit delay
and power consumption. An eminent technique known as repeater/buffer insertion is used in long
interconnections to reduce delay in VLSI circuits. This paper deals with some distinct low power
alternative circuits in buffer insertion technique and it proposes two new techniques: Dynamic Threshold
Swing Limited (DTSL) and High Dynamic Threshold Swing Limited (HDTSL). The DTSL uses Dynamic
Threshold MOSFET configuration. In this gate is tied to the body and it limits the output swing. High
Dynamic Threshold Swing Limited (HDTSL) also uses the same configuration along with a high threshold
voltage(high-Vth). The simulation results are performed in Cadence virtuoso environment tool using 45nm
technology. By simulating and comparing these various repeater circuits along with the proposed circuits it
is analyzed that there is trade off among power, delay and Power Delay Product and the 34.66% of power
is reduced by using the high- Vth in HDTSL when compared to DTSL.
KEYWORDS
Buffer Insertion, Boostable repeater, Swing Limited Interconnect circuit, Dynamic Threshold, Multi Vth
1. INTRODUCTION
In recent years, increasing prominence of portable system and the need to limit power
consumption in very high density VLSI chips have led to rapid and innovative development in
low-power. From the last few decades, the CMOS technology has emerged as a predominant
technology in the field of nano electronics. As the technology has become compact there is rapid
increase in demand of high performance and low power digital systems. The interconnect is a
widely recognized cause of bottleneck in chip performance. Interconnect can no longer be seen as
a simple resistor but the associated parasitics such as capacitance and inductance also need to be
considered [1]. Thus any signal propagating through interconnect can be expected to be delayed.
One popular technique that reduces the delay is buffer insertion.
1.1. Buffer Insertion
As the VLSI technology is being scaled to nanometer, interconnect delay has becoming a
overriding constraint in the circuit design. The 50% of total path delay is exploited by
interconnect delay. Buffer insertion/repeater technique [2] is very efficient one to reduce the
2. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.6, December 2014
64
delay over long interconnect. This technique is used to restore the signal strength in long
interconnects. Various factors can deteriorate the signal performance in long interconnects, so
repeater insertion is needed. The buffer insertion technique divides the long interconnect into
equal smaller sections[3] and this is inserted between a driver and a receiver to drive each of these
sections. So the total delay can be reduced by insertion of these repeaters along the interconnect
wire length.
The paper is organised as follows. Section 2 explains various existing alternative circuits. They
are as follows boostable repeater, schmitt trigger, transient sensitive accelerator (TSA), swing
limited interconnect circuit (SLIC). Section 3 explains the proposed dynamic threshold swing
limited (DTSL) and high dynamic threshold swing limited (HDTSL). The operation of these
circuits is explained below in detail. These circuits are inserted in buffer insertion technique and
outputs are analyzed. The simulation results for the existing and proposed circuits are performed
for the various power supply and temperature variations are shown in section 4. By comparing the
simulation results of these two proposed circuits it is observed that the HDTSL offer significant
power savings upto 34.66% than DTSL. Finally Section 5 contains the conclusion.
2. CONVENTIONAL WORK
2.1. Boostable Repeater
In VLSI circuits the power efficiency is one of the main challenges as they are being scaled to
nanometer regime. So due to this the process variations and aging may cause degradation to the
circuits. Power consumption can be allocated uniformly across the fabricated instances during the
design time only, although many instances may not have variations. To compensate these
variations a circuit is used i.e., Adaptive circuit [4]. Adaptive design provides a power efficient
approach to these variations; the power will be used only when the variations of circuit are
harmful. So a new approach to fine grained voltage adaptation is Boostable Repeater [5]. Figure 1
shows the circuit diagram of Boostable Repeater. The main idea to introduce a Boostable repeater
design is, it will increase its internal voltage rail momentarily to boost up the switching speed.
The main advantage of using the Boostable repeater design is to achieve precise voltage
adaptation without using any voltage regulators or any power grid. This is operated in two modes.
(1) Boosting ON and (2) Boosting OFF. The boosting ON again consist of two phases (i)
Charging Phase and (ii) Boosting phase [5]. In Boosting phase the capacitor gets discharged and
it pulls up the output voltage. the boosting accelerates the rising transition of the output and hence
it improves the switching speed.
Figure 1. Boostable Repeater
3. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.6, December 2014
65
2.2. CMOS Schmitt Trigger
In digital systems, the Schmitt trigger is one kind of regenerative circuit. The CMOS Schmitt
triggers [6] are the circuit that converts the varying voltage to stable logic signal. The basic
Schmitt trigger- inverter circuit is shown in the Figure 2. Schmitt triggers are usually used to
generate fast transitions when a slowly varying function exceeds a predetermined level.
The designed Schmitt trigger as a buffer is inserted at a higher frequency through an
interconnect length in order to propagate the signal exactly from transmitting to receiving
end so as to reduce the delay and power. Schmitt trigger switches faster when compared
to ordinary CMOS buffer. Thus it leads to delay reduction.
Figure 2. CMOS Schmitt Trigger
2.3. Transient Sensitive Accelerator
Transient sensitive Accelerator(TSA) is a circuit that used for highly resistive interconnects. The
main advantage of TSA [8] is, it scales down both the delay time and cross talk voltages. Another
advantage is that it can operate in self-time and can be applied to bidirectional signal
communication. The circuit diagram of TSA is shown below as Figure 3. The TSA internally
comprises of three sub-circuits: Transient Sensitive Trigger (TST), Clamp Transistors and
Accelerator Transistors [8]. For the long interconnects the RC delay time can be reduced by using
TST [7]. It changes its logical threshold voltage depending upon the input signal transition. This
threshold voltage can be set to some constant value by decreasing the size of the transistors N1
and P1 or by increasing the size of the transistors N2 and P2. This results in fast detection of
signal voltage transition. The lower half of the circuit consists of Schmitt trigger followed by an
inverter. The interconnect voltage is assumed to have a long rise and fall time stemming from the
large RC constant. The TST senses the transition at an early stage and the Schmitt trigger detects
the change at the end of the transition. This timing difference in the sensing can be utilized as an
acceleration period if the circuit turns ON during the interval. The clamp transistors and
accelerator work alternatively. The clamp transistors work in the steady state and the accelerator
transistors are turned ON during the transition interval. During the transition interval, the path
through the clamp transistors gets disappears and accelerates the voltage transition. The main
purpose of this circuit is to prevent TST from reacting to a small voltage fluctuations, it slightly
delays the signal detection of the TST.
4. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.6, December 2014
66
Figure 3. Transient Sensitive Trigger (TSA)
2.4. Swing Limited Interconnect Circuit
One of the solutions to achieve better energy efficiency is to reduce the swing voltage of the
signal on the interconnect. The principal behind the low-swing techniques is the dependence of
dynamic power on swing voltage. By the use of this results in reduced charging and discharging
of interconnect capacitance. Reducing the swing voltage results in faster signalling method for on
chip interconnects. The low swing interconnect architecture is presented in [9].
Swing Limited Interconnect circuit (SLIC) [10] mainly restricts the swing at the input. The output
of interconnect is never allowed to its full rail. The circuit for SLIC is shown in figure 4. SLIC is
a three stage cascaded inverter configuration with keeper transistors. M1 and M2 are the keeper
transistors. The main function of the keeper transistors is to limit the swing from full rail to
reduced rail. Inverter 1 acts as a level restoration circuit. It converts the input full rail voltage to
reduced rail swing. This inverter also provides the necessary operating voltage for keeper
transistors M1 and M2. The inverter 2 converts reduced signal swing to full rail. The NMOS is
tied to Vdd and PMOS to ground. The main idea for this is to use them to hold inverter-1 input to
just around the switching threshold. When the input is high, the output of inverter 1 is low, due to
this the PMOS is turned ON and NMOS is turned OFF which pulls down the output of inverter 1.
This output is pulled down below the midpoint of the supply voltage by the PMOS. After this
point the PMOS automatically gets OFF and the NMOS is turned ON. This intern pulls the output
of interconnect. Thus the output of interconnect in never allowed to discharge and charge to its
full-rail.
5. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.6, December 2014
67
Figure 4. Swing Limited Interconnect Circuit (SLIC)
3. PROPOSED WORK
3.1. Dynamic Threshold Swing Limited
One of the most promising ways to attain both high speed and low power at low supply voltage is
to vary threshold voltage of the MOSFETs. The configurations have been reported for many
devices and circuits for variable voltage threshold. One is Dynamic Threshold MOSFET
configuration (DTMOS) [11].
Figure 5. Dynamic Threshold Swing Limited (DTSL)
The dynamic power dissipation is marginal compared to speed enhancement. DTMOS has a
nonzero static power dissipation component. This DTMOS contains the high Vt at zero bias and
low Vt at Vgs=Vdd. The gate is tied to the body in the DTMOS. The DTMOS inverter is shown in[
]. The Swing Limited Interconnect circuit is modified by using this dynamic threshold MOSFET
forming a new circuit called Dynamic Threshold Swing Limited(DTSL). The circuit for DTSL is
shown in Figure 5. This also uses the low-swing signalling technique. Several low- swing
signalling schemes are proposed in[12]. The power consumption can be reduced by using this
Dynamic Threshold MOSFETS. The operation of this circuit is that it limits the swing at the input
along with dynamic threshold. This is due to the keeper transistors. The output of this is the
6. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.6, December 2014
68
reduced rail when compared to the input. This designed DTSL is connected in buffer insertion
technique with particular interconnect length.
3.2. High Dynamic Threshold Swing Limited
High-performance and low-power are the two main criteria in modern digital design. MTCMOS
[13] is an effective circuit level technique. The performance and design is improved by utilizing
high threshold voltage transistors. This technology is straight forward to use because existing
designs can be easily be modified into MTCMOS blocks by simply adding high-Vth power
supply, yet circuits can be easily placed in low leakage states at fine grain level of control. we
assume that the values of the threshold voltages are specified by the process technology and
cannot be variables in the optimization process[14]. This is usually true since the threshold
voltage is very difficult to control accurately and the designers are not at the liberty of selecting a
value that is not supported by the process. The goal of the selection process is to enable a
subsequent power optimization of the circuit to reduce the dynamic component of the power
dissipation. Henceforth, the low and high threshold voltage values will be called VtL and VtH ,
respectively, and the corresponding gates will be referred to as low-Vt and high-Vt gates,
respectively
In this paper, HDTSL based on high-Vth CMOS technology is proposed. Keeper transistors are
used which reduces the leakage current while saving exact logic state. The DTSL circuit is
modified by using this high-Vth CMOS forming a new circuit called High Dynamic Threshold
Swing Limited(HDTSL). The circuit for HDTSL is shown in Figure 6. This is also a three stage
cascaded inverter but with high-Vth. Here M1 and M2 are the keeper transistors which limit the
swing on the input. The operation is same as the DTSL but with the reduced power consumption.
The proposed circuit maintains the lower power consumption characteristics as compared to the
DTSL. This designed HDTSL is connected in buffer insertion technique with particular
interconnect length.
Figure 6. High Dynamic Threshold Swing Limited (HDTSL)
4. SIMULATION RESULTS
All the circuits are simulated in 45nm technology using Cadence Virtuoso tool. Power, delay and
Power Delay Product (PDP) is compared for the various alternative repeaters. Table 1 shows the
comparison results of various circuits’ interms of power, delay and PDP. It shows that TSA
7. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.6, December 2014
69
consumes less power when compared to other circuits. Table 2. shows Comparison of Power,
delay and PDP for DTSL and HDTSL at 45nm technology. HDTSL consumes less power than
the DTSL. Table 3. shows comparison of proposed DTSL and HDTSL circuits interms of power
and delay with supply voltage variation at room temperature. Table 4. shows comparison of
proposed DTSL and HDTSL circuits interms of power and delay with temperature variations
operating at Vdd=1V.
Table 1. Comparison of Power, delay and PDP for various circuits at 45nm technology
Designs Power(µW) Delay(ns) PDP(fJ)
Booster 11.09 0.26 2.88
Schmitt trigger 4.968 0.31 1.54
TSA 2.11 0.84 1.79
SLIC 6920 0.079 480
Table 2. Comparison of Power, delay and PDP for DTSL and HDTSL at 45nm technology
Designs Power(µW) Delay(ns) PDP(fJ)
DTSL 116.8 0.19 22.19
HDTSL 76.31 0.28 21.63
Table 3. Comparison of proposed DTSL and HDTSL circuits interms of power and delay with supply
voltage variation at room temperature
Supply
Voltage
DTSL HDTSL
Power(µW) Delay(ns) Power(µW) Delay(ns)
0.7V 103.5 0.23 58.93 0.35
0.8V 108.8 0.21 69.54 0.32
0.9V 112.4 0.20 73.86 0.30
1V 116.8 0.19 76.31 0.28
1.2V 122.2 0.18 80.72 0.27
8. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.6, December 2014
70
Table 4. Comparison of proposed DTSL and HDTSL circuits interms of power and delay with temperature
variations operating at Vdd=1V
Temperature
DTSL HDTSL
Power(µW) Delay(ns) Power(µW) Delay(ns)
-40°C 127.4 0.141 85.83 0.19
-27°C 127.3 0.149 85.49 0.21
0°C 124.3 0.158 82.66 0.24
27°C 116.8 0.19 76.31 0.28
40°C 111.2 0.20 72.32 0.31
The Supply voltage is varied ranging from 0.7V to 1.2V and observed that power increases as the
supply voltage is increased and delay also is increased for both DTSL and HDTSL. The
Temperature is varied from -40°C to 40°C and observed that the power increases as the voltage is
increased and delay also increased for both the DTSL and HDTSL. There is a trade off between
these Power, Delay and PDP. Figure 7. A) shows the histogram comparing the power for
proposed DTSL and HDTSL. B) shows the histogram comparing the PDP for proposed DTSL
and HDTSL. The power consumption is less for the HDTSL than the DTSL. So this HDTSL is
power efficient. The PDP is also less for HDTSL. Figure 8. shows the simulation waveform of
proposed HDTSL in Cadence Virtuoso using 45nm technology. By analyzing the result it can be
observed that the output of interconnect is reduced rail when compared to input.
A) B)
Figure 7. A) Comparison of power consumption for DTSL and HDTSL
B) Comparison of PDP for DTSL and HDTSL
9. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.6, December 2014
71
Figure 8. Simulation waveform of proposed HDTSL in Cadence Virtuoso using 45nm technology
The High Dynamic threshold swing limited interconnect system does not break interconnects.
This system uses the receiver, reduces the voltage swing on interconnects from rail- to rail to a
reduced rail. The waveform of SLIC is shown in figure 8. It can been observed that the output of
interconnect is reduced rail as compared to the input. This is due to M1 and M2 transistors. The
low swing at output of interconnect is restored to fully rail by the subsequent three inverters.
Figure 9. A) shows the Power versus voltage variations B) shows the Delay versus Voltage
variations C) shows the Power versus Temperature variations D) shows the Delay versus
Temperature variations.
A) B)
10. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.6, December 2014
72
C) D)
Figure 9. A) Power versus Voltage variations B) Delay versus Voltage variations
C) Power versus Temperature variations D) Delay versus Temperature variations
5. CONCLUSIONS
The performance estimation of various existing alternative repeaters and proposed circuits are
analyzed and compared for on-chip inter-connect system in Cadence Virtuoso tool using 45nm
technology. From the simulation results it is analyzed that the proposed techniques output is the
reduced rail when compared to the input. From comparisons table it is analyzed that booster as a
buffer improves the switching speed than Schmitt trigger but the power gets reduced. TSA
consumes less power when compared to Schmitt trigger. The delay of SLIC is very low but the
power consumed is very high than the other two. So two new techniques are proposed. The
proposed DTSL uses the Dynamic threshold technology, which consumes less power than SLIC.
Another proposed HDTSL uses the high-Vth CMOS technology, which offer significant power
savings upto 34.66% than DTSL. The Supply voltage is varied ranging from 0.7V to 1.2V are
done and observed that power increases as the supply voltage is increased for both DTSL and
HDTSL. The Temperature is varied from -40°C to 40°C and observed that the power increases as
the voltage is increased for both the DTSL and HDTSL. There is a trade off between these Power,
Delay and PDP. Hence HDTSL is both Power and Energy efficient when compared to DTSL.
REFERENCES
[1] Magdy A. El-Moursy & Eby G. Friedman, (2004) “Optimum wire sizing of RLC interconnect with
repeaters”, in proc. INTEGRATION, the VLSI journal 38 205–225.
[2] A. Mahesh Kumar, SreehariVeeramachaneni & M.B.Srinivas, (2010) ”Alternative approach to Buffer
Insertion for Delay and Power Reduction in VLSI Interconnects”, in proc Center for VLSI and
Embedded Systems Technologies, January.
[3] K. Banerjee Mehnotra, A.(2002), “A power optimal repeater insertion methodology for global
interconnects in nanometer designs,” IEEE Trans. Electron Devices, vol. 49, pp. 2001-2007.
[4] FarshadMoradi, Dag T. Wisland, Hamid Mahmoodi, Tuan Vu Cao, & MalihehZarreDooghabadi,
(2009) “Adaptive Supply Voltage Circuit Using Body BiasTechnique” in proc. 16th International
Conference "Mixed Design of Integrated Circuits and Systems", June 25-27, pp. 215-219.
[5] Kyu-Nam shim & Jiang Hu, (2013)” Boostable Repeater design for variation Resilience in VLSI
Interconnects” in proc. IEEE Trans. Very Large Scale Integr(VLSI) syst., vol. 21,No. 9,sept pp1619-
1631.
11. International Journal of VLSI design & Communication Systems (VLSICS) Vol.5, No.6, December 2014
73
[6] Saini.S, (2009)“Schmitt Trigger as an alternative to Buffer Insertion for Delay and Power Reduction
in VLSI Inter-connects”, IEEE Region10Conference-TENCON.
[7] Hong-Yi Huang & Shih-Lun Chen, (2006) “High-Speed Transition Detecting Circuits for On-Chip
Interconnections” in proc Tamkang Journal of Science and Engineering, Vol. 9, No 1, pp. 37_44.
[8] Iima, T., Mizuno, M., Horiuchi, T. & Yamashina,M., (1996) “Capacitor Coupling Immune, Transient
SensitiveAccelerator for Resistive Interconnect Signals of Subquarter Micron ULSI,” in proc. IEEE J.
Solid-State Circuits, Vol. 31, pp531_536.
[9] Volkan Kurusun, Radu M.Secareanu and Eby G. Fredeman (2002) "Cmos voltage interface circuit for
low power system." in proccedings of IEEE international Sympoism on circuits and systems, Vol 3,
May pp 667-670.
[10] VishakVenkatraman, Mark Anders, HimanshuKaul, Wayne Burleson & Ram Krishnamurthy “ A
Low Swing Signalling Circuit Technique for 65-nm On Chip Interconnects” in proc IEEE Soc
Conference, pp289 – 292.
[11] FariborzAssaderaghi, Dennis Sinitsky, Stephen A. Parke, Jeffrey Bokor, Ping K. Ko & Chenming Hu
, (1997)“Dynamic Threshold-Voltage MOSFET(DTMOS) for Ultra-Low Voltage VLSI” in proc
IEEE Transactions On Electron Devices, Vol. 44, No. 3, March pp 414-422.
[12] Zhang, H., George, V. and Rabaey, J. M., (2000) “Low-swing on-chip Signaling Techniques:
Effectiveness and Robustness,” IEEE Trans. VLSI Systems, Vol. 8, pp. 264_ 272.
[13] V. Kursun and E. G. Friedman, "Multi-Voltage CMOS Circuit Design." New York: Wiley, 2006
[14] P.Sreenivasulu, G.Vinatha, Dr. K.Srinivasa Rao, Dr. A.Vinaya babu, (2013) " Novel Ultra Low
Power Multi-threshold CMOS Technology", in proc International Journal of Advanced Research in
Computer Science and Software Engg. 3(8), August , pp 81-88.
.