This document discusses two methods for signal and power integrity simulation: vector fitting (VF) and piecewise-linear fitting (PWL). VF approximates complex frequency functions with rational polynomials, while PWL simplifies time-domain S-parameter responses, both suitable for high-speed simulations. The advantages of PWL with digital wave simulation (DWS) include faster processing times and improved stability compared to traditional vector fitting methods.

1. 1 Copyright Piero Belforte 2015
VECTOR VS PIECEWISE-LINEAR FITTING FOR
SIGNAL AND POWER INTEGRITY SIMULATION
This brief technical note introduces the basic concepts of two fitting methods suitable for signal
and power integrity simulation up to multi-gigabit/sec rates. The traditional method is based on
Vector Fitting (VF) VECTFIT [1,2], a well known technique to approximate complex functions of
frequency by a rational polynomial expression in terms of poles and residues. The second is a full
time-domain approach mainly based on behavioral models supported by the Digital Wave
Simulator DWS [3,4,5,6,7,8,9] . DWS processes the waves of a Digital Network built up
connecting together scattering blocks (traditional circuit elements, nodes and S-parameter blocks)
coming from a Spice-like description. These two complementary methods can deal with both
mono and two-dimensional signal propagation related to lossy interconnects (cables, traces etc.)
and power distribution planes of printed circuit boards. They are schematically compared in the
flow of Fig.1
Fig.1 General modeling/simulation flow: on the left the classical way based on impedance Vector
Fitting , on the right the full time-domain approach based on S-parameters and DWS processing.

2. 2 Copyright Piero Belforte 2015
The traditional way: Frequency domain Vector Fitting
The modeling flow using Vector Fitting is shown in the left side of the flow of Fig. 1.
In case of mono-dimensional propagation, as applies to lossy interconnects, the physical line is
discretized according to a chosen spatial pitch in several equal segments (unit cells) connected in
cascade. The segmentation pitch is related to the required model bandwidth. Each cell can be
implemented as a ZY-TL circuit where Z is a series impedance, Y a parallel admittance, both
frequency dependent and TL is an ideal Transmission Line (TL). Starting from the geometrical and
physical crossection data, the impedance Z0 and delay time td are obtained from theoretical
formulations related to the specific cross-section. Z and Y are obtained from the theoretical
expressions of skin effect and dielectric losses versus frequency respectively [5].Using the VECTFIT
code applied to theoretical frequency behaviors, unit-cell poles and zeros can be extracted and
then mapped into RL or RLC circuits leading to a Spice-like cellular model of the interconnect. This
ZY-TL model can be simulated in time domain using a conventional Nodal Analysis solver like Spice
or processed by DWS. Using a Nodal Analysis simulator a careful choice of Spice version is needed
because the presence of several "short" Transmission Lines requires both an accurate TL model
and the ability to work at small (picosecond or even subpicosecond) fixed time step. Only a subset
of commercial Spice versions is able to satisfy the previous conditions, while other versions could
lead to inaccurate results or convergence problems. MicroCap11, MC11 of Spectrum Software[7] is
a Spice versions able to deal with this class of circuits.
DWS, available as cloud-based SpicySWAN application by Ischematics [11], can be also used to
process the ZY-TL models requiring only 1/100 of the simulation time required by MC11 working
at the same time step ( see also DWS VIDEOS, [18]).This means that sub-picosecond time steps
can be used to get very accurate results in short times. Simulation times are in the order of
seconds on a current pc for cellular models of hundreds ZY-TL segments. MC11 typically requires
several minutes to do the same job due to the 100X DWS/MC11 speedup. The results are
practically identical to those obtained by DWS with relative differences in the order of 1e-6.
Several commercial tools like CST's [13] Cable Studio or PCB Studio adopt this VF-based method to
model and simulate cables or printed circuit board interconnects. A 40Gbps comparison between
DWS and CST Cable Studio has been performed for a RG58 coaxial cable, leading to a 720X
speedup with very similar simulated eye diagrams [CST VS DWS].

3. 3 Copyright Piero Belforte 2015
The unconventional way: PWLFIT, Time-domain PWL Fitting
This method can be applied when the time-domain S-parameters step responses of DUT are
available. Sources of such responses can be TDR/TDT measurements on the DUT, analytical
formulas or 2D/3D field solvers. In case of measurement, a setup de-embedding is needed to
extract the required intrinsic DUT S-parameters. Modern TDR and VNA can directly perform this
task, otherwise a de-embedding loop procedure can be performed by DWS simulation as shown in
Fig.1 using an accurate model of the setup itself. A Behavioral Time-domain Model (BTM, [8,9])
can be built up directly from the files containing the samples of the de-embedded S-parameters
using the FILE mode description supported by DWS . A more computationally efficient way is to
use the piecewise linear fitting (PWLFIT) of S-parameter behaviors as shown in Fig.1. This task can
be done manually on the plotted waveforms using the MCS (Model Capture System[9]) facility
included in DWV, the DWS graphic postprocessor, or other online tools as Plot Digitizer, or even
automatically on the imported files coming from measurements or simulations. In case of spatial
segmentation in several BTM cells connected in cascade (micro-behavioral model), pwl
breakpoint optimization can be performed by simulation of the whole cascade comparing the
simulated result to measurements or to imported simulations. At the end of this optimization
process a de-embedded model of the DUT is available (PWL DE-EMBED example). A similar
procedure can be applied to 2D BTM models of p.c.b power distribution planes (2D BTM MODELS).
Thanks to the fast convolution algorithm included in DWS, the processing time for PWL BTM
models is 10 to 100 times shorter than the time required using the circuital model and 1000 to
10000X shorter compared to Spice simulation times.
Several application examples of this technique are available for interconnects like coaxial cables
[RG58], p.c.b. traces [COPLANAR MSTRIP], coupled interconnects [COUPLED MSTRIP], Beatty Line
[BL1, BL2] and power distribution planes [POWER PLANES]. More examples can be found in the
Appendix and at Piero Belforte Research Gate Website [19].
PWLFIT vs VECTFIT Feature Comparison
Time-domain piecewise fitting combined with DWS processing offers several advantages with
respect conventional Vector fitting combined with Nodal Analysis circuital simulation. It is known
that time-domain S-parameters behaviors in matched conditions are much simpler than the
corresponding frequency-domain behaviors [GOH]. This means that few pwl (tens) breakpoints
can model these behaviors with small errors. To fit the equivalent impedances in frequency
domain a large number of poles and zeros could be required leading to potential numerical
stability problems. These stability problems can be avoided by conditioning in some way the VF
data. On the contrary the well known stability of Digital Wave processing [3] doesn't require any
conditioning of PWL description to prevent numerical instability. Circuital models coming from
Vector Fitting, BTM models and even s-plane/z-plane descriptions can be mixed together in very
complex networks (up hundreds of thousands scattering elements, MULTI-LAYER PCB 220K) and

4. 4 Copyright Piero Belforte 2015
processed by DWS in times that are up to 4 orders of magnitude lower than using traditional
Spice simulation.
Concluding remarks
PWLFIT and DWS advantages over VECTFIT and Spice can be summarized with the 3S acronym:
SIMPLICITY, STABILITY and SPEED.
SIMPLICITY because the pwl fitting of a time-domain behavior is a very fast, explicit and intuitive
process that doens't need the solution of implicit equations as required by Vector fitting. Time-
domain S-parameter of actual devices in matched conditions shows simpler behaviors than the
corresponding impedance in the frequency domain.
STABILITY because the use of Digital Wave processing is intrinsically very stable. Extracted pwl
behaviors processed by fast convolution within DWS are unconditionally stable if the source
behavior is stable. This means that NO numerical conditioning is required. As known Vector Fitting
often require numerical conditioning to get stable results.
SPEED: time-domain pwl fitting is a very fast process. DWS simulations are also very fast even at
very small time steps required by multigigabit system analysis. DWS/SPICE typical speedups are
100X for traditional RLC-TL circuits and up to 10000X when using pwl Behavioral Models in time
domain.
REFERENCES
[1] B. Gustavsen, A. Semlyen, “Rational approximation of frequency domain responses by vector fitting”,
IEEE Trans. Power Delivery, vol. 14, July. 1999, pp. 1052-1061. VF Gustavsen
[2] Vector Fitting Website: VECTFIT
[3] A. Fettweis, "Wave Digital Filters: Theory and Practice," Proceedings of IEEE, vol. 74, no. 2, Feb. 1986,
pp. 270-327. WDF FETTWEIS
[4] P. Belforte, G. Guaschino 1985 "DWS 8.5" DWS 8.5
[5] P. Belforte, U. Colonnelli, G. Guaschino DIGITAL WAVE SIMULATION 1975
[6] P. Belforte, B. Bostica, G. Guaschino, "Time-domain simulation of lossy interconnection using digital
wave networks, ISCAS '82 Rome, ISCAS 82
[7] P. Belforte, G. Guaschino, "Electrical simulation using digital wave networks, IASTED '85 Paris: IASTED 85
[8] P. Belforte, F. Maggioni, J. Torres, "Characterization and modeling of MCM (Multi-Chip Module)
substrates and components" IEEE Transactions on Computers, June 1993 IEEE Computers June 1993
[9] HDT (High Design Technology) "A high-performance environment for modeling and simulation of digital
systems" HP High -Speed Digital Systems Design and Test Symposium 1993 : HP SEMINAR 1993
[10] S. Caniggia, F. Maradei, “Signal Integrity and Radiated Emission”, John Wiley & Sons, 2008. CANIGGIA
MARADEI

5. 5 Copyright Piero Belforte 2015
[11] Spicy Swan Ischematics SpicySWAN
[12] Micro-Cap 11.0 MC11
[13] CST Cable Studio Cable Studio
[14] J.H.R. Schrader "Wireline Equalization using Pulse Width Modulation" Twente University Thesis 2007:
SCHRADER 2007
[15] J. Schutt-Ainé, P. Goh, Y. Mekonnen, J. Tan, F. Al Hawari, P. Liu, W. Dai "Comparative Study of
Convolution and Order Reduction Techniques for Blackbox Macromodeling Using Scattering
Parameters", IEEE Trans. Comp., Pack. and Manufac. Tech., vol. 1, no. 10, Oct. 2011, pp. 1642-1650:
CONVOLUTION S-PARAM.
[16] P. Goh, M.F. Ain "Fast S-parameter Convolution for Eye Diagram Simulations of High-Speed
Interconnects" SICASE 190 2013: FAST CONV. EYE DIAGRAMS
[17] R.B Wu "Fast Eye-Diagram Analysis", 2013 : FAST EYE DIAGRAM
[18] P. Belforte: DWS VIDEO PLAYLIST
[19] Piero Belforte: Research Gate Website Piero Belforte Research Gate
Piero Belforte Born in Turin in 1947, received his Laurea degree in Electronics Engineering summa cum laude in1970
from the Politecnico of Turin. From 1970 to 2000 he worked in CSELT, the Research Center of Telecom Italia as Head of Switching Techniques
Department and then as Head of Hardware Qualification Department. His main activity was focused to state-of-the-art digital switching systems and
qualification tools for the Telecom network.In 1975 he started the development of several generations of high-speed modeling and simulation tools
using innovative DSP algorithms for fast computer simulation of high-speed electronic systems. These tools have beenutilized from the beginning
up to present for the design of both state-of-the-art prototypes and commercial products.In 1988 he founded and directed the company HDT (High
DesignTechnology) for the development of state-of.-the art CAE tools for SI/PI/EMC prediction based on digital wave simulation. In the last years of
his activity in CSELT he also created the hardware quality project THRIS involving several high tech companies and Universities.. From 2001 to
present he continues his research activity as Independent Researcher. In this role he developed the HiSAFE fault insertion tool for multi-gigabit IP
systems adopted by Cisco Systems as a standard qualification tool for high-end products. In 2012 he started the development of Spicy SWAN,
cloud-based circuit simulation application in partnership with Ed Pataky founder of Ischematics. He is author of several publications and
international patents in the field of digital electronics with reference to digital switching systems and techniques for telecom networks, high-speed
electronics, signal and power integrity, circuital modeling and simulation, electromagnetic compatibility and test equipment for high performance
digital systems. His publications and patents are available at https://www.researchgate.net/profile/Piero_Belforte and
https://www.linkedin.com/in/pierobelforte Email address: piero.belforte@gmail.com

6. 6 Copyright Piero Belforte 2015
APPENDIX : DWS & PWLFIT EXAMPLE MIX
The following Web links point to miscellaneous examples of the thousands available using DWS and PWLFIT. They are
technical documents extracted from Research Gate site PB_RG , interactive 2D and 3D plots of exported SpicySWAN
simulations processed by the online plotting application plot.ly, SpicySWAN simulation reports generated by the
application itself and tutorial/application videos from DWS PLAYLIST. The interactive plots allow the user to select the
plotted variables, zoom, pan, read the plotted samples and changing the viewpoint for the 3D plots.
Coaxial cables
Technical documents
[A1] TDR MEASUREMENT OF A RG58 COAXIAL CABLE
[A2] RG58 COAXIAL CABLE: BTM VS ANALYTICAL MODELS
[A3] RG58 COAXIAL CABLE S-PARAMETERS: CST VS DWS VS SPICE
[A4] ZYTL and RLTL RG58 COAXIAL CABLE MODELS VS ACTUAL TDR
[A5] BIDIRECTIONAL TRANSMISSION ON COAXIAL CABLE BY DWS
Interactive plots
[A6] RG58 CU TASKER 1.83M: MEASURED S21 & CSA803C/S24 FIXTURE
[A7] 61 VS 610 ZYTL CELL COMPARISON: 10PS INPUT RAMP, TSTEP=500FS
[A8] RG223U VS RG58CU 3D FREE OSCILLATION PATTERNS
SpicySWAN simulation reports
[A9] COAXIAL CABLE COMPARATIVE FOPS
Lossy Interconnects
[A10] COPLANAR MSTRIP: DWS VS 9000E (video)
[A11] COPLANAR MSTRIP: WORST-CASE EYE DIAGRAMS (video)
Lossy Coupled lines
[A12] DWS MODELING AND SIMULATION OF COUPLED LINES
[A13] COUPLED MICROSTRIPS: .1-20GHZ S-PARAMETERS COMPARISON BETWEEN SI9000E AND DWS TDR-BASED BTM MODELS
Power distribution planes
[A14] POWER PLANE SWITCHING NOISE: CST VS DWS VS MC10
[A15] POWER PLANE LOW-FREQ CAPACITANCE
[A16] COAXIAL CABLE IMPEDANCE PROFILE BY DWS VIRTUAL VNA
DWS vs Spice comparison
[A17] SPICE INTEGRATION ERROR OF A 10-CELL LC CIRCUIT STEP RESPONSE
[A18] NONLINEAR TL: DWS vs MC11 (video)