ic technology and applications

1. Introduction to IC Technology
&
ApplicationsApplications
EE405
Dr. Rizwan AkramDr. Rizwan Akram
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2. OutlineOutline
• Introduction to IC technologyIntroduction to IC technology
• Moore’s Law
i b l l• Design Abstract levels
• IC Classifications
• Traditional IC design Flow
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3. The IC MarketThe IC Market
• The semiconductor industry is approaching $300B/yr in sales
Military
Communications
24%
Military
2%
Computers
42%
T t ti C El t i
Industrial
8%
Transportation
8%
Consumer Electronics
16%
Courtesy of Dr. Bill Flounders, UC Berkeley Microlab
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8. • In 1965, Gordon Moore predicted that the number of transistors
that can be integrated on a die would double every 18 to 14 months
• i.e., grow exponentially with time
• Amazing visionary – million transistor/chip barrier was crossed in the
1980’s.
– 2300 transistors, 1 MHz clock (Intel 4004) ‐ 1971
– 42 Million, 2 GHz clock (Intel P4) ‐ 2001
Relative sizes of ICs in graph
– 140 Million transistor (HP PA‐8500)
100
10
TELENGTH(nm)
LO W P O W E R
Source: Intel web page (www.intel.com)
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2000 2005 2010 2015 2020
1
GAT
Y E AR
LO W P O W E R
H IG H P E R FO R M AN C E
International Technology Roadmap for Semiconductors

9. Limits of Moore’s Law?
• Growth expected until 30 nm gate length (currently: 180 nm)
– size halved every 18 mos ‐ reached insize halved every 18 mos. reached in
– 2001 + 1.5 log2((180/30)2) = 2009
– what then?
• Paradigm shift needed in fabrication process
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14. IC Fabrication
• Goal: Mass fabrication (i.e. simultaneous fabrication)
of many IC “chips” on each wafer, each containing
IC Fabrication
of many IC chips on each wafer, each containing
millions or billions of transistors
• Approach: Form thin films of semiconductors, metals,
and insulators over an entire wafer, and pattern each
layer with a process much like printing (lithography).
Planar processing consists of a sequence of
additive and subtractive steps with lateral patterning
oxidation
deposition
ion implantation
etching lithography
p
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15. Planar Processing
• DEPOSITION of a thin film
g
(patented by Fairchild Semiconductor in 1959: J. A. Hoerni, US Patent 3,064,167)
• LITHOGRAPHY
– Coat with a protective layerCoat with a protective layer
– Selectively expose the protective layer
– Develop the protective layer
• ETCH to selectively remove the thin film
• Strip (etch) the protective layerStrip (etch) the protective layer
Courtesy of Dr. Bill Flounders, UC Berkeley Microlab
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16. Overview of IC Process Steps
E i
Test
Overview of IC Process Steps
EpitaxyBare Silicon
Wafer
Processed
Wafer
Deposition/growth
Anneal
Mask Pattern
CMP
Ion Implantation
Mask Pattern
Generation
CD SEM
Metrology
Defect
Detection
Etch Lithography
Courtesy of Dr. Bill Flounders, UC Berkeley Microlab
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17. What are shown on previous diagrams cover only the so called front‐end
processing ‐ fabrication steps that go towards forming the devices and
inter‐connections between these devices to produce the functioning IC's. The
end result are wafers each containing a regular array of the same IC chip or
die. The wafer then has to be tested and the chips diced up and the good chipsdie. The wafer then has to be tested and the chips diced up and the good chips
mounted and wire‐bonded in different types of IC package and tested again
before being shipped out.
From Howe, Sodini: Microelectronics:An Integrated
Approach, Prentice Hall
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18. Recurring Costs
While the cost of producing a single transistor has dropped exponentially over the past few
cost of die + cost of die test + cost of packaging
i bl t
While the cost of producing a single transistor has dropped exponentially over the past few
decades, the basic cost equation hasn’t changed. Cost of a circuit is dependent upon the
chip area.
p g g
variable cost = ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐
final test yield
cost of wafer
cost of die =cost of die = ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐
dies per wafer × die yield
die yield = (1 + (defects per unit area × die area)/)‐die yield = (1 + (defects per unit area × die area)/)
Alpha depends upon the complexity of the manufacturing process (and is roughly proportional
to the number of masks). A good estimate for today’s complex CMOS process is alpha = 3.
Defects per unit area is a measure of the material and process‐induced faults. A value
between 0.5 and 1 defects/cm2 is typical today but strongly depends upon the maturity of the
process.
 × (wafer diameter/2)2  × wafer diameter
dies per wafer = ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐  ‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐‐
die area  2 × die area
p
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19. Yield ExampleYield Example
 Example
 wafer size of 12 inches, die size of 2.5 cm2, 1 defects/cm2,
 = 3 (measure of manufacturing process complexity) = 3 (measure of manufacturing process complexity)
 252 dies/wafer (remember, wafers round & dies square)
 die yield of 16%
 252 x 16% = only 40 dies/wafer die yield !
 Die cost is strong function of die area
 proportional to the third or fourth power of the die area
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27. 33
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28. 44
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31. System Specification
Functional Specifications
Function/Archt. design
Functional
Simulation
Specifications
Logic
Simulation
Behavioral
Representation
Logic Synthesis
Circuit Structural
Circuit Design
Circuit
Analysis
Structural
Representation
Structural
Representation
Extraction and
Verification 31

32. (Continued)
Structural
Representation
Extraction and
Physical Synthesis
RepresentationVerification
Physical
Representation
Fabrication
Packaging
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