The document discusses the history and development of electronic manufacturing and integrated circuits. It begins with the invention of the transistor in 1947 and its replacement of germanium with silicon. The integrated circuit was developed in 1958, combining multiple transistors on a single silicon chip. Gordon Moore observed that the number of transistors on integrated circuits doubled every year (Moore's Law). Key developments included the microprocessor in 1971 and dynamic random access memory. The document also describes the various levels of interconnection and packaging used to produce electronic devices and circuits.

1. Electronic Manufacturing and the
Integrated Circuit

2. 1.MICROELECTRONICS AND THE TRANSISTOR
• 1947:invention of the transistor at Bell Laboratories.
• Transistor:capable of both amplifying and switching (on/off) electrical signals.
• Early 1950s: the first transistor was based on the semiconductor Germanium.
• Transistors based on the superior properties and manufacturability of silicon (Si) followed
later in the decade replacing Ge in almost all applications.
• smaller and lighter transistor considerably lowers level of power for operation.
• 1958: Integrated Circuit (IC) consisted of multiple transistors interconnected on a single
silicon die.
• 1960s:the IC went into production. Rapid growth characterized by the introduction of ICs
with increasing transistor count and functionality.
• 1965: Gordon Moore, noted that the IC’s “complexity” was roughly doubling every year of
manufacture and predicted that it would continue to do so in the future.
• 1970s, introduction of the microprocessor and the Dynamic Random Access Memory (DRAM)
• 1971: invention of the microprocessor at Intel Corporation.

3. 1.MICROELECTRONICS AND THE TRANSISTOR
• In particular, the timeframe for doubling is a best fit at 24 months for the
microprocessor and 18 months for the DRAM (newly modified Moore’s Law)
• For the microprocessor “complexity” indicates the number of transistors per
device while for the DRAM it is the number of bits per device.
• Packaging and assembly technologies are drived by IC as well as the marketplace
(i.e. end product)
• Marketplace products are driven by requirement for high performance, and by
size and cost.
• To be marketable and remain competitive,next generation models must be
“smaller, better, and cheaper”.
• Electronics Manufacturing Process:starts with the IC through “Packaging Levels” or
“Levels of Interconnection” involving assembly of both bare die and packaged
components.

4. 1.MICROELECTRONICS AND THE TRANSISTOR
• realizing chip level performance
in the end product involves:
1. Identifying and
accommodating the electrical,
mechanical and thermal
requirements inherent in the
IC, and
2. Selecting those manufacturing
technologies that incorporate
attributes that will contribute
to an end product that is
“smaller, better, and
cheaper”.

5. 1.MICROELECTRONICS AND THE TRANSISTOR
• Levels of Interconnect/Packaging
1. Level 1.0—covering the connection (assembly) of the die to a package (SCP) or
substrate (MCP).The interconnect technologies:
(a) Chip and Wire—C&W
(b) Tape Automated Bonding
(c) Flip Chip (FC) Bonding
2. Level 2.0, interconnection of multiple bare die and/or packages through a
substrate interconnect,a printed wiring board (PWB).printed circuit board (PCB) or a
printed wire assembly (PWA) is the board with components attached
3. Level 3.0, assembly to a PWB (motherboard) of multiple Level 2.0 board
assemblies

6. 1.MICROELECTRONICS AND THE TRANSISTOR
• When multiple die are connected to a package/substrate, the substrate must provide the
necessary interconnections between die that is accomplished by an embedded conductor
interconnect network within the package. These package/substrates are manufactured using
thick film/cofired ceramic, thin film or laminate printed wiring board (PWB) processes.
• Silicon (Si), Gallium Arsenide (GaAs) and Silicon Germanium (SiGe) are the semiconductor
materials currently available and used in IC manufacturing.
• the decreasing feature size, the increased functional density and performance, has been
achieved with the starting silicon wafer going from 25 millimeter (mm) diameter to 300 mm.
• Smaller feature size and larger wafers mean more die being realized through common
processes. And more die per wafer equates to lower cost per device.
• Increased functional density means increased complexity. As a consequence the number of
photomasks, the major tool needed to manufacture the IC, has increased from less than 10
to 30 and more.

7. Chip On Board
Chip & Wire
TAB
Flip Chip
Printed Circuit Board (PCB) or Printed Wiring
Board Assembly
(PWBA)

8. IC circa 1970, Single Level Al
Metallization 20 Micrometers~
Minimum Line Width IC circa 2000, Multilevel Metallization
SEM Photomicrograph Multilevel Copper
Interconnect, Minimum
Line Width ~2 micrometers
Single Chip Packaging
Multichip Packaging

9. 1.MICROELECTRONICS AND THE TRANSISTOR
• International Technology Roadmap for Semiconductors
(ITRS), a roadmap presenting an assessment of the
semiconductor industry’s technology requirements
based on the continuing development of the IC.
• An increase in number of I/O pads increases the result
of increased functionality.
• Peripheral format is that the number of I/O pads
needed cannot be allowed to dictate the final chip size.
Chip size must be based on active circuit area
requirements only. Multiple rows will provide additional
I/Os but results in larger die. This in turn means fewer
die per wafer and therefore a higher cost per device.
• The single row peripheral format is designed specifically
for chip & wire assembly
• Area array format allows the entire surface of the IC to
be used for I/O pad terminations.
Peripheral and Area Array I/O formats

10. I/O Capabilities: Peripheral Format vs. Area Array

11. 1.MICROELECTRONICS AND THE TRANSISTOR
• Area array format
packages include Pin or
Pad Grid Arrays (PGA),
and Ball Grid Arrays
(BGA).
• accommodating the high
I/O count, area array also
requires a smaller
footprint on the PWB
Area Array Packages—BGAs