A universal asynchronous receiver-transmitter is a computer hardware device for asynchronous serial communication in which the data format and transmission speeds are configurable.
Logical instruction of 8085
Instruction Set of 8085
Classification of Instruction Set
Logical Instructions
AND, OR, XOR
Logical Instructions
Summary Logical Group
Logical instruction of 8085
Instruction Set of 8085
Classification of Instruction Set
Logical Instructions
AND, OR, XOR
Logical Instructions
Summary Logical Group
DHCP was created by the Dynamic Host Configuration Working Group of the Internet Engineering Task Force. It is a method for assigning Internet Protocol (IP) addresses permanently or to individual computers in an organization’s network.
PAI Unit 2 Protection in 80386 segmentationKanchanPatil34
2015 course SPPU SEIT syllabus of subject Processor Architecture and Interfacing (PAI) This covers protection mechanism in 80386 microprocessor through conforming code segment and call gate
Introduction to Bus | Address, Data, Control BusHem Pokhrel
Handouts for BBa First Semester Prime College.
UNIT 5: Central Processing Unit: Control Unit, Arithmetic and Logic Unit, Register set, Functions of Central Processing Unit. Introduction to Bus (Address, Data, Control)
Communication protocols (like UART, SPI, I2C) play an very important role in Micro-controlled based embedded systems development. These protocols helps the main board to communicate with different peripherals by interfacing mechanism. Here is a presentation that talks about how these protocols actually work.
Introduction to the Data Link Layer, Types of errors, redundancy and coding. Block coding, Error detection, error correction. Linear block codes. Cyclic codes(CRC), Checksum method.
UART Serial Communication Module Design and Simulation Based on VHDLIJERA Editor
UART (Universal Asynchronous Receiver Transmitter) is a kind of serial communication protocol; mostly used for short-distance, low speed, low-cost data exchange between computer and peripherals. During the actual industrial production, sometimes we do not need the full functionality of UART, but simply integrate its core part. UART includes three kernel modules which are the baud rate generator, receiver and transmitter. The UART implemented with VHDL language and simulated using XILINX ISE12.1 to achieve compact, stable and reliable data transmission. It’s significant for the design of SOC. The simulation results are completely consistent.
DHCP was created by the Dynamic Host Configuration Working Group of the Internet Engineering Task Force. It is a method for assigning Internet Protocol (IP) addresses permanently or to individual computers in an organization’s network.
PAI Unit 2 Protection in 80386 segmentationKanchanPatil34
2015 course SPPU SEIT syllabus of subject Processor Architecture and Interfacing (PAI) This covers protection mechanism in 80386 microprocessor through conforming code segment and call gate
Introduction to Bus | Address, Data, Control BusHem Pokhrel
Handouts for BBa First Semester Prime College.
UNIT 5: Central Processing Unit: Control Unit, Arithmetic and Logic Unit, Register set, Functions of Central Processing Unit. Introduction to Bus (Address, Data, Control)
Communication protocols (like UART, SPI, I2C) play an very important role in Micro-controlled based embedded systems development. These protocols helps the main board to communicate with different peripherals by interfacing mechanism. Here is a presentation that talks about how these protocols actually work.
Introduction to the Data Link Layer, Types of errors, redundancy and coding. Block coding, Error detection, error correction. Linear block codes. Cyclic codes(CRC), Checksum method.
UART Serial Communication Module Design and Simulation Based on VHDLIJERA Editor
UART (Universal Asynchronous Receiver Transmitter) is a kind of serial communication protocol; mostly used for short-distance, low speed, low-cost data exchange between computer and peripherals. During the actual industrial production, sometimes we do not need the full functionality of UART, but simply integrate its core part. UART includes three kernel modules which are the baud rate generator, receiver and transmitter. The UART implemented with VHDL language and simulated using XILINX ISE12.1 to achieve compact, stable and reliable data transmission. It’s significant for the design of SOC. The simulation results are completely consistent.
Synthesis & FPGA Implementation of UART IP Soft Coreijsrd.com
this paper presents synthesis and hardware implementation of fully functional Universal Asynchronous Receiver Transmitter Intellectual Property core using XILINX SPARTAN-3 XC3S400 series FPGA. The UART soft core module consists of a transmitter along with baud rate generator and a receiver module with false start bit detection features. This has been implemented using VERILOG hardware description language and synthesized using XILINX ISE development tools. All behavioral simulation of UART module performed using MODELSIM simulator. After successful FPGA implementation transmitter and receiver module was tested by connecting FPGA board with Hyper Terminal software via RS232 interface at a data speed of 9.6 kbps.
Achieving Reduced Area and Power with Multi Bit Flip-Flop When Implemented In...IJERA Editor
A UART (Universal Asynchronous Receiver and Transmitter) is a device allowing the reception and transmission of information, in a serial and asynchronous way. This project focuses on the implementation of UART with status register using multi bit flip-flop and comparing it with UART with status register using single bit flip-flops. During the reception of data, status register indicates parity error, framing error, overrun error and break error. The multi bit flip-flop is indicated in this status register. In modern very large scale integrated circuits, Power reduction and area reduction has become a vital design goal for sophisticated design applications. So in this project the power consumed and area occupied by both multi-bit flip-flop and single bit flip is compared. The underlying idea behind multi-bit flip-flop method is to eliminate total inverter number by sharing the inverters in the flip-flops. Based on the elimination feature of redundant inverters in merging single bit flip-flops into multi bit flip-flops, gives reduction of wired length and this result in reduction of power consumption and area.
Implementation of UART with Status Register using Multi Bit Flip-FlopIJMER
A UART (Universal Asynchronous Receiver and Transmitter) is a device allowing the
reception and transmission of information, in a serial and asynchronous way. This project focuses on
the implementation of UART with status register using multi bit flip-flop. During the reception of data,
status register indicates parity error, framing error, overrun error and break error.In modern very large
scale integrated circuits, Power reduction and area reduction has become a vital design goal for
sophisticated design applications. Multi-bit flip-flop is an effective power saving implementation
methodology by merging single bit flip-flops in the design. The underlying idea behind multi-bit flip-flop
method is to eliminate total inverter number by sharing the inverters in the flip-flops. Based on the
elimination feature of redundant inverters in merging single bit flip-flops into multi bit flip-flops, gives
reduction of wired length and this result in reduction of power consumption and area
Implementation of Universal Asynchronous Receiver and TransmitterIJERA Editor
Universal Asynchronous Receiver Transmitter (UART) is the serial communication protocol that is used for data exchange between computer & peripherals. UART is a low velocity, short-distance, low-cost protocol. UART includes three modules which are received, the baud rate generator and transmitter. The UART design with Very High Description Language can be integrated into the Field Programmable Gate Array to achieve stable data transmission and to make system reliable and compact. In the result and simulation part, this project will focus on check the receive data with error free & baud rate generation at different frequencies. Before synthesizing of UART a baud rate generator is incorporated into the system. We use the frequency divider which sets itself to required frequency for the functionality at lower frequency. All modules are designed using VERILOG and implemented on Xilinx Suite development board.
In telecommunication and computer science, serial communication is the process of sending data one bit at a time, sequentially, over a communication channel or computer bus. This is in contrast to parallel communication, where several bits are sent as a whole, on a link with several parallel channels.
Serial communication is used for all long-haul communication and most computer networks, where the cost of cable and synchronization difficulties make parallel communication impractical. Serial computer buses are becoming more common even at shorter distances, as improved signal integrity and transmission speeds in newer serial technologies have begun to outweigh the parallel bus's advantage of simplicity (no need for serializer and deserializer, or SerDes) and to outstrip its disadvantages (clock skew, interconnect density). The migration from PCI to PCI Express is an example.
WHY CHILDREN ABSORBS MORE MICROWAVE RADIATION THAT ADULTS: THE CONSEQUENCES” ...Shahrukh Javed
In today’s world, technologic developments bring social and economic benefits to large sections of society; however, the health consequences of these developments can be difficult to predict and manage. With rapid advancement in technologies and communications, children are increasingly exposed to MWRs at earlier and earlier ages. Microwave radiation causes damaging health effects, especially for children, whose brains are fragile and still developing. MWR penetration is greater relative to developing brain of fetus and child, and they will have a longer penetration of exposure than adults. This concerns the effects of microwave on health because they pervade diverse fields of our lives. Thus, children are at greater risk than adults when exposed to possible human carcinogen[1], computer simulation using MRI scans of children is the only possible way to determine the microwave radiation (MWR) absorbed in specific tissues in children and this radiation is measured in terms of specific absorption rate[2] (SAR). It also includes an assessment of the potential susceptibility of children to MWR and concludes with a recommendation for additional research in present legal limits for exposure to MWR and the development of precautionary policies in the face of scientific uncertainty.
• UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
• UART is a device that has the capability to both receive and transmit serial data.
• A universal asynchronous receiver-transmitter is a computer hardware device for asynchronous serial communication in which the data format and transmission speeds are configurable.
A heart rate monitor is a personal monitoring device that allows one to measure one's heart rate in real time or record the heart rate for later study. It is largely used by performers of various types of physical exercise.
As the ages of mankind progressed there was a rapid change in the means of transportation with technology starting from the days of bullockcarts to the present days of planes,drones and space shuttles. Travel speed increased from miles/hr to the speed of light.
The source to destination became so closer to each others. There was an advancement in the field of the air traveling system with the help of airplane. But as the speed increases , the horror of air crash also introduced. Because at a height of 2000m and above if a plane crashes ,it will be a terror for any body. So to take the feed back of the various activities happens in the plane and record them engineers need a mechanism to record such activities .
With any airplane crash, there are many unanswered questions as to what brought the plane down. Investigators turn to the airplane's flight data recorder (FDR) and cockpit voice recorder (CVR), also known as "BLACK BOXES" for answers. In recent times these black boxes helped to know answers for many of issues regarding the crashes and may come to help to solve many cases in the future also.so these black boxes play a vital role in this modern world with the advancement of technology
What is wireless power transmission(WPT)?
Why is WPT?
History of WPT
Types of WPT
Techniques to transfer energy wirelessly
Advantages and disadvantages
Applications
Conclusion
References
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Student information management system project report ii.pdfKamal Acharya
Our project explains about the student management. This project mainly explains the various actions related to student details. This project shows some ease in adding, editing and deleting the student details. It also provides a less time consuming process for viewing, adding, editing and deleting the marks of the students.
Hybrid optimization of pumped hydro system and solar- Engr. Abdul-Azeez.pdffxintegritypublishin
Advancements in technology unveil a myriad of electrical and electronic breakthroughs geared towards efficiently harnessing limited resources to meet human energy demands. The optimization of hybrid solar PV panels and pumped hydro energy supply systems plays a pivotal role in utilizing natural resources effectively. This initiative not only benefits humanity but also fosters environmental sustainability. The study investigated the design optimization of these hybrid systems, focusing on understanding solar radiation patterns, identifying geographical influences on solar radiation, formulating a mathematical model for system optimization, and determining the optimal configuration of PV panels and pumped hydro storage. Through a comparative analysis approach and eight weeks of data collection, the study addressed key research questions related to solar radiation patterns and optimal system design. The findings highlighted regions with heightened solar radiation levels, showcasing substantial potential for power generation and emphasizing the system's efficiency. Optimizing system design significantly boosted power generation, promoted renewable energy utilization, and enhanced energy storage capacity. The study underscored the benefits of optimizing hybrid solar PV panels and pumped hydro energy supply systems for sustainable energy usage. Optimizing the design of solar PV panels and pumped hydro energy supply systems as examined across diverse climatic conditions in a developing country, not only enhances power generation but also improves the integration of renewable energy sources and boosts energy storage capacities, particularly beneficial for less economically prosperous regions. Additionally, the study provides valuable insights for advancing energy research in economically viable areas. Recommendations included conducting site-specific assessments, utilizing advanced modeling tools, implementing regular maintenance protocols, and enhancing communication among system components.
Immunizing Image Classifiers Against Localized Adversary Attacksgerogepatton
This paper addresses the vulnerability of deep learning models, particularly convolutional neural networks
(CNN)s, to adversarial attacks and presents a proactive training technique designed to counter them. We
introduce a novel volumization algorithm, which transforms 2D images into 3D volumetric representations.
When combined with 3D convolution and deep curriculum learning optimization (CLO), itsignificantly improves
the immunity of models against localized universal attacks by up to 40%. We evaluate our proposed approach
using contemporary CNN architectures and the modified Canadian Institute for Advanced Research (CIFAR-10
and CIFAR-100) and ImageNet Large Scale Visual Recognition Challenge (ILSVRC12) datasets, showcasing
accuracy improvements over previous techniques. The results indicate that the combination of the volumetric
input and curriculum learning holds significant promise for mitigating adversarial attacks without necessitating
adversary training.
Final project report on grocery store management system..pdfKamal Acharya
In today’s fast-changing business environment, it’s extremely important to be able to respond to client needs in the most effective and timely manner. If your customers wish to see your business online and have instant access to your products or services.
Online Grocery Store is an e-commerce website, which retails various grocery products. This project allows viewing various products available enables registered users to purchase desired products instantly using Paytm, UPI payment processor (Instant Pay) and also can place order by using Cash on Delivery (Pay Later) option. This project provides an easy access to Administrators and Managers to view orders placed using Pay Later and Instant Pay options.
In order to develop an e-commerce website, a number of Technologies must be studied and understood. These include multi-tiered architecture, server and client-side scripting techniques, implementation technologies, programming language (such as PHP, HTML, CSS, JavaScript) and MySQL relational databases. This is a project with the objective to develop a basic website where a consumer is provided with a shopping cart website and also to know about the technologies used to develop such a website.
This document will discuss each of the underlying technologies to create and implement an e- commerce website.
Cosmetic shop management system project report.pdfKamal Acharya
Buying new cosmetic products is difficult. It can even be scary for those who have sensitive skin and are prone to skin trouble. The information needed to alleviate this problem is on the back of each product, but it's thought to interpret those ingredient lists unless you have a background in chemistry.
Instead of buying and hoping for the best, we can use data science to help us predict which products may be good fits for us. It includes various function programs to do the above mentioned tasks.
Data file handling has been effectively used in the program.
The automated cosmetic shop management system should deal with the automation of general workflow and administration process of the shop. The main processes of the system focus on customer's request where the system is able to search the most appropriate products and deliver it to the customers. It should help the employees to quickly identify the list of cosmetic product that have reached the minimum quantity and also keep a track of expired date for each cosmetic product. It should help the employees to find the rack number in which the product is placed.It is also Faster and more efficient way.
About
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
• Remote control: Parallel or serial interface.
• Compatible with MAFI CCR system.
• Compatible with IDM8000 CCR.
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
• Easy in configuration using DIP switches.
Technical Specifications
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
Key Features
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
• Remote control: Parallel or serial interface
• Compatible with MAFI CCR system
• Copatiable with IDM8000 CCR
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
Application
• Remote control: Parallel or serial interface.
• Compatible with MAFI CCR system.
• Compatible with IDM8000 CCR.
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
• Easy in configuration using DIP switches.
Saudi Arabia stands as a titan in the global energy landscape, renowned for its abundant oil and gas resources. It's the largest exporter of petroleum and holds some of the world's most significant reserves. Let's delve into the top 10 oil and gas projects shaping Saudi Arabia's energy future in 2024.
2. 2 Project Report - UART
April19,2009
S.No Topic Page No.
1. PROJECT STATEMENT 3
2. FUNCTIONAL SPECIFICATIONS
INTRODUCTION 3
BASIC CONCEPT 3
SERIAL CONNECTION 4
APPROACH 4
SYSTEM DIAGRAM 5
FUNCTIONAL BLOCK DIAGRAM 6
3. WORKING
TRANSMITTER 7
RECEIVER 8
4. SIMULATIONS 9
5. RTL SCHEMATIC
TRANSMITTER 10
RECEIVER 11
6. SYNTHESIS REPORT AND TIMING ANALYSIS 12
7. POST PLACE AND ROUTE SIMULATION 17
8. RUNNING ON ACTUAL HARDWARE
BASIC STEPS 18
HYPERTERMINAL SETUP 18
9. VERIFICATION STRATEGY 21
10. REFERENCES 21
3. 3 Project Report - UART
April19,2009
PROJECT STATEMENT
Develop a Verilog based UART (Universal Asynchronous Receiver and Transmitter), and demonstrate its
working (as both transmitter and receiver) by interfacing it to Microsoft Windows HyperTerminal.
FUNCTIONAL SPECIFICATIONS
Introduction
UART is a device that has the capability to both receive and transmit serial data. UART
exchanges text data in an American Standard Code for Information Interchange (ASCII) format in
which each alphabetical character is encoded by 7 bits and transmitted as 8 data bits. For
transmission the UART protocol wraps this 8 bit subword with a start bit in the least significant
bit (LSB) and a stop bit in the most significant bit (MSB) resulting in a 10 bit word format.
Start Data 0 Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Stop
Basic Concept
UART transmitter controls transmission by fetching a data word in parallel format and directing
the UART to transmit it in a serial format. Likewise, the Receiver must detect transmission,
receive the data in serial format, strip of the start and stop bits, and store the data word in a
parallel format.
Since the UART is asynchronous in working, the receiver does not know when the data will
come, so receiver generate local clock in order to synchronize to transmitter whenever start bit
is received. Asynchronous transmission allows data to be transmitted without the sender having
to send a clock signal to the receiver. The transmitter and receiver agree on timing parameters
in advance and special bits are added to each word which is used to synchronize the sending
and receiving units.
When a word is given to the UART for Asynchronous transmission, a bit called the “Start Bit” is
added to the beginning of each word that is to be transmitted. The Star Bit is used to alert the
receiver that a word of data is about to be sent, and to force the clock in the receiver into
synchronization with the clock in the transmitter. After the Start Bit, the individual bits of the
word of data are sent, with the Least Significant Bit (LSB) being sent first. Each bit in the
transmission is transmitted for exactly the same amount of time as all of the other bits, and the
receiver “looks” at the wire at approximately halfway through the period assigned to each bit to
determine if the bit is a 1 or a 0. For example, if it takes two seconds to send each bit, the
receiver will examine the signal to determine if it is a 1 or a 0 after one second has passed, then
it will wait two seconds and then examine the value of the next bit, and so on. Then at least one
4. 4 Project Report - UART
April19,2009
Stop Bit is sent by the transmitter. Because asynchronous data is “self synchronous”, if there is
no data to transmit, the transmission line can be idle.
Serial Connection
Serial Port used for UART is RS-232. It is a nine pin connector with each pin assigned with
different functionality.
Approach
We approached the given problem statement by implementing the UART receiver and
transmitter independently. First we tried to implement the UART transmitter due to its less
complexity in working and implementation. We used 9600 BAUD rate for transmission of serial
data and divided the system clock accordingly. Then we started to implement the UART
receiver. We learned the concept of clock synchronization by taking the clock many times higher
that the transmitting rate. For this we generated clock which is 8 times the transmitter BAUD
rate to minimize the distortions in the incoming data. We followed the Finite State Machine
(FSM) approach to code both UART transmitter and receiver.
5. 5 Project Report - UART
April19,2009
System Diagram
HyperTerminal
(Transmitted Data) Spartan 3E
8 – LEDs
4–PushButton
4-Switches
RS- 232
Single Bit Transmission
Single Bit Transmission
8 Bits
8Bits
Select
Load
Shift
Received Data
Reset
The above figure shows the overall working of the UART and the HyperTerminal. UART as
transmitter takes 8 – bit data from the switches and then transmits it bitwise through the
RS-232 port and is displayed on the HyperTerminal of target machine. The “load switch” is used
to load the transmit register of the UART and the “shift switch” is used to shift the data out from
the shift register of the UART. UART as a receiver accepts the 8 – bit data word from the
HyperTerminal through the RS-232 port and displays it on the LED’s. The clock used by the UART
receiver is 8 times the clock of the transmitter.
6. 6 Project Report - UART
April19,2009
Functional Block Diagram
o Transmitter
Where
[7:0] din 8 bit data to be transmitted.
Load loads the transmit register with the data.
Shift shifts the data out from the shift register.
[1:0] select for selecting din.
[3:0] CS FSM state output.
Ready indicates when ready to receive data to transmit.
o Receiver
[7:0] din
load
shift
[1:0] select
reset
clk1
UART
Transmitter
Datapath
Controller
[3:0] CS
ready
UART
Receiver
Datapath
Controller
read_not_ready_out
shift
load
Error1
Error2
clr_Sample_counter
inc_Sample_counter
clr_Bit_counter
inc_Bit_counter
read_not_ready_in
Serial_in
Sample_counter
Bit_counter
Sample_clk1
enable
7. 7 Project Report - UART
April19,2009
Where
read_not_ready_in signals that the host is not ready to receive data.
Serial_in serial bit stream received by the unit.
enable active enable bit.
Sample_counter counts the samples of a bit.
Bit_counter counts the bits that have been sampled.
read_not_ready_out signals that the receiver has received 8 bits.
inc_sample_counter increments Sample_counter.
clr_Sample_counter clears Sample_counter.
inc_Bit_counter increments Bit_counter.
clr_Bit_counter clears Bit_counter.
load causes RCV_shftreg to transfer data to RCV_datareg.
shift causes RCV_shftreg to shift towards the LSB.
Error1 asserts if host is not ready to receive data.
Error2 asserts if the stop bit is missing.
WORKING
Transmitter
UART_idle
UART_stopbit
UART_bit0
UART_bit1
UART_bit2
UART_bit3
UART_bit5
UART_startbit
UART_bit7
UART_bit6
UART_bit4
readyandshift
shift
shift
shift
shift
shift
shift
shift
shift
shift
!readyandshift
else
else
else
else
else
else
else
else
else
else
else
reset
UARTTransmitterFSM
9. 9 Project Report - UART
April19,2009
SIMULATIONS
Transmitter
Receiver
We didn’t see the simulation results for the UART receiver and implemented the design directly
on chip which produced the desired results.
13. 13 Project Report - UART
April19,2009
# FDE : 6
# FDPE : 9
# FDR : 32
# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 11
# IBUF : 5
# OBUF : 6
=========================================================================
Device utilization summary:
---------------------------
Selected Device : 3s500efg320-5
Number of Slices: 35 out of 4656 0%
Number of Slice Flip Flops: 52 out of 9312 0%
Number of 4 input LUTs: 66 out of 9312 0%
Number of IOs: 12
Number of bonded IOBs: 12 out of 232 5%
Number of GCLKs: 1 out of 24 4%
==========================================================================
o Timing Report
==============================================================================
Clock Information:
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk1 | BUFGP | 33 |
clock | NONE(Hold_2) | 19 |
-----------------------------------+------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR
resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help
prevent skew problems.
Asynchronous Control Signals Information:
----------------------------------------
-----------------------------------+------------------------+-------+
Control Signal | Buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
reset | IBUF | 14 |
-----------------------------------+------------------------+-------+
14. 14 Project Report - UART
April19,2009
Timing Summary:
---------------
Speed Grade: -5
Minimum period: 6.207ns (Maximum Frequency: 161.095MHz)
Minimum input arrival time before clock: 6.804ns
Maximum output required time after clock: 4.655ns
Maximum combinational path delay: No path found
=========================================================================
Timing constraint: Default period analysis for Clock 'clock'
Clock period: 6.207ns (frequency: 161.095MHz)
Total number of paths / destination ports: 173 / 24
-------------------------------------------------------------------------
Delay: 6.207ns (Levels of Logic = 3)
Source: CS_0 (FF)
Destination: ready (FF)
Source Clock: clock rising
Destination Clock: clock rising
Receiver
o Synthesis Report
=========================================================================
HDL Synthesis Report
Macro Statistics
# Counters : 3
32-bit up counter : 1
4-bit up counter : 1
5-bit up counter : 1
# Registers : 3
1-bit register : 1
8-bit register : 2
# Comparators : 1
4-bit comparator less : 1
=========================================================================
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : UART_RX.ngr
Top Level Output File Name : UART_RX
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
15. 15 Project Report - UART
April19,2009
# IOs : 15
Cell Usage :
# BELS : 143
# GND : 1
# INV : 5
# LUT1 : 31
# LUT2 : 3
# LUT2_L : 1
# LUT3 : 7
# LUT3_L : 1
# LUT4 : 19
# LUT4_D : 2
# MUXCY : 39
# MUXF5 : 2
# VCC : 1
# XORCY : 31
# FlipFlops/Latches : 60
# FDE : 1
# FDR : 33
# FDRE : 25
# FDRS : 1
# Clock Buffers : 2
# BUFG : 1
# BUFGP : 1
# IO Buffers : 14
# IBUF : 3
# OBUF : 11
=========================================================================
Device utilization summary:
---------------------------
Selected Device : 3s500efg320-5
Number of Slices: 42 out of 4656 0%
Number of Slice Flip Flops: 60 out of 9312 0%
Number of 4 input LUTs: 69 out of 9312 0%
Number of IOs: 15
Number of bonded IOBs: 15 out of 232 6%
Number of GCLKs: 2 out of 24 8%
=========================================================================
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o Timing Report
=========================================================================
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
Sample_clk1 | BUFGP | 33 |
Sample_clk2 | BUFG | 27 |
-----------------------------------+------------------------+-------+
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -5
Minimum period: 5.790ns (Maximum Frequency: 172.701MHz)
Minimum input arrival time before clock: 5.624ns
Maximum output required time after clock: 9.315ns
Maximum combinational path delay: 6.543ns
=========================================================================
Timing constraint: Default period analysis for Clock 'Sample_clk2'
Clock period: 5.790ns (frequency: 172.701MHz)
Total number of paths / destination ports: 405 / 61
-------------------------------------------------------------------------
Delay: 5.790ns (Levels of Logic = 3)
Source: Sample_counter_3 (FF)
Destination: Sample_counter_0 (FF)
Source Clock: Sample_clk2 rising
Destination Clock: Sample_clk2 rising
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POST PLACE AND ROUTE SIMULATION
Floor plan
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RUNNING ON ACTUAL HARDWARE
Basic Steps
In Xilinx click on Generate Programming File and then when it is complete click on
Configure device (iMPACT).
Then program the chip using this utility and on successful completion we will get an
alert.
Now we are ready to use it on hardware.
We then have to configure the HyperTerminal as explained in next section.
Now for receiver code if we type something on HyperTerminal, the value will be
reflected on LEDs and in transmitter anything given from switches will be displayed on
HyperTerminal.
For transmitter first we select from two switches what we want to send. Then we reset,
followed by load followed by shift. The character chosen will be then displayed on
HyperTerminal.
For receiver first we need to put on the enable switch and then anything typed on
HyperTerminal will be displayed on LEDs.
HyperTerminal Setup
Figure 1: New Connection Screen
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VERIFICATION STRATEGY
For verification we followed the White Box Testing approach. While doing testing, we took into
consideration following points:
Is the data being sent from HyperTerminal is displayed properly on LEDs.
Are we able to see the desired data on HyperTerminal when we send something from FPGA?
Is the sample clock (8 times transmission clock) generated properly?
We did simulations for both transmitter and receiver (not giving the simulation but working fine
with hardware) on Xilinx ISE and the results are displayed in the Simulation section above.
We calculated the Hexadecimal values of all the characters by hand and then matched the
results of the kit with the calculations done by hand.
For black box testing we gave different inputs and observed the outputs and matched them with
desired ones which are beforehand known.
If the sample clock generated at the receiver is not 8 times the transmitter clock then the output
will differ from those of the correct ones.
REFERENCES
Advance Digital Design using Verilog HDL by Michael D Ciletti.
http://bwrc.eecs.berkeley.edu/people/grad_students/tinas/Fall04SFSU852/Lectures/UARTTrans
mitterdoneinclassRev1.doc
http://www.lammertbies.nl/comm/info/serial-uart.html
http://www.linksprite.com/images/UART-RS232-1.jpg
http://www.cyq.com/htdocs/hyperterminal.htm
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ANNEXURE A
Transmitter
//------------------------------------------------------------------------
---------
// Uart Transmit Module
//
// Author: Akshay Soni (200601148)
// Tanvi Sharma (200601196)
//
// parameters:
// din.........8 bit bus of data that is to be sent out
// load........This signal write the data to a holding register and sets a
Ready flag to let the
// transmitter know that there is data ready to go
out.
// clk1........system clock.
// reset.......system reset, returns uart to an idle state and clears
ready.
// shift.......signal to let the system know when it is time to shift a
bit(this is the baud rate).
// txd.........transmit data output.
// ready.......status: 0 indicates no data in holding register.
// status: 1 indicates holding register is full.
//------------------------------------------------------------------------
--------------------------
module uarttx(load,clk1,reset,shift,txd,ready,CS,select);
input load; // loads the transmit register
input clk1; // 1x transmit clock
input reset; // resets the registers
input [1:0] select; // to select the data to be transmitted
input shift; // this is when the shift register is supposed
to shift
output txd; // output data
output ready; // indicates ready to recieve char to transmit
output [3:0]CS; // states of the output
reg ready; // ready status bit
reg txd; // transmit bit
reg [8:0] INT; // nine bit shift register
reg [7:0] Hold; // holding register for the data
reg doshift; // tells the shift register to shift its data
reg doload; // tells the shift register to load its data
reg clearready; // tells the ready bit to clear
reg setready; // tells the ready bit to set
reg clock = 1'b0;
reg [7:0] din = 8'h61; // data to be transmitted
integer a = 0; // integer used for clock division
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always @(select)
begin
case(select)
2'b00: din = 8'h62;
2'b01: din = 8'h63;
2'b10: din = 8'h64;
2'b11: din = 8'h65;
default: din = 8'h61;
endcase
end
always @(posedge clk1)
begin
if(a == 2604)
begin
a = 0;
clock = ~clock;
end
else
a = a+1;
end
always @(posedge clock)
begin
if(load)
begin
Hold <= din; //load data into holding register
end
end
always @(load)
if(load)
setready <= 1;
else
setready <= 0;
//------------------------------------------------------------------------
// Uart State machine
//
// LSB is the first bit to be transmitted in UART transmission.
// But the naming of the states is different from that.
//
//------------------------------------------------------------------------
-
parameter [3:0]
UART_IDLE = 4'b0000,
UART_STARTBIT = 4'b0001,
UART_BIT7 = 4'b0010,
UART_BIT6 = 4'b0011,
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UART_BIT5 = 4'b0100,
UART_BIT4 = 4'b0101,
UART_BIT3 = 4'b0110,
UART_BIT2 = 4'b0111,
UART_BIT1 = 4'b1000,
UART_BIT0 = 4'b1001,
UART_STOPBIT = 4'b1010;
// Declaration of current state and next state variables
reg [3:0] CS;
reg [3:0] NS;
always @ (posedge clock or posedge reset)
begin
if (reset) CS <= UART_IDLE;
else CS <= NS;
end
always @ (CS or ready or shift)
begin
case (CS) // case statement for the states
UART_IDLE: begin
if (ready && shift) begin
NS <= UART_STARTBIT;
doshift = 0;
doload = 1; //load data into shift register
clearready = 1; //clear ready bit
end
else begin
NS <= UART_IDLE;
doshift = 0;
doload = 0;
clearready = 0;
end
end
UART_STARTBIT: begin
if(shift) begin
NS <= UART_BIT7; //go to next state
doshift = 1; //shift data out register
doload = 0;
clearready = 0;
end
else begin
NS <= UART_STARTBIT; //hold this state
doshift = 0;
doload = 0;
clearready = 0;
end
end
UART_BIT7: begin
if(shift) begin
NS <= UART_BIT6; //go to next state
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doshift = 1; //shift data out register
doload = 0;
clearready = 0;
end
else begin
NS <= UART_BIT7; //hold this state
doshift = 0;
doload = 0;
clearready = 0;
end
end
UART_BIT6: begin
if(shift) begin
NS <= UART_BIT5; //go to next state
doshift = 1; //shift data out register
doload = 0;
clearready = 0;
end
else begin
NS <= UART_BIT6; //hold this state
doshift = 0;
doload = 0;
clearready = 0;
end
end
UART_BIT5: begin
if(shift) begin
NS <= UART_BIT4; //go to next state
doshift = 1; //shift data out register
doload = 0;
clearready = 0;
end
else begin
NS <= UART_BIT5; //hold this state
doshift = 0;
doload = 0;
clearready = 0;
end
end
UART_BIT4: begin
if(shift) begin
NS <= UART_BIT3; //go to next state
doshift = 1; //shift data out register
doload = 0;
clearready = 0;
end
else begin
NS <= UART_BIT4; //hold this state
doshift = 0;
doload = 0;
clearready = 0;
end
end
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UART_BIT3: begin
if(shift) begin
NS <= UART_BIT2; //go to next state
doshift = 1; //shift data out register
doload = 0;
clearready = 0;
end
else begin
NS <= UART_BIT3; //hold this state
doshift = 0;
doload = 0;
clearready = 0;
end
end
UART_BIT2: begin
if(shift) begin
NS <= UART_BIT1; //go to next state
doshift = 1; //shift data out register
doload = 0;
clearready = 0;
end
else begin
NS <= UART_BIT2; //hold this state
doshift = 0;
doload = 0;
clearready = 0;
end
end
UART_BIT1: begin
if(shift) begin
NS <= UART_BIT0; //go to next state
doshift = 1; //shift data out register
doload = 0;
clearready = 0;
end
else begin
NS <= UART_BIT1; //hold this state
doshift = 0;
doload = 0;
clearready = 0;
end
end
UART_BIT0: begin
if(shift) begin
NS <= UART_STOPBIT; //go to next state
doshift = 1; //shift data out register
doload = 0;
clearready = 0;
end
else begin
NS <= UART_BIT0; //hold this state
doshift = 0;
doload = 0;
clearready = 0;
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end
end
UART_STOPBIT: begin
if(shift && !ready) begin
NS <= UART_IDLE; //nothing more to do,
so idle
doshift = 0;
doload = 0;
clearready = 0;
end
else if (shift && ready) begin
NS <= UART_STARTBIT; //another byte waiting,
go do it
doshift = 0;
doload = 1;
//load data into shift register
clearready = 1; //clear ready bit
end
else begin
NS <= UART_STOPBIT; //hold this state
doshift = 0;
doload = 0;
clearready = 0;
end
end
default: begin
doshift = 0;
doload = 0;
clearready = 0;
NS <= UART_IDLE;
end
endcase
end
//---------------------------------------------------------------
// shift register
//
// shift register can do a load, and do a shift
//---------------------------------------------------------------
always @(posedge clock or posedge reset)
begin
if(reset) begin
INT <= 9'b111111111; //reset transmit register to all 1's
end
else begin
if(doload) begin
INT <= {Hold,1'b0}; //load data and set start bit to 0
txd <= INT[0];
end
else if (doshift) begin
INT <= {1'b1,INT[8:1]}; //shift data, shift in 1's
txd <= INT[0];
end
else begin
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INT <= INT; //hold data
txd <= INT[0];
end
end
end
//---------------------------------------------------------------
// ready status bit
// when status == 1, this indicates that there is data waiting
// in the data holding register ready to be
// transmitted.
// when status == 0, data holding register is empty
//---------------------------------------------------------------
always @ (posedge clock or posedge reset)
begin
if(reset)
ready <= 0; //always not ready at reset
else begin
if(setready)
ready <= 1;
else if(clearready)
ready <= 0;
else
ready <= ready; //hold ready
end
end
endmodule