This document describes a project to design a robust UART architecture using a recursive running sum filter for better noise performance. It discusses adding noise to communication channels to test noise performance. It then describes implementing a UART receiver using a recursive running sum filter to reduce noise while maintaining signal integrity. The UART design is tested on a Nexys3 Spartan-6 FPGA board in Xilinx ISE using VHDL. Simulation results at different noise levels show the filter is effective at reducing noise.

1. A Robust UART
Architecture Based on
Recursive Running
Sum Filter for Better
Noise Performance

2. Project Outline:
Why?
Electronic communications devices that operate in environments
with a high level of electromagnetic noise require special
consideration and testing to ensure the continuous delivery of
uncorrupted data.
What?
Additive white Gaussian noise (AWGN) is a basic noise model used
in Information theory to mimic the effect of many random processes
that occur in nature.
Solution:-
In this project we describes a novel architecture ofUniversal
Asynchronous Receiver Transmitter (UART)based on Recursive
Running Sum (RRS) filter.

3. Tools Used
Software
 Xilinx ISE Design Suite 14.1
 Xilinx PlanAhead 14.1
 Modelsim SE-64 10.1c
 MATLAB R2013a
 X-CTU
 Digilent Adept
Hardware
 Nexys3 Spartan-6 FPGA Board(XC6LX16-CS324)

4. Serial Communication:UART
The Universal Asynchronous Receiver/Transmitter (UART) controller is the
key component of a serial communication system.
The UART takes bytes of data and transmits the individual bits in a
sequential fashion. At the destination, a second UART re-assembles the bits
into complete bytes.
Thus the UART protocol can be explained in terms of two sub systems.
 Transmitter
 Receiver

5. Character framing in UART
•The idle, no data state is high-voltage, or powered.
•The start bit (logic low)signals the receiver that a new character is
coming.
•A configurable number of data bits (usually 8, but users can choose 5 to
8 or 9 bits depending on which UART is in use), an optional parity bit if
the number of bits per character chosen is not 9 .
•Since the start bit is logic low (0) and the stop bit is logic high (1) thus
there are always at least two guaranteed signal changes between
characters.

6. Baud rate & Baud rate pre-scaler
The baud rate of a data communications system is the number of symbols per
second transferred. It is the number of distinct symbol changes (signaling
events) made to the transmission medium per second in a
digitally modulated signal or a line code.
A baud rate of 9600 baud is chosen as it is one of the most commonly used
baud values in pc’s and communication equipment. It is a rate neither too
high nor too low for smooth data transfer.
The system clock drives all the logic blocks on the FPGA. If we time each bit to
be transmitted within a clock cycle it may lead to logic hazards. Thus to scale
down the rate at which bits are being transmitted we use a baud rate pre-
scaler or scaling factor.
Baud rate = 9600
Clock rate = 100Mhz.
Prescaler=Clock rate/ Baud rate=10416.667~10416

7. UART Transmitter
Step 1: Start
Step 2: Declare entity tx with input clk, start and an
array data of size 8 of type std_logic. The outputs are busy &
tx_lineof type std_logic.
Step 3: Begin Architecture with signals prscl, index of
integer type and datafl, txflag of std_logic type.
Step 4: Insert start bit and stop bit at positions 0 & 9 of
datafl as 0& 1 respectively.
Step 5: Check if clk is high ,txflag is zero and start is one,
else go to next step . If conditions are true set txflag and
busy. Move contents of data to datafl(8-1).
Step 6: Increment prscl by one as long as its less than
10416.When prscl reaches 5208 move all values in datafl to
tx_line. Simultaneously check whether index is less than 9 and
increment index in steps of unity.
Step 7: When index is 9 set tx_flag, busy and index to zero
indicating transmission of 8bits is over.
Step 8: Stop

8. UART Receiver
Step 1: Start
Step 2: Declare entity rx with input cl, rx_line of type std_logic. The
outputs are busy , data_ok and an array data of size 8of type std_logic.
Step 3: Begin Architecture with signals prscl, index of integer type and
datafl, rxflag of std_logic type
Step 4:. Check whether clk is high, rx_flag& rx_line are zero else go to next
step. If so set busy & rx_flag and reset index & prscl.
Step 5: Reset data_ok.
Step 6: Check whether rx_flag is set ,if condition is true and prscl is less
then 10416, continue to incriment it in steps of one. When prscl is 5208 move
contents of rx_line to datafl. Simultaneously check if index is less than 9 ,
continue to increment index.
Step 7: Check if start(0) and stop(1) bits are correct in data_fl if so move
data_fl(8-1) to data.
Step 8: Restore rx_flag , busy to initial value of zero and set data_ok.
Step 9: Stop Uart

9. Transmittersimulation
Receiver simulation

10. Simulink Description

11. Simulation Results
Input:-
Variance=1:-

12. Variance=2:-
Variance=4:-

13. Matlab Analysis with variation in
SNR
SNR=30

14. SNR=25
SNR=20
SNR=15

15. SNR=10

16. Recursive running sum filter
As the name implies, the running sum filter operates by summing a number
of points from the input signal to produce each point in the output signal.
In spite of its simplicity, the running sum filter is optimalfor reducing random
noise while retaining a sharp step response.
𝐻 𝑧 =
1 − 𝑧−𝑀
1 − 𝑧−1

17. Implementation of filter in UART
Receiver
Step 1:Start.
Step 2:Declare entity uartsampl with clk,rx as the input ports and tx as the output
port.
Step 3:Begin architecture named behavioral.
Step 4:Begin process sensitive to change in either clk or rx.
Step 5:Declare variables
 prssclkcnt: Counter for prescale clock, integer type,intialy 0.
 sampleclkcnt : Counter for sample clock, integer type,intialy 0.
 uartclkcnt: Counter for UART clock, integer type,intialy 0.
 prssclk , sampleclk, uartclk : Clocks for UART receiver, sampling incoming bits
and prscaling uart clocking respectively. All are initially 0 & type stdlogic.
 sample: Sample variable similar to a counter of type integer with initial value 5.
 dtem : Is a temporary data variable of type stdlogic with initial value 1.
 rcvmd: Flag register of type stdlogic initially low. It turns high when reception
has begun.
 buff: 10 bit logic vector dedicated to storing received signal. Initially all bits are
0.
 bcnt: Keeps count of values stored in buff. It is of type integer ,initially 0.

18. Step 6: During the rising edge of clk toggle prssclk 26 times with prssclkcnt
keeping count.
Step 7: Sample each incoming bit 10 times. The sampleclk is toggled 260 times
,this count is handled by sampleclkcnt. If a sample taken has high value sample is
incremented.
Step 8: The uartclk is toggled 2604 times within each rising edge of clk . The
count is handled by uartclkcnt.
 If the value of sample currently is greater than 5 assign dtem=1.Else
dtem=0.Initila value of sample = 5 allows us to prevent misinterpreting noise for
signal.
 Check if dtem and rcvmd are 0.This implies start bit has been received .Thus
now we can set rcvmd as 1.
 If rcvmd is 1 ,i.e., start bit received correctly and valid signal is incoming store
subsequent values of dtem to buff(bcnt).
value of bcnt is varied from 0 to 9.
 Check if stop bit is received correctly, else reset buff to”0000000000”.
Step 9:Stop.

19. Spartan 6 – Nexys 3
• The Nexys3 is a complete, ready-to-use
digital circuit development platform based
on the Xilinx Spartan-6 LX16 FPGA.
• Xilinx Spartan-6 LX16 FPGA in a 324-pin
BGA package
• Consist of four 6 input LUTS & 8 FF
• 16Mbyte Cellular RAM (x16)
• 32 DSP slices
• 10/100 Ethernet PHY
• On-board USB2 port for programming &
data xfer
• USB-UART and USB-HID port (for
mouse/keyboard)
• 100MHz CMOS oscillator
• 500 Mhz+ clock speed
• GPIO includes 8 LEDs, 5 buttons,8 slide
switches and 4-digit seven-segment display
• USB2 programming cable included

20. DesignSummary
file:///C:/Users/User/Desktop/Uart/Uart/rs232/uart/uart_sum
mary.html

21. REFERENCE
• FANG Yi-yuan and CHEN Xue-jun, Design and simulation of uart serial
communication module based on vhdl, may 2014
• MAHESH GIRI & P. P. SHINGARE, Design and implementation of uart using
vhdl on fpga, vol.2, issue 5, may 2014
• Ms.Neha R. Laddha and Prof.A.P.Thakare, Implementation of serial
communication using UART with configurable baud rate, vol.1, issue 4,2014