The 80486 microprocessor features an integrated math coprocessor that is 3 times faster than the 80386/387 combination. It has an 8KB internal code and data cache and uses a 168-pin PGA package. New signals support burst mode memory access and bus sharing. The 80486 includes parity checking/generation and additional page table entry bits control internal caching.

19. GENERAL PURPOSE REGISTERS INSTRUCTION POINTER AND FLAG REGISTER SEGMENT REGISTERS CODE SEGMENT DATA SEGMENT CS SS DS ES FS GS EIP EFLAGS IP FLAGS 0 16 31 15 ESP EBP EDI ESI EDX ECX EBX EAX SP BP DI SI DX CX BX AX 0 16 31 15 STACK SEGMENT

20. CF VM RF 0 NT IOPL OF IF TF SF ZF 0 AF 0 PF 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 DF 16 17 18 31 RESERVED FOR INTEL E F L A G FLAGS Flag Register of 80486 AC CF: Carry Flag AF: Auxiliary carry ZF: Zero Flag SF : Sign Flag TF : Trap Flag IE : Interrupt Enable DF : Direct Flag OF : Over Flow IOPL : I/O Privilege Level NT : Nested Task Flag RF : Resume Flag VM : Virtual Mode AC : Alignment Check

22. P A R I T Y 1 G X 8 ___ BE 3 ___ BE 2 ___ BE 1 ___ BE 0 1 G X 8 1 G X 8 1 G X 8 P A R I T Y P A R I T Y P A R I T Y DP 3 D 31 - D 24 DP 2 DP 1 DP 0 D 23 - D 16 D 15 - D 8 D 7 - D 0

25. P E M P E M T S N E W P A M W T C E P G 31 16 15 0 Control Register Zero ( CR 0 )For The 80486 Microprocessor

28. P R W U S P W T P C D A D O O OS BITS PAGE TABLE OR PAGE FRAME Page Directory or Page Table Entry For The 80486 Microprocessor 31 0 1 2 3 4 5 6 7 8 9 10 11 12

31. 0 31 31 31 0 0 Con Ent Set select Tag Valid LRU Bits Valid bits 3 7 11 11 10 2 4 3 Cache test register of the 80486 microprocessor TR 3

32. GENERAL PURPOSE REGISTERS INSTRUCTION POINTER AND FLAG REGISTER SEGMENT REGISTERS CODE SEGMENT DATA SEGMENT CS SS DS ES FS GS EIP EFLAGS IP FLAGS 0 16 31 15 ESP EBP EDI ESI EDX ECX EBX EAX SP BP DI SI DX CX BX AX 0 16 31 15 STACK SEGMENT