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1. A.S.M. Bakibillah et al Int. Journal of Engineering Research and Applications www.ijera.com
ISSN : 2248-9622, Vol. 4, Issue 5( Version 7), May 2014, pp.89-91
www.ijera.com 89 | P a g e
Effect of Oxide Charge and Interface Traps on Drain Current
Degradation of Vertical Silicon Tunneling Field Effect Transistors
A.S.M. Bakibillah* and Md. Sohel Rana**
*(Institute of Semiconductor Engineering, University of Stuttgart, Germany)
** (School of Engineering and Information Technology, the University of New South Wales, Australia)
ABSTRACT
In this Paper, we present reliability performance of vertical Si Tunneling Field Effect Transistors (TFETs) in
device geometry with tunneling in-line with the gate electric field by physical analysis and experimental results.
Analyzing transfer characteristics of the fabricated devices by Keithley 4200 (semiconductor parameter
analyzer) we show the degradation mechanism of drain current because of the presence of oxide charge and
interface traps at the tunneling region. The experimental result compared to theoretical calculation is reasonable.
We provide further suggestions to minimize this effect for improved device performance.
Keywords - Device reliability, drain current degradation, interface traps, oxide charge, tunneling field-effect
transistor (TFET)
I. INTRODUCTION
As the Si based Complementary Metal-
Oxide-Semiconductor (CMOS) technology
approaching its edge of miniaturization; it becomes
necessary to investigate new technologies to extend
device performance [1]. The incoming technology
should contain some important features such as faster
operation, energy efficiency and more functionality
per unit area and time at reasonable cost. As an
alternative solution, tunneling field effect transistor
(TFET) is receiving much attention because of its
low power operation, high on current and faster
switching speed with sub-threshold swing lower than
60 mV/dec at room temperature compared to
conventional MOSFETs [2-3]. The electron-hole
tunneling probability in TFETs assists to achieve the
lower sub-threshold slope whereas the current
switching process in MOSFETs depends on the
thermionic injections in which carriers must
surmount a particular height of an energy barrier that
defines the steepness of the transition slope. Till now
the investigations of TFETs are mainly focused on
the understanding of basic device characteristics and
fabrication technology [4-5]. Among them the
vertical TFETs with particular geometry modification
has been achieved considerable attention [6-7].
However, research outcomes on the reliability
performance of TFETs are not available yet. This
paper demonstrates the effect of oxide charge and
interface traps on drain current degradation which has
an impact on device performance and reliability of
vertical Si TFETs.
II. EXPERIMENT AND ANALYSIS
For our reliability experiments the v-groove
vertical Si TFETs were fabricated with layer
sequence as follows: 200 nm of p++-Si (1020
cm-3
) as
source region, 50 nm of i-Si, 50 nm of n+-Si (1018
cm-3
) drain region and finally, 150 nm of n++-Si
(1020
cm-3
) to ensure ohmic contacts shown in Fig.
1(a). The deposition of active layers is performed by
Molecular Beam Epitaxy (MBE). Another layer of i-
Si with a thickness of di = 7 nm is deposited as an
extended channel at 700 °C in a second MBE step. A
SiO2 gate oxide is deposited by Plasma Enhanced
Chemical Vapor Deposition (PECVD) at a
temperature of 390 °C. The Layer thickness of the
gate oxide is chosen to be 20 nm because as far as the
PECVD - oxides are concerned, films with a
thickness below 20 nm have a problem with leakage
currents and make the measurement of transistors
difficult. An SEM image of a finished device is
shown in Fig. 1(b).
(a)
RESEARCH ARTICLE OPEN ACCESS

2. A.S.M. Bakibillah et al Int. Journal of Engineering Research and Applications www.ijera.com
ISSN : 2248-9622, Vol. 4, Issue 5( Version 7), May 2014, pp.89-91
www.ijera.com 90 | P a g e
(b)
Fig. 1. (a) Schematic cross section of a v- groove
vertical Si TFET. The arrows indicate the possible
tunneling directions (b) SEM image of the device.
The dotted line indicates the cut along which the
schematic cross section shown in Fig. 1(a). The inset
at the lower left corner shows the etching profile of
the mesa and trench sidewalls.
The transmission probability at the tunnel
junction region of TFETs can be described by
Wentzel–Kramer–Brillouin approximation [8-9] for
the band-to-band tunneling (BTBT) phenomena and
is given by:
Where m*
denotes the effective mass of the
carriers, Eg is the bandgap energy and λ is the
screening tunneling length that illustrates the
extension of the source channel interface thus the
transition region which depends on device geometry.
Since the thickness of the gate oxide has a direct
impact on the electrostatic screening length, λ (as a
result it has an effect on transmission probability
shown by equation 1) and PECVD oxides are
deposited, the process variations in the gate oxide
introduces a disparity in the performance of the
fabricated devices. Again, in Si TFETs, the interface
traps can be both acceptor and donor-like traps where
the acceptor-like traps normally exist at energies
above the Si midgap while the donor-like traps exist
at energies below the Si midgap and are uniformly
distributed through the channel region. The oxide
charge can be either positive or negative charges that
exist in the gate region. In principle the drain current
degradation is caused by the gate oxide charge and
interface traps which is located above the tunneling
region and has a negative impact on the tunneling
field near junction region as well as on the tunneling
current.
III. RESULTS AND DISCUSSION
The transfer characteristics of the v-groove
transistors are measured using Keithley 4200 at a
temperature of 300 K for different gate voltages with
Vds = 0.5 V. The characterization data from the
analyzer is then plotted and analyzed again using
MatLab and there found a deviation in the
characteristics curves due to the presence of oxide
charge and interface traps which has a direct impact
on drain current as shown in Fig. 2 and Fig. 3
respectively.
-6 -4 -2 0 2 4 6 8 10 12 14
10
-10
10
-9
10
-8
10
-7
10
-6
10
-5
Vgs (V)
Id(A)
di
=7nm
Vds
=0.5V
dox
=20nm
I´on
=7.1040e-07
reduced drain current
no oxide-charge
oxide charge Qot
~6×1011
cm-2
Fig. 2. Id-Vgs curves with and without the gate oxide
charge and effect of oxide charge on the degradation
of drain current Id.. The oxide charge is located in the
SiO2.
It is found that the reduction of Id is mainly
due to the presence of oxide charge located very near
to the tunneling junction and is uniformly distributed.
The charge exist in the gate region introduces a gate
capacitance. In this experiment the PECVD gate
oxide is characterized separately by MOS
capacitances and found to contain Qot ∼ 6×1011
cm−2
of charges which degrades the drain current by an
amount of 7.1040 × 10-7
A.
-10 -5 0 5 10 15
10
-10
10
-9
10
-8
10
-7
10
-6
Vgs (V)
Id(A)
di
=7nm
Vds
=0.5V
dox
=20nm
reduced drain current
I´on
=9.2070e-08
no interface-trap
interface trap Dit
~1.1×1012
cm-2
.eV-1
Fig. 3. Id-Vgs curves with and without the interface
traps and Effect of interface traps on the degradation
of drain current Id.

3. A.S.M. Bakibillah et al Int. Journal of Engineering Research and Applications www.ijera.com
ISSN : 2248-9622, Vol. 4, Issue 5( Version 7), May 2014, pp.89-91
www.ijera.com 91 | P a g e
Similar to the case of gate oxide charge,
only the traps located very near to the tunneling
junction has effect on Id degradation. Here the
interface state density is found to be Dit ∼ 1.1 × 1012
cm−2
· eV−1
that causes the reduction of Id by 9.2070
× 10-8 A.
The reduction of drain current occurs in
TFET devices due to interface traps causes
degradation in transconductance while the gate oxide
charges introduce a shift in sub-threshold swing. To
understand the root of transfer characteristics shift
because of interface traps and gate oxide charge, the
drain current given by the Kane’s (BTBT) model can
be assumed [10] and given by:
Where the tunneling field is given by E =
E(VDS, VGS, DIT, QOT), A and B denote constants, and
DIT and QOT characterize the interface traps and gate
oxide charge respectively. A small modification in
the field E may cause a large change in the tunneling
current Id. From the above equation (2), it is clear that
the tunneling field is modified near the source region
by the existence of any interface traps and/or oxide
charge which in turn reduces the tunneling current.
IV. CONCLUSION
In this paper we have demonstrated the
degradation mechanism in vertical Si TFET. The
effect of oxide charge and interface traps is shown on
the drain current as a parameter of TFET device
performance and reliability. Currently we are only
able to fabricate thermal and PECVD oxides in our
clean room. Since the thickness of the i-Si layer
deposited during the second MBE step is a critical
parameter, we chose not to use the thermal oxide as a
gate oxide. For PECVD-oxides, films with a
thickness below 20 nm have a problem with leakage
currents as discussed above. Future improvements
will include an improvement of the gate oxide as well
as a reduction in the thickness of the i-Si channel
layer for further enhancement of device performance
and reduce the effect of oxide charge and interface
traps.
V. ACKNOWLEDGEMENT
This work at the Institute of Semiconductor
Engineering, University of Stuttgart, was supported
in part by the Deutsche Forschungsgemeinschaft
under Grant FI 1511/2-1.
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