The document discusses a presentation given by Ashish Kumar Singh on his research investigating heterojunction silicon-on-insulator tunnel field effect transistors. The presentation outline includes an introduction discussing challenges with MOSFET scaling, the history and state-of-the-art of TFET research, the basic structure and operation of TFETs, investigations of Ge-source/Si strained SOI TFETs, a proposed Ge-source SOI TFET with oxide overlap, analytical modeling of the proposed device, conclusions and future work.
Analytical Modeling of Tunneling Field Effect Transistor (TFET)Abu Obayda
Tunneling Field-Effect Transistor (TFET) has emerged as an alternative for conventional CMOS by enabling the supply voltage, VDD, scaling in ultra-low power, energy efficient computing, due to its sub-60 mV/decade sub-threshold slope (SS). Given its unique device characteristics such as the asymmetrical source/drain design induced unidirectional conduction, enhanced on-state Miller capacitance effect and steep switching at low voltages, TFET based circuit design requires strong interactions between the device-level and the circuit-level to explore the performance benefits, with certain modifications of the conventional CMOS circuits to achieve the functionality and optimal energy efficiency. Because TFET operates at low supply voltage range (VDD<0.5V) to outperform CMOS, reliability issues can have profound impact on the circuit design from the practical application perspective. In this thesis report, we have analyzed the drain current characteristics of TFET with respect channel length. From our simulation result, it is observed that the drain current is minimum with respect to increasing channel length for Si and the drain current decreases for all the materials when the channel length is increased and after normalization lowest value of drain current is got for 10nm channel length.
Analytical Modeling of Tunneling Field Effect Transistor (TFET)Abu Obayda
Tunneling Field-Effect Transistor (TFET) has emerged as an alternative for conventional CMOS by enabling the supply voltage, VDD, scaling in ultra-low power, energy efficient computing, due to its sub-60 mV/decade sub-threshold slope (SS). Given its unique device characteristics such as the asymmetrical source/drain design induced unidirectional conduction, enhanced on-state Miller capacitance effect and steep switching at low voltages, TFET based circuit design requires strong interactions between the device-level and the circuit-level to explore the performance benefits, with certain modifications of the conventional CMOS circuits to achieve the functionality and optimal energy efficiency. Because TFET operates at low supply voltage range (VDD<0.5V) to outperform CMOS, reliability issues can have profound impact on the circuit design from the practical application perspective. In this thesis report, we have analyzed the drain current characteristics of TFET with respect channel length. From our simulation result, it is observed that the drain current is minimum with respect to increasing channel length for Si and the drain current decreases for all the materials when the channel length is increased and after normalization lowest value of drain current is got for 10nm channel length.
Reduced channel length cause departures from long channel behaviour as two-dimensional potential distribution and high electric fields give birth to Short channel effects.
Multiple gate field effect transistors foreSAT Journals
Abstract
This is a review paper on the topic of multiple gate field effect transistors: MuGFETs, or FinFETs, as they are called. First, the motivation behind multiple gate FETs is presented. This is followed by looking at the evolution of FinFET technologies; the main flavors (variants) of Multigate FETs; and their advantages/disadvantages. The physics and technology of these devices is briefly discussed. Results are then presented which show the performance figures of merit of FinFETs, and their strengths and weaknesses. Finally, a perspective on the future of the FinFET technology is presented. Keywords: CMOS scaling, Double gate MOSFET, FinFET, Multiple gate FET, Multigate FET
A Study On Double Gate Field Effect Transistor For Area And Cost Efficiencypaperpublications3
Abstract: Proposal for a field effect transistor had been presented, with numerical device simulations to verify the title in every manner possible. The two transitional field effect transistors like pMOS and nMOS functions are simultaneously performed, working as one or as the other according to the voltage applied to the gate terminal. Increase in the circuit speed is observed when this technology is implemented on the device suggested with respect to the standard CMOS technology, presented a drastic reduction of number devices and associated parasitic capacitances. In addition to it IC obtained with the proposed device are fully compatible with the standard CMOS technology and the fabrication processes. Fabrication of Static Ram cells with three transistors only with minimum dimensions and a single bit line by saving silicon area and increasing the memory performance with respect to standard CMOS technologies. It is also presented that the fully compatible CMOS process can be used to successfully manufacture the new FET structure.
DC performance analysis of a 20nm gate length n-type Silicon GAA junctionless...IJECEIAES
With integrated circuit scales in the 22-nm regime, conventional planar MOSFETs have approached the limit of their potential performance. To overcome short channel effects 'SCEs' that appears for deeply scaled MOSFETs beyond 10nm technology node many new device structures and channel materials have been proposed. Among these devices such as Gate-all-around FET. Recentely, junctionless GAA MOSFETs JL-GAA MOSFETs have attracted much attention since the junctionless MOSFET has been presented. In this paper, DC characteristics of an n-type JL-GAA MOSFET are presented using a 3-D quantum transport model. This new generation device is conceived with the same doping concentration level in its channel source/drain allowing to reduce fabrication complexity. The performance of our 3D JL-GAA structure with a 20nm gate length and a rectangular cross section have been obtained using SILVACO TCAD tools allowing also to study short channel effects. Our device reveals a favorable on/off current ratio and better SCE characteristics compared to an inversionmode GAA transistor. Our device reveals a threshold voltage of 0.55 V, a sub-threshold slope of 63mV / decade which approaches the ideal value, an Ion/Ioff ratio of 10e + 10 value and a drain induced barrier lowring (DIBL) value of 98mV/V.
Reduced channel length cause departures from long channel behaviour as two-dimensional potential distribution and high electric fields give birth to Short channel effects.
Multiple gate field effect transistors foreSAT Journals
Abstract
This is a review paper on the topic of multiple gate field effect transistors: MuGFETs, or FinFETs, as they are called. First, the motivation behind multiple gate FETs is presented. This is followed by looking at the evolution of FinFET technologies; the main flavors (variants) of Multigate FETs; and their advantages/disadvantages. The physics and technology of these devices is briefly discussed. Results are then presented which show the performance figures of merit of FinFETs, and their strengths and weaknesses. Finally, a perspective on the future of the FinFET technology is presented. Keywords: CMOS scaling, Double gate MOSFET, FinFET, Multiple gate FET, Multigate FET
A Study On Double Gate Field Effect Transistor For Area And Cost Efficiencypaperpublications3
Abstract: Proposal for a field effect transistor had been presented, with numerical device simulations to verify the title in every manner possible. The two transitional field effect transistors like pMOS and nMOS functions are simultaneously performed, working as one or as the other according to the voltage applied to the gate terminal. Increase in the circuit speed is observed when this technology is implemented on the device suggested with respect to the standard CMOS technology, presented a drastic reduction of number devices and associated parasitic capacitances. In addition to it IC obtained with the proposed device are fully compatible with the standard CMOS technology and the fabrication processes. Fabrication of Static Ram cells with three transistors only with minimum dimensions and a single bit line by saving silicon area and increasing the memory performance with respect to standard CMOS technologies. It is also presented that the fully compatible CMOS process can be used to successfully manufacture the new FET structure.
DC performance analysis of a 20nm gate length n-type Silicon GAA junctionless...IJECEIAES
With integrated circuit scales in the 22-nm regime, conventional planar MOSFETs have approached the limit of their potential performance. To overcome short channel effects 'SCEs' that appears for deeply scaled MOSFETs beyond 10nm technology node many new device structures and channel materials have been proposed. Among these devices such as Gate-all-around FET. Recentely, junctionless GAA MOSFETs JL-GAA MOSFETs have attracted much attention since the junctionless MOSFET has been presented. In this paper, DC characteristics of an n-type JL-GAA MOSFET are presented using a 3-D quantum transport model. This new generation device is conceived with the same doping concentration level in its channel source/drain allowing to reduce fabrication complexity. The performance of our 3D JL-GAA structure with a 20nm gate length and a rectangular cross section have been obtained using SILVACO TCAD tools allowing also to study short channel effects. Our device reveals a favorable on/off current ratio and better SCE characteristics compared to an inversionmode GAA transistor. Our device reveals a threshold voltage of 0.55 V, a sub-threshold slope of 63mV / decade which approaches the ideal value, an Ion/Ioff ratio of 10e + 10 value and a drain induced barrier lowring (DIBL) value of 98mV/V.
Electrical characterization of si nanowire GAA-TFET based on dimensions downs...IJECEIAES
This research paper explains the effect of the dimensions of Gate-all-around Si nanowire tunneling field effect transistor (GAA Si-NW TFET) on ON/OFF current ratio, drain induces barrier lowering (DIBL), sub-threshold swing (SS), and threshold voltage (V T ). These parameters are critical factors of the characteristics of tunnel field effect transistors. The Silvaco TCAD has been used to study the electrical characteristics of Si-NW TFET. Output (gate voltage-drain current) characteristics with channel dimensions were simulated. Results show that 50nm long nanowires with 9nm-18nm diameter and 3nm oxide thickness tend to have the best nanowire tunnel field effect transistor (Si-NW TFET) characteristics.
Investigation and design of ion-implanted MOSFET based on (18 nm) channel lengthTELKOMNIKA JOURNAL
The aim of this study is to invistgate the characteristics of Si-MOSFET with 18 nm length of ion implemented channel. Technology computer aided design (TCAD) tool from Silvaco was used to simulate the MOSFET’s designed structure in this research. The results indicate that the MOSFET with 18 nm channel length has cut-off frequency of 548 GHz and transconductance of 967 μS, which are the most important factors in calculating the efficiency and improving the performance of the device. Also, it has threshold voltage of (-0.17 V) in addition obtaining a relatively small DIBL (55.11 mV/V). The subthreshold slope was in high value of 307.5 mV/dec. and this is one of the undesirable factors for the device results by short channel effect, but it does not reduce its performance and efficiency in general.
Structural and Electrical Analysis of Various MOSFET DesignsIJERA Editor
Invention of Transistor is the foundation of electronics industry. Metal Oxide Semiconductor Field Effect Transistor (MOSFET) has been the key to the development of nano electronics technology. This paper offers a brief review of some of the most popular MOSFET structure designs. The scaling down of planar bulk MOSFET proposed by the Moore’s Law has been saturated due to short channel effects and DIBL. Due to this alternative approaches has been considered to overcome the problems at lower node technology. SOI and FinFET technologies are promising candidates in this area.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Performance analysis of ultrathin junctionless double gate vertical MOSFETsjournalBEEI
The main challenge in MOSFET minituarization is to form an ultra-shallow source/drain (S/D) junction with high doping concentration gradient, which requires an intricate S/D and channel engineering. Junctionless MOSFET configuration is an alternative solution for this issue as the junction and doping gradients is totally eliminated. A process simulation has been developed to investigate the impact of junctionless configuration on the double-gate vertical MOSFET. The result proves that the performance of junctionless double-gate vertical MOSFETs (JLDGVM) are superior to the conventional junctioned double-gate vertical MOSFETs (JDGVM). The results reveal that the drain current (ID) of the n-JLVDGM and p-JLVDGM could be tremendously enhanced by 57% and 60% respectively as the junctionless configuration was applied to the double-gate vertical MOSFET. In addition, junctionless devices also exhibit larger ION/IOFF ratio and smaller subthreshold slope compared to the junction devices, implying that the junctionless devices have better power consumption and faster switching capability.
Microelectronic technology
This report briefly discusses the need for Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs), their structure and principle of operation. Then it details the fabrication and characterization of the MOSFETs fabricated at the microelectronic lab at University of Malaya
shows the simulation and analysis of a MOSFET device using the MOSFet tool. Several powerful analytic features of this tool are demonstrated, including the following:
calculation of Id-Vg curves
potential contour plots along the device at equilibrium and at the final applied bias
electron density contour plots along the device at equilibrium and at the final applied bias
spatial doping profile along the device
1D spatial potential profile along the device
Design & Performance Analysis of DG-MOSFET for Reduction of Short Channel Eff...IJERA Editor
An aggressive scaling of conventional MOSFETs channel length reduces below 100nm and gate oxide thickness below 3nm to improved performance and packaging density. Due to this scaling short channel effect (SCEs) like threshold voltage, Subthreshold slope, ON current and OFF current plays a major role in determining the performance of scaled devices. The double gate (DG) MOSFETS are electro-statically superior to a single gate (SG) MOSFET and allows for additional gate length scaling. Simulation work on both devices has been carried out and presented in paper. The comparative study had been carried out for threshold voltage (VT), Subthreshold slope (Sub VT), ION and IOFF Current. It is observed that DG MOSFET provide good control on leakage current over conventional Bulk (Single Gate) MOSFET. The VT (Threshold Voltage) is 2.7 times greater than & ION of DG MOSFET is 2.2 times smaller than the conventional Bulk (Single Gate) MOSFET.
Please read the following IEEE Spectrum articles and answer the quest.pdffasttrackcomputersol
Please read the following IEEE Spectrum articles and answer the questions given. You may
want to use illustrations in your answer to the questions, and mark them up accordingly as part of
answering the questions. If you take illustrations from some source (including the IEEE
Spectrum articles) please make sure this is properly cited.
http://spectrum.ieee.org/semiconductors/nanotechnology/the-next-highperformance-transistor-
could-be-made-from-lateral-nanowires Describe a FINFET and how it works. How is it different
than the planar MOSFET described in the first 5 slides of the TFET lecture? Is the FINFET a
quantum device? Give reasons why or why not. How is the nanowire device described here
different than the FINFET? Why is this difference an advantage for the nanowire device? They
one problem with the nanowire device is capacitive coupling. What is this and explain why it is a
problem with the nanowire device?
Solution
1)
The FinFET technology promises to provide the deliver superior levels of scalability needed to
ensure that the current progress with increased levels of integration within integrated circuits can
be maintained.
The FinFET offers many advantages in terms of IC processing that mean that it has been adopted
as a major way forwards for incorporation within IC technology.
FinFET technology has been born as a result of the relentless increase in the levels of
integration. The basic tenet of Moore\'s law has held true for many years from the earliest years
of integrated circuit technology. Essentially it states that the number of transistors on a given
area of silicon doubles every two years.
Some of the landmark chips of the relatively early integrated circuit era had a low transistor
count even though they were advanced for the time. The 6800 microprocessor for example had
just 5000 transistors. Todays have many orders of magnitude more.
basically what is finfet??
FinFET technology takes its name from the fact that the FET structure used looks like a set of
fins when viewed.
The main characteristic of the FinFET is that it has a conducting channel wrapped by a thin
silicon \"fin\" from which it gains its name. The thickness of the fin determines the effective
channel length of the device.
In terms of its structure, it typically has a vertical fin on a substrate which runs between a larger
drain and source area. This protrudes vertically above the substrate as a fin.
The gate orientation is at right angles to the vertical fin. And to traverse from one side of the fin
to the other it wraps over the fin, enabling it to interface with three side of the fin or channel.
This form of gate structure provides improved electrical control over the channel conduction and
it helps reduce leakage current levels and overcomes some other short-channel effects..
The term FinFET is used somewhat generically. Sometimes it is used to describe any fin-based,
multigate transistor architecture regardless of number of gates.
Due to the increased emphas.
Simulation study of single event effects sensitivity on commercial power MOSF...journalBEEI
High-frequency semiconductor devices are key components for advanced power electronic system that require fast switching speed. Power Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is the most famous electronic device that are used in much power electronic system. However, the application such as space borne, military and communication system needs Power MOSFET to withstand in radiation environments. This is very challenging for the engineer to develop a device that continuously operated without changing its electrical behavior due to radiation. Therefore, the main objective of this study is to investigate the Single Event Effect (SEE) sensitivity by using Heavy Ion Radiation on the commercial Power MOSFET. A simulation study using Sentaurus Synopsys TCAD software for process simulation and device simulation was done. The simulation results reveal that single heavy ion radiation has affected the device structure and fluctuate the I-V characteristic of commercial Power MOSFET.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Overview of the fundamental roles in Hydropower generation and the components involved in wider Electrical Engineering.
This paper presents the design and construction of hydroelectric dams from the hydrologist’s survey of the valley before construction, all aspects and involved disciplines, fluid dynamics, structural engineering, generation and mains frequency regulation to the very transmission of power through the network in the United Kingdom.
Author: Robbie Edward Sayers
Collaborators and co editors: Charlie Sims and Connor Healey.
(C) 2024 Robbie E. Sayers
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Governing Equations for Fundamental Aerodynamics_Anderson2010.pdf
SOTA.pptx
1. URSI Regional Conference on Radio Science (URSI RCRS 2020)
Investigation of Heterojunction Silicon-on-Insulator Tunnel field Effect
Transistor in Nanometer Era
PRESENTED BY
ASHISH KUMAR SINGH
PHD RESEARCH SCHOLAR
DEPARTMENT OF ELECTRONICS ENGINEERING
INDIAN INSTITUTE OF TECHNOLOGY
(BHU),VARANASI, INDIA
7/30/2022 1
2. 7/30/2022 2
Introduction
Basic Structure and Operating Principle of TFET
History and State-of-the-Art
Investigation of Ge-source/Si Strained SOI TFET
Proposed Ge-Source SOI TFET with Oxide Overlap
2D Analytical Model of the Proposed Device
2D Analytical Gate Threshold Voltage Model of the Proposed Device
Conclusions and Future work
Publications
References
OUTLINE
3. 7/30/2022 3
Chapter 1: Introduction
Chapter 2: History and State-of-the -Art
Chapter 3: TFET: Basic Structure and Operation Principle
Chapter 4: Investigation of Ge-source/Si Strained SOI TFET
Chapter 5: Proposed Ge-Source SOI TFET with Oxide Overlap
Chapter 6: 2D Analytical Model of the Proposed Device
Chapter 7: 2D Analytical Gate Threshold Voltage Model of the Proposed Device
Chapter 8: Conclusions and Future work
Organization of the Thesis
4. 7/30/2022 4
Subthreshold Leakage Current.
Short channel Effects.
Gate Tunneling Currents.
Time Dependent Dielectric Breakdown.
Limitation of MOSFET
5. 7/30/2022 5
New ideas, technologies, concepts and alternative devices will be required for continued
performance improvements.
Scaling: Tunneling field effect transistor (TFET) designs do not suffer from short channel
effects
Power Dissipation: TFETs can beat the 60 mV/decade sub-threshold swing of MOSFETs
Design Flexibility: Circuits can be made with fewer devices.
Introduction
6. 7/30/2022 6
In nanometer regime, the technology is facing many critical challenges and reliability
issues.
Aggressive scaling of MOSFET has resulted in short channel effects and exponential rise
in leakage current.
To mitigate these issues, Tunnel FET is extensively studied. This is considered to be the
most promising devices for possible applications in future VLSI.
Introduction
7. 30 July 2022 7
In nanometer regime, the technology is facing many critical challenges and
reliability issues.
Aggressive scaling of MOSFET has resulted in short channel effects and
exponential rise in leakage current.
To mitigate these issues, Carbon nanotubes and Nanowire–FETs are
extensively studied.
These are considered to be the most promising devices for possible
applications in future VLSI.
8. 7/30/2022 8
MOSFET vs. TFET
MOSFET:
• Classical device
• High ION
• SS > 60mV/dec
TFET:
• Quantum device
• Extremely Low IOFF
• SS < 60mV/dec
• Low ION
MOSFET
TFET
9. 7/30/2022 9
TFET can allow lower sub-threshold swing for lower operating voltages.
High Ion/Ioff ratio ( > 107).
Fabrication of TFET compared to other alternative devices is compatible with standard CMOS
processing since it can be implemented as a reverse biased gate p-i-n diode.
Leads to chips that consume less power.
Negative differential resistance (NDR) properties can be exploited to create simpler designs.
Chapter-1
Introduction
11. 7/30/2022 11
Tunneling is a quantum mechanical phenomenon with no analog in classical physics.
It occurs when an electron passes through a potential barrier without having enough
energy to do so.
The mathematical formulations of quantum tunneling is Schrödinger formulations
presents an interesting phenomenon where a particle tunnels through an energy
barrier.
Band-to band tunneling is the quantum mechanical phenomena in which the electrons
“tunnel” across the energy gap of the semiconductor.
For direct tunneling , an electrons travels from the valance band to the conduction band
without the absorption or emission of phonon.
In the indirect tunneling process, the tunneling particle acquires by change in
momentum by absorbing and emitting the phonon.
Quantum Tunneling
12. 30 July 2022 12
Chapter-2
Semiconductor industry is looking for different materials and devices to integrate with
the current silicon based technology in a long term future.
Tunnel FET is found to be the most promising candidate in this context.
Much progress has been made in recent years showing that TFETs can outperform the
state of the art silicon FETs in many ways.
History and State-of-the-art
13. 7/30/2022 13
The key point of this device is that the gate overlapping with the source is essential to make surface inversion.
Oxide thickness used are 15nm and 20nm; Doping varies from 1E17/cm3 to 1E19/cm3 .
If doping is higher 1E19/cm3, the surface electric fields are high and most of the voltage drop across oxide and there is less band gap of band bending in Si.
If the doping density is lower 1E17/cm3 although the band bending is large, the depletion regions are too wide to allow significant tunneling.
If the doping density is 1E18/cm3 then there is onset of current at Vg= Vd = 3 V with oxide thickness 15 nm.
If the oxide thickness will increase the tunnel current decreases because the electric field in the Silicon at the same voltage will decrease.
In 1987, Banerjee et al. at Texas Instruments studied the behavior of a three-terminal silicon tunnel device using a p- -region instead of an intrinsic region under
the gate.
Banerjee et al. in 1987
14. 7/30/2022 14
First experiment al demonstration of three terminal TFET with Ion=10-6uA/um @VGS=-5V.
Tunneling barrier is formed when a negative bias is applied to the gate creating an accumulation layer underneath the oxide.
The device has the potential for much improved performance over existing transistors because of the tunneling nature.
Reddick and Amaratunga at Cambridge reported experiments on silicon surface tunnel transistors.. They were motivated by the desire for devices that would be
faster than conventional MOSFETs, as tunneling devices are, and that could be scaled down more easily without running into problems such as punchthrough.
Reddick et al. in 1995
15. 7/30/2022 15
They fabricated a Si vertical TFET to also gate the Zener side of the tunnel junction and noted its potential for low off-current relative to the MOSFET.
n+ is source and p+ is drain and Pt and Ti/W is gate.
Threshold Voltage is almost 3 mV.
.
Hansch et al. in 2000
16. 7/30/2022 16
Optimization of electrical parameters of a vertical TFET
SiGe replaced the silicon delta layer already used by Hansch, and in theory, the smaller
bandgap should have reduced the tunnel barrier width and increased tunneling current in the
on-state as well as lowering the subthreshold swing.
Effect of mole fraction in subthreshold swing
δp Si is replaced by δp SiGe
With SiGe, the tunneling currents increases with increasing x, and therefore Vt is lower
significantly.
Bhuwalka et al. in 2004
17. 7/30/2022 17
Studied the scaling properties of TEFT device for 130 nm,90 nm and 65 nm node.
For 130 nm node the Vt is very high and causes the degradation of the ON current at supply voltage
of 1.5 V.
For 90 nm node, the ON current is improved by factor of 10 ,Vt reduced, subthreshold swing of 75
mV/decade and DIBL is only 60mV which is comparable to the MOSFET..
For 65 nm node, the ON current is improved by factor of 10 ,Vt reduced more ,subthreshold swing of
78 mV/decade ,DIBL is only 15mV and OFF current is 14 pA/um.
.
Nirschl et al. in 2006
18. 7/30/2022 18
S & D doped with 1020 cm-3 and the p-type body doped with 1017 cm-3, L = 50 nm,
tdielectric = 3 nm, and tSi = 5 nm. Vd = 1 V.
Using a high-κ gate dielectric showing an ON-current as high as 0.23 mA for a gate voltage
of 1.8 V, an OFF-current of less than 1 fA, an improved average subthreshold swing of 57
mV/dec, and a minimum point slope of 11 mV/dec.
As temperature increases, Ioff increases, but Ion changes very little. Slopes are only
slightly affected by changes in temperature.
On current increases and decreases the subthreshold swing as the gate dielectric constant
increases.
K. Boucart in 2007
19. 7/30/2022 19
Threshold voltage is 0.12 V.
Ion 12.1 μA / μm and 5.4 nA / μm
Subthreshold swing depends upon oxide thickness and SOI layer thickness.
The use of lower EOT ,lower bandgap material and more abrupt source doping profile will increase
ON current .
High-k material can be used.
Choi et al. in 2007
20. 7/30/2022 20
Ion = 300uA/um and SS~50mV/decade
Reduce the amipolarity by using the hetrostructure of large bandgap material at the drain side to reduce the tunneling.
.
Krishnamohan et al. in 2008
21. 7/30/2022 21
First experitmental investigation on SOI,GeOI and Si1-x Gex TFET.
Introducing a novel TFET architecture to solve the ambipolar nature called
the DFET( Drift TFET) by increasing the OFF current.
Small bandgap material is used to increase the ON current.
Intrinsic area Si is responsible for reducing ambipolarity.
SiN is used as protection layer to avoid the undesired silicidation of the
area.
Mayer et al. in 2008
22. 7/30/2022 22
Ge in the source of an n-channel TFET, record high ION/IOFF
ratio (>106) is achieved for low-voltage (0.5V) operation.
ION(μA/μm) = 0.42
IOFF(pA/μm) = 0.12
ION/IOFF = 3E6
Not discussed about subthreshold swing.
Kim et al., in 2009
23. 7/30/2022 23
This paper study the sensitivity to parameter fluctuations for an optimized double-gate silicon Tunnel FET with a high-k
gate dielectric.
Boucart et al., in 2010
25. 7/30/2022 25
Steepest SS (<60mV/decade) ever reported in a III-V TFET
Heterojunction TFET shows steeper SS over a wider range of ID than the homojunction
TFET.
Electrical oxide thickness (EOT) scaling and increased source doping in tandem with
tunnel barrier height reduction are shown to greatly improve the SS of the III-V TFETs
and increase ID by more than 20X.
Dewey et al., in 2011
26. 7/30/2022 26
ION enhancements over n-channel
In0:53Ga0:47As Homj-TFET are
experimentally demonstrated by
utilizing i) a staggered GaAs0:5Sb0:5
source and ii) an N+ pocket (δ)-doped
channel.
Hetj-TFET showing the maximum ION of
60 μA/μm at VGS = 2.5 V. at VDS = 0.75 V.
Mohata et al., in 2011
27. 7/30/2022 27
Ion reaches ∼140 μA/μm at Vgs = 1.2 V and Vds = 0.5 V for a Ge content of 50%.
SS is less than 60 mV/dec for a very large Id range.
With increasing Ge content, the on-current increases due to the reduced band-
gap energy.
The key steps include very thin Si layer growth, steep doping in the SiGe layer,
and selective etch of the SiGe layer.
Zhao et al., in 2011
28. 7/30/2022 28
P-type Be-doped (NA = ~5×1016 cm-3) In0.53Ga0.47
Gallium doped P+ Ge-source .
Gate stack comprising 5.6-nm Al2O3 and 120-nm TaN was formed.
.
Guo et al., in 2012
29. 7/30/2022 29
.
Chang et al., in 2012
SS is 46 mV/dec at 1 pA/μm
ION/IOFF ratio is 1.4×107
ION is 1.4 μA/μm
IOFF is 0.1 pA/μm
30. 7/30/2022 30
epi-Ge HTFET shows the subthreshold swing from 120–240 mV/dec with IDS = 10−11–
10−10 A/μm, which is smaller than Si TFET.
epi-Ge device shows drain current as high as 11 μA/μm at VGS = VDS = −2 V, which
enhances 2.3 times as compared with that of Si HTFET.
Lee et al., in 2013
31. 7/30/2022 31
By lowering the supply voltage below 0.5 V, up to 10× reduction of the energy delay product is
feasible by using area tunneling devices.
Different VT is achieved by varying doping concentration in epitaxial layer.
.
Rajoriya et al. in 2013
32. 7/30/2022 32
High Subthreshold Swing
Low on current
High threshold voltage
High Miller capacitance
Lack of Modeling of Tunnel FET
Major Limitations of the TFET
35. 7/30/2022 35
I vs. characteristics for different channel length L .
DS GS
V
I vs. characteristics for different oxide thickness .
DS GS ox
V t
36. 7/30/2022 36
I vs. characteristics for different dielectric materials.
DS GS
V I vs. characteristics for different doping
levels of homo and hetero junction SOI-TFET.
DS GS
V
37. 7/30/2022 37
I vs. characteristicsfor different overlaps
of proposed homo and hetero junction SOI-TFET.
DS GS
V DS GS
I vs. V characteristicsfor different overlaps for different
overlaps/underlaps of proposed hetero junction SOI TFET
38. 7/30/2022 38
Impact of Ge-concentration
. characteristics for different Ge concentration.
DS GS
I vs V . characteristics for different Ge concentration.
DS DS
I vs V
39. 7/30/2022 39
. characteristics for different Ge concentration.
C vs V
a
b
c
d
Impact of Ge concentration on (a) /I ratio b
c d V using CC and TC method.
ON OFF m
out t
I g
R
40. 7/30/2022 40
Chapter 5
Proposed Ge-source SOI-TFET with Oxide Overlap
Cross sectional view conventional
of proposed Ge-source SOI-TFET.
Cross sectional view of gate overlap
on Ge-source of propose SOI-TFET.
Cross sectional view of oxide overlap
on Ge-source of propose SOI-TFET.
41. 7/30/2022 41
Energy band along the channel for conventional TFET,
oxide overlap and gate overlap of the proposed device.
42. 7/30/2022 42
. and . characteristic for conventional TFET, oxide overlap and gate overlap
of the proposed device
DS GS DS DS
I vs V I vs V
43. 7/30/2022 43
Normalized - characteristics and - characteristics for conventional TFET, oxide overlap and
gate overlap of the proposed device.
gd DS
C V C V
44. 7/30/2022 44
Proposed Ge-Source SOI TFET with Oxide Overlap
. for different dielectric materials.
DS GS
I vs V
. for different V
DS GS DS
I vs V
45. 7/30/2022 45
Drain voltage variation for the a Point and Average Subthreshold Swing
b Threshold volta Transconductance
ge using CC and TC method c
d / ratio of the proposed device.
m
ON OFF
g
I I
a
c
b
d
46. 7/30/2022 46
Process Flow of the Proposed Device
2 2
a SOI wafer b gate stack consisting of AlN/ HfO , Aluminum, LTO gate-hardmask and HfO gate-sidewall
spacers on source were deposited and patterned c drain region is implanted with As+ and the source regio
n etche-
disotropically to form oxide-to-source overlap area d Ge is selectively deposited only.
a
b
c
d
47. References
VDD(V)
Gate
Length
(µm)
ION
(µA/um)
IOFF
(pA/um)
ION/IOFF
SS@
(1nA/µm)
(mV/dec)
Steepest SS
(mV/dec)
EOT
(nm)
Body Structure
W.M. Reddick
et al.[5]
5 3µm 0.01 0.1 105 >600 >600 24 Bulk Si
P.F. Wang
et al. [17] 3 100 nm 0.02 10 2x103 450 375 6 Bulk Si
W.Y. Choi
et al. [18]
1 70nm 12.1 1000 1.2x104 60 52.8 2
SOI
TSi= 70 nm
F. Mayer
et.al [19]
1 0.02 1 2x104 330 42 3
(HFO2)
SOI
TSi = 20 nm
S.H. Kim
et al. [20] 0.5 0.25-5µm 0.42 0.14 3x106 80 40 3
SOI
TSi = 70 nm
(poly- Ge source)
K. Jeon
et al.[21] 1 20µm 1.2 0.017 7x107 70 46 0.9
(HFO2)
SOI
Tsi = 40 nm
(source Ni-Silicate + pocket formation)
R. Gandhi
et al.[22] 1.2 GAA 0.02
0.2
105 1000 50 4.5 Silicon NW diameter = 40 nm
(GAA structure)
Hsu-Yu Chang et al.[30]
1.1 100nm 1.4 0.1 1.4×107 77 46 3.5
(Al2O3)
SOI
TSi = 50nm
(with dopant pocket)
Our Work
0.5
30nm
33 8.55 3.4×109 44 37 1.4
(HfO2/SiO2)
SGOI
TSiGe = 20nm
(with germanium as source)
7/30/2022 47
48. 7/30/2022 48
Chapter 6
Analytical Modeling of the Heterojunction SOI TFET with Oxide Overlap
Cross sectional view of the proposed device
For subthreshold region of operations, it is assumed that:
No mobile charges in the channel and no depletion region at
source/drain channel interfaces.
Doping profiles of source/drain channe
l junctions are abrupt.
Thick buried oxide is used , hence, the vertical electric field in
the channel/buried oxide interface is assumed to be negligible.
49. 7/30/2022 49
characteristics of the proposed d
- evice.
DS GS
I V characteristics of the proposed d
- evice.
DS DS
I V
Simulation Results
50. 7/30/2022 50
Surface Potential
The potential distribution in the channel is governed by 2D Poisson’s equation and is given by:
2 2
2 2
, ,
where, is the electrostat
0
ic potential.
x y x y
x y
To solve , potential is divided into two parts:
,
, , , ,
where, is the solution of 1D Poisson's equation,
, is th ol
e s
L R
x y
x y V y U x y V y U x y U x y
V y
U x y
ution of 2D Poisson's equation.
51. 7/30/2022 51
Surface Potential
The potential distribution in the channel is governed by 2D Poisson’s equation and is given by:
2 2
2 2
, ,
where, is the electrostat
0
ic potential.
x y x y
x y
, is divided into U and U
L R
U x y
, , ,
where, is the solution of 1D Poisson's equation, , is the
To solve , potential is divided i
solution of 2D Poisson's equation.
nto two parts:
x y x y V y U x y
V y U x y
To solve the field discontinuity at germanium/oxide and silicon/oxide interface the physical gate oxide
thickness is converted into: and for Si and Ge regions, respect
ge si
ox ox ox ox ox
ox ox
t t t t
t
ively.
where , , and are the relative permittivities of the oxide, silicon, and germanium, respectively, and
is the physical thickness of the gate oxide stack
ox si ge
ox
t
52. 7/30/2022 52
1D solution of Poisson's equation
is given by:
G
G
V y
V y y
W
Surface Potential
The necessary boundary conditions are:
,0 0
( , )
, 0 0
0, 0,
, ,
0,
,
y W
S
D DS
S G
S
D G
D
U x
dW x y
U x W
dx
U y y y V y
U L y L y y V V y
y y
t
L y y
t
where,
for the overlap region
for the channel region
the thickness of the silicon body
,
=
=
=gate voltag
flat band voltage
e
G F
si ox
si ox
si
G
G
F
S B
B
S
W
V
V
W t t
t t
t
V
V
Here, is for overlap region and is for channel
region, and are the built-in potentials at source/drain
channel junction, respectively, is drain-to-source voltage.
ox ox
S D
DS
t t t t
V
53. 7/30/2022 53
2 2
2 2
For 2D analysis, let us consider
( , ) ( , )
0
U x y U x y
x y
Using separation of variable method is used to solve , and is given as:
, ( ) ( )
U x y
U x y X x Y y
0
2D solution of the Poisson's equation using suitable boundary conditions is given by:
sinh sinh
, sin sin
sinh sinh
n n n n
n n
n n
n
A L x B x
U x y y y
L L
2
here
1 2
w
n n W
Surface Potential
54. 7/30/2022 54
Solving the constants and , the values are given as:
sin sin
2
cos
sin sin
2
cos
n n
ox
S GS GS
n S
ox
D GS GS
n D
A B
rt W
V V
A W
W t W
rt W
V V
B W
W t W
0
0
The constants and are given as:
2
0, sin
2
, sin
n n
W
n n
W
n n
A B
A U y y dy
W
B U L y y dy
W
Variation of the constants with number of terms n .
Parameters A and
n n
B
55. 7/30/2022 55
0 0
Using 1D and 2D solution , we can get the electrostatic potential
sinh sinh
( , ) sin sin
sinh sinh
n n n n
GS
GS n n
n n
n n
A L x B x
V
x y V y y y
W L L
surface
0 0
The surface potential is given as:
sinh sinh
sin sin 1
sinh sinh
n n ox
ox ox GS
n n
A L x B x rt
rt rt V
L L W
56. 7/30/2022 56
.
variation along the channel for different V .
s GS
variation along the channel for different L.
s
Model Verification
57. 7/30/2022 57
Electric Field and Band Gap
The horizontal and vertical electric-field distribution can be obtained by differentiating the potential function in,
and are given by:
0 0
0 0
sin sin
,
cosh cosh
sinh sinh
sinh sinh
,
cos cos
sinh sinh
n n
x n n n n n n
n n
n n
n n
G
y n n n n n n
n n
n n
y y
x y
E A L x B x
x L L
L x x
x y
E A y B y
y W L L
2 2
The absolute electric field is expressed as :
x y
E E E
The conduction bandand valance bandare defined as:
C
V g
E q
E E q
where, is the electrostatic potential, is the electron affinity and is the effective energy band g .
ap
g
E
58. 7/30/2022 58
.
Energy band diagram along the channel for different V .
GS
Electric Field variation along the channel.
Model Verification
59. 7/30/2022 59
Drain Current
,
DS
I q G x y dxdy
Based on the model expressions, of the device is calculated numerically using the integration of the on
BTBT Generation rate G of the dev e:
ic
DS
I
2
exp
B
G AE
E
1 2
2
1 2 2
3 2
2 1 2
: 9 (300 )
For direct tunneling pr
(300
o
)
cess r o g C
r g C
A g m qF h E K
B m E K qh
Kane nonlocal electric field is used for the calculation of BTBT direct generation rate G , and is given by:
1 , is the elementary charge, is the conduction band offset,
is the degeneracy factor, is Planck's c
where, is the elec
onstant and is reduced tunneling mass.
tric field, o C
r
F V cm q
g h m
E
18 1 1 2 7
18 1 1 2 7
For TCAD simulation A and B are
For analytical model A a
9.16 10 and 3.1 10 / .
8.1 10 and 2.95 10 / .
nd B are
cm s V V cm
cm s V V cm
60. 7/30/2022 60
Transfer characteristics of the SOI -TFET
device for different dielectric materials.
Simulated - characteristics for hetero
and homo junction of the proposed de e
vic .
DS GS
I V
Model Verification
61. 7/30/2022 61
Cross-sectional schematic of the proposed
n-type SOI-TFET.
Chapter 7
2D Gate Threshold Voltage Model of the Ge-source SOI TFET with Oxide/Source
Overlap
62. 62
Gate threshold voltage model
where is the gap energy and is the applied reverse bias at the source.
g S
E V
The depletion region length at the source-body
junction is given by
2
1 2
ge S
A A si ge si D
V y
l
qN N N
In TFET, the gate threshold volatge is the applied gate
voltage at which the energy barrier starts to saturate.
This effective inflection point in tunneling barrier width
at the tunneling junction is given by:
( )
g
bw
S S
E l
T
q V
64. Cont…
When the potential at reaches, the drain current becomes a linear
function of the gate voltage and the corresponding which is found by solving
the following equation:
bw DS D
gs t
x T V
V V
0
0
sinh
sin
sinh
sinh
sin 1
sinh
n bw
ox
n
DS D
n bw ox
ox GS
n
A L T
rt
L
V
B T rt
rt V
L W
Due to the hyperbolic terms the above equation cannot be solved for in closed f m
or .
gs
V
0
sin
2
cos sin
For a long-ch
sin sin
2
annel device , the threshold voltage can be a
1 sin
pproximated by:
tL
ox
DS D S ox
ox
n
tL
ox
ox
ox
L V
rt
V W rt
W rt
V
rt W
t
W W rt W
0
ox
n
rt
64
65. Cont…
1 2 3
Expanding the hyperbolic terms around using Taylor’s series
and retaining only the first two
sinh
s
terms, we
inh
get
gs tL
bw gs
V V
L T B B B V
1 2 3
bw gs
T A A A V
1
2
3 2
1 2
3
where, sinh ,
0.5 cosh ,
0.5 cosh ,
sinh , 0.5 cosh ,
0.5 cosh and
2 1
1
tL
tL tL FB tL
tL tL gs
tL tL tL FB tL
tL tL gs
g ge ox ox
S A
B L K V
B K V L K V V V
B B K V L K V V
A K V A K V K V V V
A K V K V V
E t W rt
K
qN W
65
66. Cont…
2
3 3 1
0
3 3 2
3 3 2 1 1
0
1 2 2
1 2
0
4
2
where,
2sin sinh
2sin
1
sinh
2sin
sinh
gs t
ox
n
D
ox
ox
FB
n
S D
ox
n
b b ac
V V
a
a t B A C W L
A B C
t
rt
b
W W L A B V K K C
K K C
t
c
W L K K V
1
1 1 2 2 1 2
1
; and .
ox
FB DS D
FB
rt
V V
W
C
K B B K A A
66
67. Cont…
The expressionfor is the approximation of Taylor series expansion which is
valid for The model calculation become accurate when the deviation of the
threshold voltage from its long channel counterpart
fulfills this condition. A
thicker high-K dielectric gives rise to larger effective oxide thickness EOT ,
which makes larger. For such cases, the actual threshold voltage for smaller
channel length may differ significantly fromand the model will fail to predict
accurate results.
67
68. 7/30/2022 68
variation along the channel for different V .
surface GS
of propos
vs. V ed device.
t DS
V
Model Verification
69. 7/30/2022 69
for different dielectric materials of
proposed Si-based homojunction devic
.
e
vs
.
t
V L for different dielectric materials of
proposed heterojunction device with Ge-source
vs
.
.
t
V L
Model Verification
75. 7/30/2022 75
Today TFETs represent the most promising steep-slope switch candidate, having the potential to use a supply voltage
significantly below 0.5 V and thereby offering significant power dissipation savings. Because of their low off currents,
they are ideally suited for low-power and low-standby-power logic applications operating at moderate frequencies.
The biggest challenge is to achieve high performance (high ION) without degrading IOFF, combined with an S of less
than 60 mV per decade over more than four decades of drain current. This requires the additive combination of the
many technology boosters which are available or under research.
Conclusion
76. 7/30/2022 76
Today TFETs represent the most promising steep-slope switch candidate, having the potential to use a supply voltage
significantly below 0.5 V and thereby offering significant power dissipation savings. Because of their low off currents,
they are ideally suited for low-power and low-standby-power logic applications operating at moderate frequencies.
The biggest challenge is to achieve high performance (high ION) without degrading IOFF, combined with an S of less
than 60 mV per decade over more than four decades of drain current. This requires the additive combination of the
many technology boosters which are available or under research.
Future Work
77. 30 July 2022 77
Journal:
1. Sweta Chander and S. Baishya, “Hetero-Junction SOI-Tunnel FET with Oxide/Source Overlap,” Elsevier Superlattices &
Microstructures, Revised, Version Under Review (SCI: impact factor 2.09).
2. Sweta Chander and S. Baishya, “Hetero-Junction SOI-Tunnel FET with Oxide/Source Overlap,” Elsevier Superlattices &
Microstructures, vol. 85, pp. 45-50, July 2015 (SCI: impact factor 2.09).
3. Sweta Chander and S. Baishya, “A Two-dimensional Gate Threshold Voltage Model for a Hetero- Junction SOI-Tunnel FET with
Oxide/Source Overlap”, IEEE Electron Device Letters, vol. 36, no. 7, pp. 714-716, May 2015 (SCI: impact factor 2.77).
Publications
Conference:
1. Accepted, Sweta Chander and S. Baishya, “Study of Heterostructure Silicon-on-Insulator Tunnel FET,” 12th IEEE India International
conference (INDICON 2015), Jamia Milia Islamia, New Delhi, India, December 17-20, 2015,.
2. Accepted, Sweta Chander and S. Baishya, “Nanoscale Characterization of Heterostructure SOI Tunnel FET,” 4th International
Conference on Advanced Nanomaterials and Nanotechnology (ICANN 2015), IIT Guwahati, India, December 8-11, 2015.
3. Accepted, Sweta Chander and S. Baishya, “Improved Miller Capacitance of New Heterostructure Silicon-on-Insulator Tunnel FET,”
IEEE International Conference TENCON 2015, Macau, China, November 1-4, 2015.
4. Sweta Chander and S. Baishya, “Feasibility Study of a Novel Asymmetric SGOI-TFET Using Non-Local BTBT Model,”Annual 11th IEEE
India International Conference (INDICON 2014), Pune, Maharastra, pp. 1-6, December 11-13, 2014.
5. Sweta Chander and S. Baishya, “A novel nanoscale FD SOI-TFET Architecture with Improved performanc,”3rd International Conference
nanotechnology- Innovative materials, Processes, Products and Applications (NANOCON 014), Bharti Vidyapeeth, Pune , Maharastra,
India, October 14-15 ,2014.
78. 30 July 2022 78
5. Sweta Chander and S. Baishya, “Performance Analysis of Nanowire FET and tunnel FET with Different Channel Material in Nano
Regime,” 3rd International Conference nanotechnology- Innovative materials, Processes, Products and Applications (NANOCON 014),
Bharti Vidyapeeth, Pune , Maharastra, India, 14-15 October 2014.
6. Sweta Chander and S. Baishya,” A Comprehensive Analysis of SOI-TFET with Novel AlxGa1-xAs Channel Material,” IEEE 2nd
International Conference on Devices, Circuits and Systems, Karunya University, Tamilnadu, India, pp. 1-5, March 6-8, 2014.
7. Sweta Chander, Om Prakash Mahto, Vivek Chander and S. Baishya,” Analysis of Novel SGOI-TFET with Record Low Subthreshold
Swing (SS) and High Ion/Ioff Ratio,” 8th IEEE International Conference on Computing for Sustainable Global Development (INDIAcom
2014), Bharati Vidyapeeth, New Delhi, India, pp. 500-504, March 5-7, 2014.
8. Sweta Chander, Vivek Chander and S. Baishya,” Improved Miller Effect using Al0.2Ga0.8As as a novel channel material in SOI based
TFET,” IEEE International Conference on VLSI and Signal Processing, IIT Kharagpur, West Bengal, India, January 10-12, 2014.
9. Sweta Chander and S. Baishya, “Advantage of SOI-TFET with Channel Material of Al0.2Ga0.8As,” 10th National Conference on Solid
State Ionics (NCSSI 10), IIT Kharagpur, West Bengal, India, December 22-23, 2013.
10. Sweta Chander and S. Baishya, “Impact of Channel Length & Oxide Thickness Variation in an Asymmetric SGOI-TFET,” IEEE Asia-
Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia 2013), GITAM University, Visakhapatnam,
India, pp. 103-106, December 19-21, 2013.
11. Sweta Chander and S. Baishya, “SOI-TFET with Different Mole Fraction of Germanium,” International Conference on Advanced
Nanomaterials and Nanotechnology (ICANN 2013), IIT Guwahati, India, December 1-3, 2013.
Publications
80. 7/30/2022 80
1. K. Moselund, H. Ghoneim, M. T. Björk, H. Schmid, S. Karg, E. Lörtscher, W. Riess, and H. Riel, “Comparison of VLS grown Si NW tunnel FETs with different gate stacks,” in Proc.
ESSDERC, pp. 448-451,2009
2. S. Mookerjea, R. Krishnan, S. Datta, and V. Narayanan, ”Effective Capacitance and Drive Current for Tunnel FET (TFET) CV/I Estimation”, IEEE Trans. Electron Devices, vol. 56, no. 9,
pp. 2092-98, Sept. 2009.
3. K. Jeon, W.-Y. Loh, P. Patel, C. Y. Kang. J. Oh, A.Bowonder, C. Park, C. S. Park, C. Smith, P. Majhi, H.-H. Tseng, R. Jammy, T.-J. King Liu, and C. Hu, "Si tunnel transistors with a novel
silicided source and 46mV/dec swing," Symposium on VLSITechnology Digest, pp. 121-122, June 2010.
4. Dheeraj Mohata, Saurabh Mookerjea, Ashish Agrawal, Yuanyuan Li, Theresa Mayer, Vijaykrishnan Narayanan ,Amy Liu2, Dmitri Loubychev, Joel Fastenau, and Suman Datta,
“Experimental Staggered-Source and N+ Pocket-Doped Channel III–V Tunnel Field-Effect Transistors and Their Scalabilities” Applied Physics Express 4 ,024105, 2011.
5. Ram Asra, Mayank Shrivastava, Kota V. R. M. Murali, Rajan K. Pandey, Harald Gossner, and V. Ramgopal Rao, “A Tunnel FET for VDD Scaling Below 0.6 V With a CMOS-Comparable
Performance”, IEEE Transactions On Electron Devices, Vol. 58, No. 7, July 2011.
6. Kuo-Hsing Kao, Anne S. Verhulst, William G. Vandenberghe, Bart Sorée, Wim Magnus, Daniele Leonelli, Guido Groeseneken,, and Kristin De Meyer, “Optimization of Gate-on-
Source-Only Tunnel FETs With Counter-Doped Pockets” IEEE Transactions On Electron Devices, Vol. 59, No. 8, August 2012.
7. Min Hung Lee, Jhe-Cyun Lin, and Cheng-Ying Kao “Hetero-Tunnel Field-Effect-Transistors With Epitaxially Grown Germanium on Silicon” IEEE Transactions On Electron Devices, Vol.
60, No. 7, July 2013.
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