The document discusses input/output organization. It covers peripheral devices, input-output interfaces, asynchronous data transfer, modes of transfer including programmed I/O, interrupt-initiated I/O, and direct memory access (DMA), priority interrupts, and input-output processors. Specifically, it describes how priority interrupts work using both software polling and hardware daisy chaining approaches, and how parallel priority interrupts use an interrupt register, mask register, and priority encoder to determine the highest priority interrupt request.
An I/O interface consists of circuitry that connects input/output devices to a computer system. It has a data path that transfers data between the interface and device. This side is called a port and can be either serial or parallel. A parallel port transfers data simultaneously using multiple pins, while a serial port transmits data one bit at a time, making it convenient for long distances. Both parallel and serial ports contain buffers to store data and status flags accessed by the processor to determine if the buffer is full or empty. The interface also performs any necessary format conversions like parallel to serial for a serial port.
This document discusses input/output organization in computer systems. It describes peripheral devices for input and output, input/output interfaces that allow communication between peripherals and the CPU/memory, and various methods for transferring data asynchronously between independent devices or systems, including strobe control, handshaking, and serial transmission. Asynchronous data transfer is necessary because peripherals often operate at different speeds than the CPU and memory.
The document discusses input/output (I/O) interfaces. An I/O interface is required for communication between the CPU, I/O devices, and memory. It performs data buffering, control and timing, and error detection. There are two main techniques for I/O interfacing - memory mapped I/O and I/O mapped I/O. Programmed I/O is an approach where the CPU polls I/O devices by checking their status periodically to see when operations complete.
The document discusses input-output organization between a CPU and peripherals. It notes that signal conversion and synchronization may be required due to differences in data rates and formats. Special interface hardware is used to supervise and synchronize input and output transfers. The document also discusses asynchronous and synchronous data transfer methods and the use of I/O buses versus memory buses for communication with peripherals.
The document discusses various aspects of input and output devices and their interface with the central processing unit of a computer system. It describes how peripherals like keyboards, displays and printers are connected and controlled. It explains the different modes of data transfer between CPU and peripherals, including programmed I/O, interrupt-initiated I/O, and direct memory access. The document also covers topics like asynchronous and synchronous data transmission, handshaking, and hardware priority interrupts.
The document discusses different methods for accessing I/O devices in computer systems. It describes how I/O devices connect to the processor through ports and can be accessed using IN and OUT instructions. There are three main strategies for I/O - polled I/O, interrupt-driven I/O, and direct memory access (DMA). Polled I/O involves the processor continuously checking devices for readiness, interrupt-driven I/O uses interrupts to signal readiness, and DMA allows direct transfer between device and memory without involving the CPU. The strategies differ in transfer rates, latency, and CPU overhead.
The document discusses input/output organization in computer systems. It describes peripheral devices like monitors, keyboards, printers, and storage devices that are connected to computers. It then explains the need for input/output interfaces to handle differences in signal values, timing, data formats, and operating modes between the CPU and peripherals. Common interface types include serial and parallel interfaces. The document outlines techniques for synchronous and asynchronous data transfer, including the use of handshaking protocols to ensure reliable communication between devices. It provides examples of specific interface chips like the 8251 serial interface adapter.
The interface circuitry allows for communication between the microcomputer and I/O devices by converting between their different signaling formats and synchronization rates. It contains data and address registers to transfer information via common buses between the CPU and peripheral devices like keyboards, printers, disks and tapes. The interface helps overcome differences in data codes, operating modes and transfer rates between the CPU and peripherals.
An I/O interface consists of circuitry that connects input/output devices to a computer system. It has a data path that transfers data between the interface and device. This side is called a port and can be either serial or parallel. A parallel port transfers data simultaneously using multiple pins, while a serial port transmits data one bit at a time, making it convenient for long distances. Both parallel and serial ports contain buffers to store data and status flags accessed by the processor to determine if the buffer is full or empty. The interface also performs any necessary format conversions like parallel to serial for a serial port.
This document discusses input/output organization in computer systems. It describes peripheral devices for input and output, input/output interfaces that allow communication between peripherals and the CPU/memory, and various methods for transferring data asynchronously between independent devices or systems, including strobe control, handshaking, and serial transmission. Asynchronous data transfer is necessary because peripherals often operate at different speeds than the CPU and memory.
The document discusses input/output (I/O) interfaces. An I/O interface is required for communication between the CPU, I/O devices, and memory. It performs data buffering, control and timing, and error detection. There are two main techniques for I/O interfacing - memory mapped I/O and I/O mapped I/O. Programmed I/O is an approach where the CPU polls I/O devices by checking their status periodically to see when operations complete.
The document discusses input-output organization between a CPU and peripherals. It notes that signal conversion and synchronization may be required due to differences in data rates and formats. Special interface hardware is used to supervise and synchronize input and output transfers. The document also discusses asynchronous and synchronous data transfer methods and the use of I/O buses versus memory buses for communication with peripherals.
The document discusses various aspects of input and output devices and their interface with the central processing unit of a computer system. It describes how peripherals like keyboards, displays and printers are connected and controlled. It explains the different modes of data transfer between CPU and peripherals, including programmed I/O, interrupt-initiated I/O, and direct memory access. The document also covers topics like asynchronous and synchronous data transmission, handshaking, and hardware priority interrupts.
The document discusses different methods for accessing I/O devices in computer systems. It describes how I/O devices connect to the processor through ports and can be accessed using IN and OUT instructions. There are three main strategies for I/O - polled I/O, interrupt-driven I/O, and direct memory access (DMA). Polled I/O involves the processor continuously checking devices for readiness, interrupt-driven I/O uses interrupts to signal readiness, and DMA allows direct transfer between device and memory without involving the CPU. The strategies differ in transfer rates, latency, and CPU overhead.
The document discusses input/output organization in computer systems. It describes peripheral devices like monitors, keyboards, printers, and storage devices that are connected to computers. It then explains the need for input/output interfaces to handle differences in signal values, timing, data formats, and operating modes between the CPU and peripherals. Common interface types include serial and parallel interfaces. The document outlines techniques for synchronous and asynchronous data transfer, including the use of handshaking protocols to ensure reliable communication between devices. It provides examples of specific interface chips like the 8251 serial interface adapter.
The interface circuitry allows for communication between the microcomputer and I/O devices by converting between their different signaling formats and synchronization rates. It contains data and address registers to transfer information via common buses between the CPU and peripheral devices like keyboards, printers, disks and tapes. The interface helps overcome differences in data codes, operating modes and transfer rates between the CPU and peripherals.
The document discusses various topics related to input/output organization in a computer system. It describes peripheral devices that interface with the computer and transfer data asynchronously. It discusses different methods of asynchronous data transfer including strobe pulse and handshaking. It also covers topics like interrupt priority, direct memory access (DMA), input/output processors, and serial communication.
The document discusses input-output organization in computer systems. It describes peripheral devices, input-output interfaces, asynchronous data transfer methods like handshaking, direct memory access, interrupt-driven I/O, and the universal asynchronous receiver-transmitter chip. The input-output system allows communication between the computer and external devices by resolving differences in data rates and operating protocols.
This document provides an overview of input/output interfaces in 3 paragraphs. It discusses how I/O devices communicate differently than internal storage due to differences in operation, data transfer rates, word formats, and peripheral operating modes. It describes how interface modules connect I/O devices like keyboards, displays, printers and storage to the I/O bus and processor. Finally, it provides an example of an I/O interface unit that uses control and status registers to facilitate communication between a CPU and I/O device over control, data and status lines.
The document discusses input/output (I/O) organization and buses. It describes how I/O devices connect to the processor and memory via a shared bus. It discusses different I/O access methods like memory-mapped I/O and special I/O instructions. It also covers I/O interfaces, interrupts, direct memory access (DMA), and bus arbitration methods.
The document discusses input-output organization and describes various input and output peripheral devices. It then covers input-output interfaces, how data is transferred asynchronously between devices and the CPU using handshaking, and different modes of data transfer including program-controlled, interrupt-initiated, and direct memory access. It also discusses how interrupts from multiple devices are handled using priority levels and interrupt vectors.
This lecture discusses different input/output device models including shared I/O, memory mapped I/O, and programmed I/O. Shared I/O separates memory and I/O addresses but requires special I/O instructions, while memory mapped I/O maps I/O devices into memory address space eliminating special instructions but reserving addresses. Programmed I/O uses hardware and software protocols to communicate through shared I/O with up to 8 devices. The lecture also covers I/O registers, status registers, address decoding, and interrupt-driven communication between processors and I/O devices.
The document discusses various input/output (I/O) organization topics including I/O interfaces, buses, programmed I/O, interrupts, direct memory access, and memory-mapped I/O. It provides details on synchronous and asynchronous buses, interrupt request hardware, enabling and disabling interrupts, and techniques for handling interrupts from multiple devices such as polling, vectored interrupts, and daisy chaining.
The document discusses input/output organization and accessing I/O devices. There are three key components to a computer system: the processor, memory, and I/O modules. I/O modules interface between peripheral devices and the system bus, controlling the transfer of data. I/O modules perform functions like control and timing, processor/device communication, data buffering, and error detection to facilitate input and output.
The document discusses various data transfer techniques used in microprocessors, including synchronous, asynchronous, interrupt-driven I/O, DMA, and programmed I/O. It explains that synchronous transfer uses compatible speeds, asynchronous uses handshaking, interrupt-driven reduces processor waiting, DMA allows direct memory access to bypass the CPU, and programmed I/O uses the CPU to directly control I/O operations. It also covers serial vs parallel transmission and differences between them.
This document discusses input/output (I/O) organization in computer systems. It covers various I/O techniques including programmed I/O, interrupts, direct memory access (DMA), and I/O interfaces. Memory-mapped I/O allows I/O devices to use the same address space as memory. Interrupts allow I/O devices to signal the processor when they need service. DMA controllers can transfer data directly between I/O devices and memory without processor intervention. Buses and interface circuits are used to connect I/O devices to the processor and main memory.
I/O subsystems: Input/output devices such as Disk, CD,ROM, Printer etc.; Interfacing with IO devices, keyboard and display interfaces; Basic concepts Bus Control, Read Write operations, Programmed IO, Concept of handshaking, Polled and Interrupt driven I/O, DMA data transfer
The document discusses application I/O interfaces and their characteristics. Application I/O interfaces provide standard ways for operating systems to treat I/O devices uniformly by hiding differences through device drivers. I/O interfaces have characteristics like their data transfer mode (character or block), access method (sequential or random), transfer schedule (synchronous or asynchronous), ability to be shared, speed, and supported input/output directions.
Input/output modules are critical components that allow computers to interact with external devices. I/O modules serve as an interface between peripherals and the CPU/memory. They perform important functions like control and timing of data transfers, communication with the processor and devices, buffering data, and error detection. I/O modules connect to the system bus and contain data buffers, status registers, and logic to interact with the processor via control lines. This allows external devices like disks and tapes to connect indirectly to the computer and be managed through simple read/write commands.
The document discusses input/output organization in computers. It explains that all input/output devices connect to the computer via a bus that allows exchange of address, data and control signals. Each device is assigned a unique address. When the processor requests a read or write, the requested data is placed on the data lines and the address is sent to the address lines. Commonly used I/O mechanisms include interrupts and direct memory access. Memory mapped I/O allows I/O devices and memory to share the same address space.
The document discusses various methods for input/output (IO) in computer systems, including IO interfaces, programmed IO, interrupt-initiated IO, direct memory access (DMA), and input-output processors (IOPs). It describes how each method facilitates the transfer of data between the CPU, memory, and external IO devices.
This document provides information on input/output organization and interfaces in a computer system. It discusses different I/O techniques like interrupts and direct memory access. Interrupts allow I/O devices to signal the processor when they need attention. Direct memory access enables high-speed transfer of data directly between I/O devices and memory without processor involvement. The document also describes common I/O bus standards like PCI, SCSI and USB and how they facilitate communication between devices and the computer.
The document discusses various aspects of I/O organization in a computer system. It describes the input-output interface that provides a method for transferring information between internal storage and external I/O devices. It discusses asynchronous data transfer techniques like strobe control and handshaking. It also covers asynchronous serial transmission, different modes of data transfer like programmed I/O, interrupt-initiated I/O, and direct memory access (DMA).
This document discusses input/output organization and peripheral devices. It covers the following key points in 3 sentences:
Peripheral devices allow input and output between the computer and external environment. The document outlines different types of input devices, output devices, and input/output devices. It also discusses the input/output interface which provides communication between the CPU, memory, and peripheral devices by resolving differences in data formats, transfer rates, and operating modes.
The document discusses various topics related to input/output organization in a computer system. It describes peripheral devices that interface with the computer and transfer data asynchronously. It discusses different methods of asynchronous data transfer including strobe pulse and handshaking. It also covers topics like UART, FIFO buffers, and different modes of data transfer between CPU and peripheral devices including program-controlled, interrupt-initiated, and direct memory access.
The document discusses various topics related to input/output organization in a computer system. It describes peripheral devices that interface with the computer and transfer data asynchronously. It discusses the input/output interface that provides communication between the CPU and I/O devices. It also describes asynchronous data transfer methods like strobe pulse and handshaking that allow synchronization between independent units transferring data asynchronously.
The document discusses various topics related to input/output organization in a computer system. It describes peripheral devices that interface with the computer and transfer data asynchronously. It discusses different methods of asynchronous data transfer including strobe pulse and handshaking. It also covers topics like interrupt priority, direct memory access (DMA), input/output processors, and serial communication.
The document discusses input-output organization in computer systems. It describes peripheral devices, input-output interfaces, asynchronous data transfer methods like handshaking, direct memory access, interrupt-driven I/O, and the universal asynchronous receiver-transmitter chip. The input-output system allows communication between the computer and external devices by resolving differences in data rates and operating protocols.
This document provides an overview of input/output interfaces in 3 paragraphs. It discusses how I/O devices communicate differently than internal storage due to differences in operation, data transfer rates, word formats, and peripheral operating modes. It describes how interface modules connect I/O devices like keyboards, displays, printers and storage to the I/O bus and processor. Finally, it provides an example of an I/O interface unit that uses control and status registers to facilitate communication between a CPU and I/O device over control, data and status lines.
The document discusses input/output (I/O) organization and buses. It describes how I/O devices connect to the processor and memory via a shared bus. It discusses different I/O access methods like memory-mapped I/O and special I/O instructions. It also covers I/O interfaces, interrupts, direct memory access (DMA), and bus arbitration methods.
The document discusses input-output organization and describes various input and output peripheral devices. It then covers input-output interfaces, how data is transferred asynchronously between devices and the CPU using handshaking, and different modes of data transfer including program-controlled, interrupt-initiated, and direct memory access. It also discusses how interrupts from multiple devices are handled using priority levels and interrupt vectors.
This lecture discusses different input/output device models including shared I/O, memory mapped I/O, and programmed I/O. Shared I/O separates memory and I/O addresses but requires special I/O instructions, while memory mapped I/O maps I/O devices into memory address space eliminating special instructions but reserving addresses. Programmed I/O uses hardware and software protocols to communicate through shared I/O with up to 8 devices. The lecture also covers I/O registers, status registers, address decoding, and interrupt-driven communication between processors and I/O devices.
The document discusses various input/output (I/O) organization topics including I/O interfaces, buses, programmed I/O, interrupts, direct memory access, and memory-mapped I/O. It provides details on synchronous and asynchronous buses, interrupt request hardware, enabling and disabling interrupts, and techniques for handling interrupts from multiple devices such as polling, vectored interrupts, and daisy chaining.
The document discusses input/output organization and accessing I/O devices. There are three key components to a computer system: the processor, memory, and I/O modules. I/O modules interface between peripheral devices and the system bus, controlling the transfer of data. I/O modules perform functions like control and timing, processor/device communication, data buffering, and error detection to facilitate input and output.
The document discusses various data transfer techniques used in microprocessors, including synchronous, asynchronous, interrupt-driven I/O, DMA, and programmed I/O. It explains that synchronous transfer uses compatible speeds, asynchronous uses handshaking, interrupt-driven reduces processor waiting, DMA allows direct memory access to bypass the CPU, and programmed I/O uses the CPU to directly control I/O operations. It also covers serial vs parallel transmission and differences between them.
This document discusses input/output (I/O) organization in computer systems. It covers various I/O techniques including programmed I/O, interrupts, direct memory access (DMA), and I/O interfaces. Memory-mapped I/O allows I/O devices to use the same address space as memory. Interrupts allow I/O devices to signal the processor when they need service. DMA controllers can transfer data directly between I/O devices and memory without processor intervention. Buses and interface circuits are used to connect I/O devices to the processor and main memory.
I/O subsystems: Input/output devices such as Disk, CD,ROM, Printer etc.; Interfacing with IO devices, keyboard and display interfaces; Basic concepts Bus Control, Read Write operations, Programmed IO, Concept of handshaking, Polled and Interrupt driven I/O, DMA data transfer
The document discusses application I/O interfaces and their characteristics. Application I/O interfaces provide standard ways for operating systems to treat I/O devices uniformly by hiding differences through device drivers. I/O interfaces have characteristics like their data transfer mode (character or block), access method (sequential or random), transfer schedule (synchronous or asynchronous), ability to be shared, speed, and supported input/output directions.
Input/output modules are critical components that allow computers to interact with external devices. I/O modules serve as an interface between peripherals and the CPU/memory. They perform important functions like control and timing of data transfers, communication with the processor and devices, buffering data, and error detection. I/O modules connect to the system bus and contain data buffers, status registers, and logic to interact with the processor via control lines. This allows external devices like disks and tapes to connect indirectly to the computer and be managed through simple read/write commands.
The document discusses input/output organization in computers. It explains that all input/output devices connect to the computer via a bus that allows exchange of address, data and control signals. Each device is assigned a unique address. When the processor requests a read or write, the requested data is placed on the data lines and the address is sent to the address lines. Commonly used I/O mechanisms include interrupts and direct memory access. Memory mapped I/O allows I/O devices and memory to share the same address space.
The document discusses various methods for input/output (IO) in computer systems, including IO interfaces, programmed IO, interrupt-initiated IO, direct memory access (DMA), and input-output processors (IOPs). It describes how each method facilitates the transfer of data between the CPU, memory, and external IO devices.
This document provides information on input/output organization and interfaces in a computer system. It discusses different I/O techniques like interrupts and direct memory access. Interrupts allow I/O devices to signal the processor when they need attention. Direct memory access enables high-speed transfer of data directly between I/O devices and memory without processor involvement. The document also describes common I/O bus standards like PCI, SCSI and USB and how they facilitate communication between devices and the computer.
The document discusses various aspects of I/O organization in a computer system. It describes the input-output interface that provides a method for transferring information between internal storage and external I/O devices. It discusses asynchronous data transfer techniques like strobe control and handshaking. It also covers asynchronous serial transmission, different modes of data transfer like programmed I/O, interrupt-initiated I/O, and direct memory access (DMA).
This document discusses input/output organization and peripheral devices. It covers the following key points in 3 sentences:
Peripheral devices allow input and output between the computer and external environment. The document outlines different types of input devices, output devices, and input/output devices. It also discusses the input/output interface which provides communication between the CPU, memory, and peripheral devices by resolving differences in data formats, transfer rates, and operating modes.
The document discusses various topics related to input/output organization in a computer system. It describes peripheral devices that interface with the computer and transfer data asynchronously. It discusses different methods of asynchronous data transfer including strobe pulse and handshaking. It also covers topics like UART, FIFO buffers, and different modes of data transfer between CPU and peripheral devices including program-controlled, interrupt-initiated, and direct memory access.
The document discusses various topics related to input/output organization in a computer system. It describes peripheral devices that interface with the computer and transfer data asynchronously. It discusses the input/output interface that provides communication between the CPU and I/O devices. It also describes asynchronous data transfer methods like strobe pulse and handshaking that allow synchronization between independent units transferring data asynchronously.
The document discusses various aspects of input-output organization in computer systems. It describes peripheral devices, input-output interfaces, asynchronous data transfer methods using handshaking, direct memory access, interrupt handling, and input-output processors. The key aspects covered are the interface between the computer and external devices, synchronization for asynchronous data transfer, and different modes of transferring data between memory and I/O devices.
This document discusses input/output organization in computer systems. It describes:
1) Peripheral devices for input and output and how they connect to the computer via interface modules on an I/O bus.
2) Asynchronous data transfer methods like handshaking that allow communication between devices running at different speeds.
3) Memory-mapped I/O that uses memory addresses for I/O, improving flexibility over isolated I/O that has separate address spaces.
4) Asynchronous serial transfer of data one bit at a time using start and stop bits to delineate characters transferred.
The input-output subsystem allows communication between the central computer system and external devices. Peripherals like keyboards, printers, and storage devices are connected via interface units that resolve differences in data formats and transfer rates. There are two main methods for organizing input-output - isolated I/O uses separate instructions to access interface registers, while memory-mapped I/O accesses peripherals through memory addresses on a shared bus. Asynchronous transfer between asynchronous units like the CPU and I/O interfaces requires control signals to synchronize the transmission of data.
A peripheral device provides input/output functions for a computer as an auxiliary device without core computing functionality. Peripheral devices are classified into input devices, output devices, and storage devices. An input/output interface helps transfer information between internal storage and external peripheral devices. It resolves differences in data formats and speeds between the CPU and peripheral devices. The interface provides control signals and buffers data to synchronize operations. Computers can use separate I/O and memory buses or a common bus with separate control lines or common control lines to communicate with peripherals and memory.
The document discusses input-output organization and direct memory access. It describes how I/O devices are connected to computers through interfaces that handle synchronization and conversion between the CPU and peripherals. It also explains different I/O transfer modes like programmed I/O, interrupt-driven I/O, and direct memory access (DMA). DMA allows high-speed transfer of data directly between memory and an I/O device without CPU involvement by using bus request/grant signals to gain control of the buses.
This document provides an overview of input/output organization and various input/output techniques including peripheral devices, input-output interfaces, asynchronous data transfer, modes of transfer such as programmed I/O, interrupt-initiated I/O, and direct memory access. It also discusses universal asynchronous receiver transmitter chips, first-in first-out buffers, and compares different modes of transfer including their advantages and disadvantages.
Computer organisation and architecture module 1abinrj123
The document discusses computer instructions and their formats. It explains that there are three main instruction formats: memory reference, register reference, and input/output. Memory reference instructions use bits to specify an address and addressing mode. Register reference instructions specify an operation on the AC register without an operand. Input/output instructions specify an I/O operation without a memory reference. The instruction set is complete if it includes arithmetic, data movement, program control, and I/O instructions.
The document discusses input/output (I/O) organization in computers. It covers various topics related to I/O including I/O interfaces, asynchronous and synchronous data transfer, and different modes of data transfer like programmed I/O and direct memory access. It describes how I/O devices connect to the computer and how interface modules resolve differences in data formats and transfer rates between I/O devices and the CPU. It also discusses I/O buses and different methods of communication between CPU, memory, and I/O including separate I/O and memory buses, isolated I/O using separate control lines, and memory mapped I/O.
This document discusses memory and I/O interfacing in microprocessors. It describes the parallel communication interface 8255 which allows a microprocessor to interface with peripheral devices. The 8255 has three 8-bit ports that can be programmed to work in different modes like basic I/O, strobed I/O, and bidirectional modes. It reduces external logic needed for interfacing and can be programmed to perform specific functions through control words. The document also briefly mentions other programmable peripheral devices like serial interface 8251, timer 8254, and interrupt controller 8259.
This document provides information about input-output interfaces in computer systems. It discusses how interface units connect peripheral devices to the CPU and resolve differences in data formats and transfer rates. Interface units include address decoders, registers for control, status, and transferring data. The document contrasts isolated I/O, where separate input/output instructions are used, versus memory-mapped I/O, where I/O devices use memory addresses. It provides an example of an interface unit with control, status and data registers that communicate with the CPU over a shared bus.
This document provides an overview of input/output organization. It discusses peripheral devices, input and output interfaces, asynchronous data transfer, modes of transfer, interrupts, direct memory access, I/O processors, and serial communication. It describes common input devices like keyboards and optical scanners and output devices like printers and displays. It also covers I/O interfaces, buses, isolated versus memory mapped I/O, and programmable I/O interfaces.
An I/O interface consists of circuitry that connects input/output devices to a computer system. It has a data path that transfers data between the interface and device bidirectionally. The interface contains a buffer, status flags, and address decoding circuitry. It also performs any necessary format conversions such as parallel to serial for serial ports, which transmit data one bit at a time for long distance communication, while parallel ports transfer data simultaneously using multiple pins and having a simpler circuit.
The document describes a UART verification IP core. It consists of a transmitter, receiver, modem interface, baud generator, interrupt controller and control/status registers. The core performs serial-to-parallel and parallel-to-serial conversions. It can operate in 8-bit or 32-bit data bus mode and interfaces with a wishbone bus. The document outlines the UART packet structure, registers, modes of operation, block diagram, UVM verification architecture including transactions, agents, drivers, monitors, sequences, tests and scoreboard. It concludes by summarizing that the UART core was verified for different modes and test cases.
This slide deals with the Input-Output Channel of an IBM 370 computer. It includes three Block diagrams of the I-O channels as well as the Memory Unit with the Description of each and every diagrams.
This document discusses different techniques for data transfer between the CPU and I/O devices, including programmed I/O, interrupt-driven I/O, and direct memory access (DMA). It describes the basic functioning of an I/O module, comparing programmed I/O to interrupt-driven I/O. It then provides details on DMA, including how it allows high-speed transfer of data directly between memory and I/O devices without CPU involvement. The document also covers I/O interfaces, asynchronous data transfer methods like handshaking, and serial transmission techniques.
This document discusses parallel processing and pipelining. It describes different levels and types of parallel processing including job level, task level, inter-instruction level, and intra-instruction level parallelism. It also covers Flynn's classification of parallel computers as SISD, SIMD, MISD, and MIMD based on the number of instruction and data streams. Pipelining is defined as decomposing a process into sub-operations that execute concurrently. The key benefits of pipelining are that multiple computations can progress simultaneously through different pipeline stages.
The document describes the control unit of a processor and how it is implemented using either hardwired control or microprogrammed control. It provides terminology related to microprogrammed control including microinstruction, control word, sequencing word, control memory, sequencer, and microinstruction format. It explains how the address sequencer works in a microprogrammed control unit to sequence through microinstructions stored in control memory.
This document describes instruction codes and the instruction cycle in a computer. It discusses how instruction codes specify operations for the computer to perform. The instruction cycle has four phases: 1) fetch an instruction from memory, 2) decode the instruction, 3) read the effective address if indirect addressing is used, and 4) execute the instruction. It then describes the fetch and decode phases in more detail, including transferring the program counter value to the address register to fetch the instruction from memory location and loading the instruction register.
This document describes a lecture on basic computer organization and design. It discusses:
- The basic components of a computer including a processor, memory, registers, and bus.
- The instruction format and addressing modes of instructions in the basic computer.
- The registers in the basic computer including the program counter, address register, and accumulator.
- How the common bus is used to transfer data between registers and memory.
- The basic computer's instruction set including memory and register reference instructions.
- How the control unit decodes instructions and generates control signals to implement operations.
The document discusses register transfer language (RTL) and microoperations in computer organization. It covers topics like register transfer, bus and memory transfers, arithmetic operations, logic operations, and shift operations. Register transfer involves transferring data between computer registers using microoperations. Common bus systems and three-state buffers are used to transfer data between multiple registers. Memory transfers read from and write to memory locations specified by an address register. Arithmetic operations include addition, subtraction, incrementing and decrementing using half adders, full adders and binary adders. Logic operations include AND, OR and NOT gates.
The document describes the instruction set and control unit design of a basic computer. It includes:
- Memory reference instructions like AND, ADD, LDA, STA, BUN, BSA, ISZ for arithmetic, data transfer, and control flow.
- Register reference instructions like CLA, CLE, CMA for operations using the accumulator and extended accumulator.
- Input/output instructions like INP, OUT for device I/O.
The control unit implements an instruction cycle of fetch, decode, execute through a hardwired design using a program counter, instruction register, decoders and timing signals from a sequence counter. The instruction format and timing of each instruction type is also explained.
The document provides an overview of a course on basic computer organization and design. It describes the components of a basic computer including the processor, memory, registers, bus, and instruction set. The processor contains registers like the program counter, address register, data register, accumulator, and input/output registers. The memory can hold 4096 16-bit words. The instruction set includes memory reference, register reference, and input/output instructions that allow basic arithmetic, logic, branching, and I/O operations.
The document discusses the central processing unit (CPU) and its components. It covers topics like register organization, instruction formats, addressing modes, data transfer instructions, and data manipulation instructions. The key components of a CPU include storage components like registers and flags, execution components like the arithmetic logic unit (ALU), and control components like the control unit. Common addressing modes include direct, indirect, register, and immediate addressing. Data transfer instructions move data between memory and registers, while data manipulation instructions perform arithmetic, logical, and shift operations.
This document discusses parallel processing and multiprocessors. It covers various topics related to coupling of processors, interconnection structures, bus structures, memory structures, arbitration methods, and synchronization techniques for parallel systems. Tightly coupled systems use shared memory while loosely coupled systems use message passing. Common interconnection structures include buses, crossbar switches, and hypercube networks. Both static and dynamic arbitration methods are described for shared bus access. Hardware semaphores can provide mutual exclusion for critical sections in shared memory parallel systems.
This document provides an overview of computer arithmetic, including addition, subtraction, multiplication, and division algorithms. It discusses:
- The four basic arithmetic operations of addition, subtraction, multiplication, and division.
- Different representations of fixed and floating point binary data, including signed magnitude, 1's complement, and 2's complement.
- Algorithms for addition, subtraction, and multiplication of signed magnitude and 2's complement data. Subtraction is performed by adding the minuend to the 2's complement of the subtrahend.
- Hardware implementations of addition, subtraction, and multiplication, including the use of an adder, complementor, and registers. Division hardware mirrors multiplication hardware, shifting the dividend left
This document discusses register transfer language and micro-operations. It describes how digital systems can be characterized by the registers they contain and operations performed on the data. Micro-operations like shift and load are executed on register data. Register transfer language uses symbols to describe the transfer of data between registers. It allows the internal organization of computers to be described concisely and facilitates digital system design.
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Time Division Multiplexing (TDM) is a method of transmitting multiple signals over a single communication channel by dividing the signal into many segments, each having a very short duration of time. These time slots are then allocated to different data streams, allowing multiple signals to share the same transmission medium efficiently. TDM is widely used in telecommunications and data communication systems.
### How TDM Works
1. **Time Slots Allocation**: The core principle of TDM is to assign distinct time slots to each signal. During each time slot, the respective signal is transmitted, and then the process repeats cyclically. For example, if there are four signals to be transmitted, the TDM cycle will divide time into four slots, each assigned to one signal.
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3. **Frame Structure**: TDM data is organized into frames, where each frame consists of a set of time slots. Each frame is repeated at regular intervals, ensuring continuous transmission of data streams. The frame structure helps in managing the data streams and maintaining the synchronization between the transmitter and receiver.
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### Types of TDM
1. **Synchronous TDM**: In synchronous TDM, time slots are pre-assigned to each signal, regardless of whether the signal has data to transmit or not. This can lead to inefficiencies if some time slots remain empty due to the absence of data.
2. **Asynchronous TDM (or Statistical TDM)**: Asynchronous TDM addresses the inefficiencies of synchronous TDM by allocating time slots dynamically based on the presence of data. Time slots are assigned only when there is data to transmit, which optimizes the use of the communication channel.
### Applications of TDM
- **Telecommunications**: TDM is extensively used in telecommunication systems, such as in T1 and E1 lines, where multiple telephone calls are transmitted over a single line by assigning each call to a specific time slot.
- **Digital Audio and Video Broadcasting**: TDM is used in broadcasting systems to transmit multiple audio or video streams over a single channel, ensuring efficient use of bandwidth.
- **Computer Networks**: TDM is used in network protocols and systems to manage the transmission of data from multiple sources over a single network medium.
### Advantages of TDM
- **Efficient Use of Bandwidth**: TDM all
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1. Input/Output Organization 1
Overview
Peripheral Devices
Input-Output Interface
Asynchronous Data Transfer
Modes of Transfer
Priority Interrupt
Direct Memory Access
Input-Output Processor
Serial Communication
2. Input/Output Organization 2
Input Output Organization
– I/O Subsystem
• Provides an efficient mode of communication between the
central system and the outside environment
– Programs and data must be entered into computer memory for
processing and results obtained from computer must be
recorded and displayed to user.
– When input transferred via slow keyboard processor will be idle
most of the time waiting for information to arrive
– Magnetic tapes, disks
3. Input/Output Organization 3
Peripheral Devices
• Devices that are under direct control of computer are said to be
connected on-line.
• Input or output devices attached to the computer are also called
peripherals.
• There are three types of peripherals :
• Input peripherals
• Output peripherals
• Input-output peripherals
Peripheral (or I/O Device)
Monitor (Visual Output Device) : CRT, LCD
KeyBoard (Input Device) : light pen, mouse, touch screen, joy stick, digitizer
Printer (Hard Copy Device) : Daisy wheel, dot matrix and laser printer
Storage Device : Magnetic tape, magnetic disk, optical disk
5. Input/Output Organization 5
Input Output Organization
ASCII (American Standard Code for Information Interchange)
• I/O communications usually involves transfer of alphanumeric
information from the device and the computer.
• Standard binary code for alphanumeric character is ASCII
• ASCII Code :
• It uses 7 bits to code 128 characters (94 printable and 34 non printing)
• 7 bit - 00 - 7F ( 0 - 127 )
• ASCII is 7 bits but most computers manipulate 8 bit quantity as a
single unit called byte.
80 - FF ( 128 - 255 ) : Greek, Italic type font
•Three types of control characters: Format effectors, Information
separators and communication control
6.
7.
8. • Format Effectors: control the layout of
printing. They include familiar typewriter
controls, such as backspace (BS), horizontal
tabulation(HT), carriage return(CR).
• Information separators: used to separate data
into divisions like paragraphs and pages. They
include characters such as record separator
(RS) and file separator(FS).
• Communication Control characters: these are
useful during the transmission of text
between remote terminals. These include
STX(Start of text) and ETX(end of text)
9. Input/Output Organization 9
I/O Interface
• Provides a method for transferring information between internal
storage (such as memory and CPU registers) and external I/O
devices
• Resolves the differences between the computer and peripheral
devices
(1). Peripherals – Electromechanical or Electromagnetic Devices
CPU or Memory - Electronic Device
– Conversion of signal values required
(2). Data Transfer Rate
• Peripherals - Usually slower
• CPU or Memory - Usually faster than peripherals
– Some kinds of Synchronization mechanism may be needed
(3). Data formats or Unit of Information
• Peripherals – Byte, Block, …
• CPU or Memory – Word
(4). Operating modes of peripherals may differ
• must be controlled so that not to disturbed other peripherals connected to CPU
10. Input/Output Organization 10
I/O Bus and Interface
Interface :
- Decodes the device address (device code)
- Decodes the commands (operation)
- Provides signals for the peripheral controller
- Synchronizes the data flow and supervises
the transfer rate between peripheral and CPU or Memory
Processor
Interface
Keyboard
and
display
terminal
Magnetic
tape
Printer
Interface Interface Interface
Data
Address
Control
Magnetic
disk
I/O bus
4 types of command interface can receive : control, status, data o/p and data i/p
11. Input/Output Organization 11
I/O Bus and Interface
•Control command : is issued to activate peripheral and to inform what to do
•Status command : used to test various status condition in the interface and
the peripherals
•data o/p command : causes the interface to respond by transferring data from
the bus into one of its registers
•data i/p command : interface receives an item of data from the peripheral and
places it in its buffer register.
12. Input/Output Organization 12
I/O Bus and Memory Bus
• MEMORY BUS is for information transfers between CPU and the MM
• I/O BUS is for information transfers between CPUand I/O devices through
their I/O interface
•3 ways to bus can communicate with memory and I/O :
(1). use two separate buses, one to communicate with memory and the
other with I/O interfaces
- Computer has independent set of data, address and control bus one for
accessing memory and another I/O.
- done in computers that have separate IOP other than CPU.
(2). Use one common bus for memory and I/O but separate control lines
for each
(3). Use one common bus for memory and I/O with common control
lines for both
Functions of Buses
13. Input/Output Organization 13
Isolated vs. Memory Mapped I/O
- Many computers use common bus to transfer information between
memory or I/O.
- The distinction between memory transfer and I/O transfer is made
through separate read and write line.
-In the isolated I/O configuration , the CPU has distinct input and output
instructions and each of these instruction is associated with the
address of an interface register.
-Distinct input and output instructions -each associated with address of interface
register
Isolated I/O
Memory-mapped I/O
- A single set of read/write control lines
(no distinction between memory and I/O transfer)
- Memory and I/O addresses share the common address space
-> reduces memory address range available
- No specific input or output instruction
-> The same memory reference instructions can
be used for I/O transfers
- Considerable flexibility in handling I/O operations
14. Input/Output Organization 14
I/O Interface
- Information in each port can be assigned a meaning depending on the mode of operation of the
I/O device→ Port A = Data; Port B = Command;
- CPU initializes(loads) each port by transferring a byte to the Control Register
→ Allows CPU can define the mode of operation of each port
→ Programmable Port: By changing the bits in the control register, it is possible to change the
interface characteristics
CS RS1 RS0 Register selected
0 x x None - data bus in high-impedence
1 0 0 Port A register
1 0 1 Port B register
1 1 0 Control register
1 1 1 Status register
Programmable Interface
Chip select
Register select
Register select
I/O read
I/O write
CS
RS1
RS0
RD
WR
Timing
and
Control
Bus
buffers
Bidirectional
data bus
Port A
register
Port B
register
Control
register
Status
register
I/O data
I/O data
Control
Status
CPU I/O
Device
15. Input/Output Organization 15 Lecture 36
Peripheral Devices
Input-Output Interface
Asynchronous Data Transfer
Modes of Transfer
Priority Interrupt
Direct Memory Access
Input-Output Processor
16. 11-3. Asynchronous Data Transfer
Synchronous Data Transfer: Clock pulses are applied to all registers
within a unit and all data transfer among internal registers occur
simultaneously during the occurrence of a clock pulse. Two units such
as CPU and I/O Interface are designed independently of each other. If
the registers in the interface share a common clock with CPU registers,
the transfer between the two is said to be synchronous.
Asynchronous Data Transfer: Internal timing in each unit (CPU and
Interface) is independent. Each unit uses its own private clock for
internal registers. Asynchronous data transfer between two
independent units requires that control signals be transmitted
between the communicating units to indicate the time at which data is
being transmitted. One way of achieving this is by means of
STROBE(Control signal to indicate the time at which data is being
transmitted) pulse and other method is HANDSHAKING(Agreement
between two independent units).
21. Timeout : If the return handshake signal does not respond within a given time period,
the unit assumes that an error has occurred.
22. – Asynchronous Serial Transfer
• Synchronous transmission :
– The two unit share a common clock frequency
– Bits are transmitted continuously at the rate dictated by the clock
pulses
• Asynchronous transmission :
– Binary information sent only when it is available and line remain
idle otherwise
– Special bits are inserted at both ends of the character code
– Each character consists of three parts :
» 1) start bit : always “0”, indicate the beginning of a character
» 2) character bits : data
» 3) stop bit : always “1”
1 1 11 0000
Start
bit
Character bits
Stop
bit
23. • Asynchronous transmission rules :
– When a character is not being sent, the line is kept in the 1-state
– The initiation of a character transmission is detected from the
start bit, which is always “0”
– The character bits always follow the start bit
– After the last bit of the character is transmitted, a stop bit is
detected when the line returns to the 1-state for at least one bit
time
• Baud Rate : Data transfer rate in bits per second
– 10 character per second with 11 bit format = 110 bit per second
24. Input/Output Organization 24
Universal Asynchronous Receiver Transmitter
A typical asynchronous communication interface available as an IC
Transmitter Register
- Accepts a data byte(from CPU) through the data bus
- Transferred to a shift register for serial transmission
Receiver Register
- Receives serial information into another shift register
- Complete data byte is sent to the receiver register
Status Register Bits
- Used for I/O flags and for recording errors
Control Register Bits
- Define baud rate, no. of bits in each character, whether to generate and check parity, and no. of
stop bits
Chip select
I/O read
I/O write
CS
RS
RD
WR
Timing
and
Control
Bus
buffers
Bidirectional
data bus
Transmitter
register
Control
register
Status
register
Receiver
register
Shift
register
Transmitter
control
and clock
Receiver
control
and clock
Shift
register
Transmit
data
Transmitter
clock
Receiver
clock
Receive
data
CS RS Oper. Register selected
0 x x None
1 0 WR Transmitter register
1 1 WR Control register
1 0 RD Receiver register
1 1 RD Status register
InternalBus
25. Overview
Peripheral Devices
Input-Output Interface
Asynchronous Data Transfer
Modes of Transfer
Priority Interrupt
Direct Memory Access
Input-Output Processor
26. Binary information received from external device is usually
stored in memory.
Information transferred from central computer into an external
device originates in the memory unit.
The CPU merely execute I/O instructions and may accept data
temporarily but ultimate source or destination is the Memory Unit.
Data transfer between central computer and I/O devices may be
handled in a variety of modes. Some modes use CPU as
intermediate path and others transfer data directly to and from
memory unit.
Data Transfer to or from peripheral can be handled in one of
three possible modes :
Programmed I/O
Interrupt-Initiated I/O
Direct Memory Access (DMA)
Modes of Transfer
29. Programmed I/O
- Programmed I/O operations are the result of I/O
Instructions written in computer program. Each data item
transfer is initiated by an instruction in the program.
- Usually, transfer is to and from a CPU register to
peripheral. Other instructions are needed to transfer data
to and from CPU and Memory
- Transferring data under program control requires
constant monitoring of the peripheral by CPU.
30. • In programmed I/O method, CPU stays in a
program loop until the I/O unit indicated that it is
ready for data transfer. This is a time consuming
process since it keeps the processor busy
needlessly. It can be avoided by using Interrupt
facility and special commands to inform the
interface to issue an interrupt request signal when
data are available for the device.
33. Priority Interrupts
Priority
- Determines which interrupt is to be served first when two or more requests
are made simultaneously
- Also determines which interrupts are permitted to interrupt the computer while
another is being serviced
- Higher priority interrupts can make requests while servicing a lower priority
interrupt
A priority interrupt is a system that establishes priority over the
various sources to determine
- which condition is to serviced first when two or more requests
arrive simultaneously
-which conditions are permitted to interrupt the computer while
another request is being serviced
34. Priority Interrupts
Priority Interrupt by Software (Polling)
Polling procedure is used to identify highest priority source by software
means
- common branch address for all the interrupts
- Priority is established by the order of polling the devices(interrupt sources)
- highest priority device is tested first and if interrupt is on , control
branches to service routine for this source otherwise next lower priority
source is tested
- Flexible since it is established by software
- Low cost since it needs a very little hardware
- Very slow
- if there are many interrupt time required to poll may exceed time available to
service IO device
35. Priority Interrupts
Priority Interrupt by Hardware
- Require a priority interrupt manager which accepts all the interrupt requests
to determine the highest priority request
- Fast since identification of the highest priority interrupt request is identified by
the hardware
- Fast since each interrupt source has its own interrupt vector to access
directly to its own service routine
- Can be addressed using serial or parallel connection of interrupt lines.
Example of serial is Daisy chaining Priority
36. Hardware Priority Interrupts – Daisy Chain
Device 1
PI PO
Device 2
PI PO
Device 3
PI PO
INT
INTACK
Interrupt request
Interrupt acknowledge
To next
device
CPU
VAD 1 VAD 2 VAD 3
* Serial hardware priority function
* Interrupt Request Line
- Single common line
* Interrupt Acknowledge Line
- Daisy-Chain
-Serial connection of all device that request an interrupt
-Device with highest priority placed in first position followed by devices with lower
priority and so on.
-Interrupt generated by any device signals low state interrupt line
-CPU responds by enabling interrupt acknowledgement (INTACK) line.
- device receives PI=1 and passes to next only when not requesting else PI=0
-Thus device with PI=1 and PO=0 is one with highest priority requesting interrupt
39. Parallel Priority Interrupts
Mask
register
INTACK
from CPU
Priority
encoder
I0
I1
I 2
I 3
0
1
2
3
y
x
ISTIEN0
1
2
3
0
0
0
0
0
0
Disk
Printer
Reader
Keyboard
Interrupt register
Enable
Interrupt
to CPU
VAD
to CPU
Bus
Buffer
IEN: Set or Clear by instructions ION or IOF
IST: Represents an unmasked interrupt has occurred. INTACK enables tristate Bus Buffer to load VAD generated
by the Priority Logic
Interrupt Register:
- Each bit is associated with an Interrupt Request from different Interrupt Source - different priority level
- Each bit can be cleared by a program instruction
Mask Register:
- Mask Register is associated with Interrupt Register
- Each bit can be set or cleared by an Instruction
40. Priority Encoder
Determines the highest priority interrupt when more than one
interrupts take place
Priority Encoder Truth table
1 d d d
0 1 d d
0 0 1 d
0 0 0 1
0 0 0 0
I0 I1 I2 I3
0 0 1
0 1 1
1 0 1
1 1 1
d d 0
x y IST
x = I0' I1'
y = I0' I1 + I0’ I2’
(IST) = I0 + I1 + I2 + I3
Inputs Outputs
Boolean functions
41. Interrupt Cycle
At the end of each Instruction cycle
- CPU checks IEN and IST
- If IEN IST = 1, CPU -> Interrupt Cycle
SP SP - 1 Decrement stack pointer
M[SP] PC Push PC into stack
INTACK 1 Enable interrupt acknowledge
PC VAD Transfer vector address to PC
IEN 0 Disable further interrupts
Go To Fetch to execute the first instruction
in the interrupt service routine
42. Initial and Final Operations
JMP PTR
JMP RDR
JMP KBD
JMP DISK0
1
2
3
Program to service
magnetic disk
Program to service
line printer
Program to service
character reader
Program to service
keyboard
DISK
PTR
RDR
KBD
255
256
750
256
750
Stack
Main program
current instr.749
KBD
interrupt
2
VAD=00000011 3
4
Disk
interrupt
5
6
7
8
9 10
11
1
Initial and Final Operations
Each interrupt service routine must have an initial and final set of
operations for controlling the registers in the hardware interrupt system
Initial Sequence
[1] Clear lower level Mask reg. bits
[2] IST <- 0
[3] Save contents of CPU registers
[4] IEN <- 1
[5] Go to Interrupt Service Routine
Final Sequence
[1] IEN <- 0
[2] Restore CPU registers
[3] Clear the bit in the Interrupt Reg
[4] Set lower level Mask reg. bits
[5] Restore return address, IEN <- 1
43. Input/Output Organization 43
Overview
Peripheral Devices
Input-Output Interface
Asynchronous Data Transfer
Modes of Transfer
Priority Interrupt
Direct Memory Access
Input-Output Processor
44.
45. Input/Output Organization 45
Direct Memory Access
Data bus
Read
Write
ABUS
DBUS
RD
WR
Bus request
Bus granted
BR
BG
CPU
Data bus
DMA select
Read
Write
Bus request
Bus grant
Interrupt
DS
RS
RD
WR
BR
BG
Interrupt
Data bus
buffers
Address bus
buffers
Address register
Word count register
Control register
DMA request
DMA acknowledge to I/O device
Control
logic
InternalBus
Fig 2: Block diagram of DMA controller
* Block of data transfer between high speed devices like Disk and Memory
* DMA controller - Interface which takes over the buses to manage the transfer directly between
Memory and I/O Device, freeing CPU for other tasks
* CPU initializes DMA Controller by sending memory address and the block size (number of words)
Fig 1: CPU bus signals for DMA transfer
Address bus
Address register:
Contains an address to specify
Desired location in memory
Word count register
Holds no. of words to be transferred
Control register
Specifies the mode of transfer
46. Input/Output Organization 46
DMA Transfer can be made in several ways
(1) Burst Transfer : a block sequence consisting of memory words is transferred
in continuous burst while the DMA controller is master of memory
bus
- This mode of transfer is needed for fast devices such as magnetic
disk where data transmission cannot be stopped or slowed down
until an entire block is transferred
(2) Cycle stealing : Alternative technique called cycle stealing allows DMA controller to
transfer one data word at time after which it must return control of
the buses to the CPU.
- CPU merely delays its operation for one memory cycle to allow the
direct memory I/O transfer to “steal” one memory cycle
Direct Memory Access
RD and WR is bidirectional
When BG=0 CPU can communicate with DMA Register
When BG=1 CPU left the buses and DMA can communicate directly with memory
47. Input/Output Organization 47
DMA I/O Operation
DMA is first initialized by CPU. After that DMA starts and continues to transfer data
between memory and peripheral unit until an entire block is transferred.
CPU initializes the DMA by sending following information through data bus:
(1) Starting address of the memory block (for read/write)
(2) Word Count (no. of words in memory block)
(3) Control to specify mode of transfer (E.g. read/write)
(4) A control to start DMA Transfer
48. Input/Output Organization 49
DMA Transfer
BG
BR
CPU
RD WR Addr Data
Interrupt
Random-access
memory unit (RAM)
RD WR Addr Data
BR
BG
RD WR Addr Data
Interrupt
DS
RS DMA
Controller
I/O
Peripheral
device
DMA request
DMA ack.
Read control
Write control
Data bus
Address bus
Address
select
49. Input/Output Organization 50
I/O Processor - Channel
Channel
- Processor with direct memory access capability that communicates with I/O devices
- Channel accesses memory by cycle stealing
- Unlike DMA Controller, IOP can fetch and execute its own instruction
- IOP Instructions (Commands) specially designed to facilitate I/O transfer.
- Data gathered in IOP at device rate and bit capacity while CPU executing own program
- Transfer between IOP and Device similar to Programmed I/O and
transfer between IOP and Memory similar to DMA
- CPU is master while IOP is slave processor
- CPU initiates the channel by executing a channel I/O class instruction and once initiated,
channel operates independent of the CPU
PD PD PD PD
Peripheral devices
I/O bus
Input-output
processor
(IOP)
Central
processing
unit (CPU)
Memory
unit
MemoryBus
50. Input/Output Organization 51
Channel CPU Communication
Send instruction
to test IOP.path
If status OK, then send
start I/O instruction
to IOP.
CPU continues with
another program
Transfer status word
to memory
Access memory
for IOP program
Conduct I/O transfers
using DMA;
Prepare status report.
I/O transfer completed;
Interrupt CPU
Request IOP status
Transfer status word
to memory locationCheck status word
for correct transfer.
Continue
CPU operations IOP operations