The document discusses input/output organization and accessing I/O devices. There are three key components to a computer system: the processor, memory, and I/O modules. I/O modules interface between peripheral devices and the system bus, controlling the transfer of data. I/O modules perform functions like control and timing, processor/device communication, data buffering, and error detection to facilitate input and output.

1. INPUT/OUTPUT
ORGANIZATION
2013BTECHCSE005 –ANKIT RAO
2013BTMTECH003 - SHIVANK SINGH
2013BTMTECH002- RAJDEEP SHARMA
2014BTECHCSE151 –SHIVANGI GRAG

2. INPUT/OUTPUT ORGANIZATION
Accessing I/O DEVICES
The computer system's input/output (I/O) architecture is its interface to the
outside world.
● Till now we have discussed the two important modules of the computer
system -
❍ The processor and
❍ The memory.
● The third key component of a computer system is a set of I/O modules
● Each I/O module interfaces to the system bus and controls one or more
peripheral devices.

3. 1. There are several reasons why an I/O device or peripheral device is
not directly connected to the system bus.
2. Some of them are as follows -
● There are a wide variety of peripherals with various methods of
operation. It would be impractical to include the necessary logic
within the processor to control several devices.
● The data transfer rate of peripherals is often much slower than
that of the memory or processor. Thus, it is impractical to use the high-
speed system bus to communicate directly with a peripheral.
● Peripherals often use different data formats and word lengths
than the computer to which they are attached.
--> Thus, an I/O module is required.

4. The major functions of an I/O module are
categorized as follows –
 ❍ Control and timing
 ❍ Processor Communication
 ❍ Device Communication
 ❍ Data Buffering
 ❍ Error Detection

5. CPU Communication:
 Processor sends commands to the I/O system which are generally the control
signals on the control bus.
 Exchange of data between the processor and the I/O interface over the data
bus.
 Check whether the devices are ready or not.
Processor & Device Communication:
 During the I/O operation, the I/O module must communicate with the
processor and with the external device.
 The I/O must be able to perform device communication. This
communication involves command, status information and data.

6. Data Buffering:
 Data transfer rate is too high .
 Data from processor and memory are sent to an I/O interface, buffered and
then sent to the peripheral device at its data rate.
Error Detection:
 I/O interface is responsible for error detection
 Used to report errors to the processor.
 Types of errors:
 Mechanical, electrical malfunctions, bad disk track, unintentional changes.

7. MAPPING
Memory And I/O Addressing
 Set of all possible addresses that can be generated by CPU is called address
space. CPU can directly address all the addresses of it’s address space
 Memory addressing capacity depends upon number of address lines in CPU
 E.g. 8086 intel microprocessor has 20 address lines and can address 1MB of
memory directly using 20 bit address bus
 Thus 1mb is the address space of INTEL 8086 microprocessor

8. Two Methods Of Mapping
There are two techniques for addressing an I/O
device by CPU:
 Memory mapped I/O
 I/O mapped I/O (Standard I/O or Isolated I/O or
port I/O)

9. ISOLATED I/O
 Here two separate address spaces are used - one for memory location
and other for I/O devices.
 The I/O devices are provided dedicated address space.
 Hence there are two separate control lines for memory and I/O transfer.
I/O read and I/O write lines for I/O transfer
Memory Write and Memory Read for memory transfer
 Hence IN and OUT instruction deals with I/O transfer and MOV with
memory transfer.

10. MEMORY MAPPED I/O
 The technique in which CPU addresses an I/O device just like a memory
location is called memory mapped I/O scheme.
 In this scheme only one address space is used by CPU. Some addresses
of the address space are assigned to memory location and other are
assigned to I/O devices.
 There is only one set of read and write lines. Hence there is no separate
IN,OUT instructions. MOVE instruction can be used to accomplish both
the transfer.
 The instructions used to manipulate the memory can be used for I/O
devices.

11. ISOLATED Vs. MEMORY MAPPED
I/O
ISOLATED I/O MEMORY MAPPEED I/O

12. IN INTEL 8086
 8086 has both memory mapped and I/O mapped I/O. The video RAM are memory
mapped where as the Keyboard , Counter and Other devices are I/O Mapped.
 To distinguish between the memory read/write and I/O read or write, M/IO signal
is used.
• If M/IO =1, it indicates that the address present in address bus is the address of an
I/O device.
• if M/IO=0, it indicates that the address present in address bus is the address of a
memory location
 Intel 8080,zilog z80,8088 - I/O mapped I/O
 Pentium processors mostly use the isolated I/O method but provides both
schemes and Motorola 68000-uses memory mapped I/O
 IBM pc use both memory mapped I/O and I/O mapped I/O

13. I/O Mapped I/O
Advantages
 1 MB memory address space is available for use with
memory.
 Special Instructions for I/O operations maximize I/O
performance.
 Used in system where complete memory capacity is
required
Disadvantages
 Data has to be transferred to the accumulator (any one of the internal
register ) to perform arithmetic and logic operation

14. Advantages
 All I/O locations are addressed in exactly the same manner as memory
locations; no special repertoire of I/O instructions is therefore .Thus the overall
size of the instruction set is reduced.
 All arithmetic and logical operations can be performed on I/O data directly
 Used in system where memory requirement is small
Disadvantages
 Part of the memory address space is lost. (however, that with ported I/O
systems, not all of the available I/O address space is always used.)
MEMORY MAPPED I/O

15. Input output subsystem

16. Programmed I/O:
Under direct control of CPU.
Interrupt I/O:
During initiation, CPU inform interface
At end interface interrupts CPU.
DMA:
CPU doesn’t come into the picture at all.

17. INTERRUPT
• PRIORITY
• DAISY
CHAINING

18. DAISY CHAINING

19. DMA

20. ERROR DETECTION:
HAMMING CODE
 We introduce additional bit in a data stream.
 Odd parity has an XOR 1
 Even parity has an XOR 0

21. CRC Code
Cycle
redundancy
check-
Chunk of data
Code length
depends on
generating
polynomial.
Shift registers
and XOR gates
are used.

22. BUSES
 In computer architecture, a bus (related to the Latin “omnibus",
meaning "for all") is a communication system that transfers data
between components inside a computer, or between computers.
This expression covers all related hardware components (wire,
optical fibre , etc.) and software, including communication
protocols.

23.  Bus lines may be grouped into three types:
 Data
 Address
 Control
 Control signals specify:
 Whether it is a read or a write operation.
 Required size of the data, when several operand sizes (byte, word, long
word) are possible.
 Timing information to indicate when the processor and I/O devices may
place data or receive data from the bus.
 Schemes for timing of data transfers over a bus can be classified
into:
 Synchronous,
 Asynchronous.

24. Synchronous Bus
 In a synchronous bus, all the devices are synchronised by a
common clock, so all devices derive timing information from a
common clock line of the bus. A clock pulse on this common clock
line defines equal time intervals.
 In the simplest form of a synchronous bus, each of these clock pulse
constitutes a bus cycle during which one data transfer can take
place.

25. Asynchronous Bus
 In asynchronous mode of transfer, a handshake signal is used between master and slave.
 In asynchronous bus, there is no common clock, and the common clock signal is replaced
by two timing control signals: master-ready and slave-ready. Master-
ready signal is assured by the master to indicate that it is ready for a transaction, and slave-
ready signal is a response from the slave.
 The handshaking protocol proceeds as follows:
● The master places the address and command information on the bus.
Then it indicates to all devices that it has done so by activating the master-ready signal.
● This causes all devices on the bus to decode the address.
● The selected target device performs the required operation and inform the
processor (or master) by activating the slave-ready line.
● The master waits for slave-ready to become asserted before it remove its signals from
the bus.
● In case of a read operation, it also strobes the data into its input buffer.

26. Asynchronous vs. Synchronous bus
 Advantages of asynchronous bus:
 Eliminates the need for synchronization between the sender and the
receiver.
 Can accommodate varying delays automatically, using the Slave-
ready signal.
 Disadvantages of asynchronous bus:
 Data transfer rate with full handshake is limited by two-round trip delays.
 Data transfers using a synchronous bus involves only one round trip
delay, and hence a synchronous bus can achieve faster rates.